hdl: Move mezzanine related wb cores to a separate module.

The new module contains another wb crossbar. Therefore the memory mapping has changed. This has been done for the future svec design with two fmc slots.

hdl: Move mezzanine related wb cores to a separate module.
The new module contains another wb crossbar. Therefore the memory mapping has changed. This has been done for the future svec design with two fmc slots.
54eef437 · Matthieu Cattin · a9bf5a62 · 54eef437 · 54eef437 · 54eef437
Commit 54eef437 authored Jul 04, 2013 by Matthieu Cattin
7 changed files
--- a/hdl/adc/rtl/Manifest.py
+++ b/hdl/adc/rtl/Manifest.py
-files = ["fmc_adc_100Ms_core.vhd",
-         "fmc_adc_100Ms_core_pkg.vhd",
-         "fmc_adc_100Ms_csr.vhd",
-         "offset_gain_s.vhd"]
+files = [
+    "fmc_adc_mezzanine.vhd",
+    "fmc_adc_mezzanine_pkg.vhd",
+    "fmc_adc_100Ms_core.vhd",
+    "fmc_adc_100Ms_core_pkg.vhd",
+    "fmc_adc_100Ms_csr.vhd",
+    "offset_gain_s.vhd"]
--- a/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
 --------------------------------------------------------------------------------
 -- CERN (BE-CO-HT)
-- Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
+-- FMC ADC 100Ms/s core package
+-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
 --------------------------------------------------------------------------------
 --
 -- unit name: fmc_adc_100Ms_core_pkg (fmc_adc_100Ms_core_pkg.vhd)

--- a/hdl/adc/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/adc/rtl/fmc_adc_mezzanine.vhd
+--------------------------------------------------------------------------------
+-- CERN (BE-CO-HT)
+-- FMC ADC mezzanine
+-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
+--------------------------------------------------------------------------------
+--
+-- unit name: fmc_adc_mezzanine (fmc_adc_mezzanine.vhd)
+--
+-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--
+-- date: 07-05-2013
+--
+-- description: The FMC ADC mezzanine is wrapper around the fmc-adc-100ms core and
+--              the other wishbone slaves connected to a FMC ADC mezzanine.
+--
+-- dependencies:
+--
+-- references:
+--
+--------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--------------------------------------------------------------------------------
+-- last changes: see git log.
+--------------------------------------------------------------------------------
+-- TODO: - 
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+library work;
+use work.fmc_adc_100Ms_core_pkg.all;
+use work.wishbone_pkg.all;
+
+
+entity fmc_adc_mezzanine is
+  generic(
+    g_multishot_ram_size : natural := 2048
+    );
+  port (
+    -- Clock, reset
+    sys_clk_i   : in std_logic;
+    sys_rst_n_i : in std_logic;
+
+    -- CSR wishbone interface
+    wb_csr_adr_i   : in  std_logic_vector(31 downto 0);
+    wb_csr_dat_i   : in  std_logic_vector(31 downto 0);
+    wb_csr_dat_o   : out std_logic_vector(31 downto 0);
+    wb_csr_cyc_i   : in  std_logic;
+    wb_csr_sel_i   : in  std_logic_vector(3 downto 0);
+    wb_csr_stb_i   : in  std_logic;
+    wb_csr_we_i    : in  std_logic;
+    wb_csr_ack_o   : out std_logic;
+    wb_csr_stall_o : out std_logic;
+
+    -- DDR wishbone interface
+    wb_ddr_clk_i   : in  std_logic;
+    wb_ddr_adr_o   : out std_logic_vector(31 downto 0);
+    wb_ddr_dat_o   : out std_logic_vector(63 downto 0);
+    wb_ddr_sel_o   : out std_logic_vector(7 downto 0);
+    wb_ddr_stb_o   : out std_logic;
+    wb_ddr_we_o    : out std_logic;
+    wb_ddr_cyc_o   : out std_logic;
+    wb_ddr_ack_i   : in  std_logic;
+    wb_ddr_stall_i : in  std_logic;
+
+    -- Events output pulses (for interrupt and time-stamping)
+    trigger_p_o   : out std_logic;
+    acq_start_p_o : out std_logic;
+    acq_stop_p_o  : out std_logic;
+    acq_end_p_o   : out std_logic;
+
+    -- FMC interface
+    ext_trigger_p_i : in std_logic;     -- External trigger
+    ext_trigger_n_i : in std_logic;
+
+    adc_dco_p_i  : in std_logic;                     -- ADC data clock
+    adc_dco_n_i  : in std_logic;
+    adc_fr_p_i   : in std_logic;                     -- ADC frame start
+    adc_fr_n_i   : in std_logic;
+    adc_outa_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (odd bits)
+    adc_outa_n_i : in std_logic_vector(3 downto 0);
+    adc_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
+    adc_outb_n_i : in std_logic_vector(3 downto 0);
+
+    gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
+    gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
+    gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
+    gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
+    gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
+    gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
+    gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
+    gpio_si570_oe_o  : out std_logic;                     -- Si570 (programmable oscillator) output enable
+
+    spi_din_i       : in  std_logic;    -- SPI data from FMC
+    spi_dout_o      : out std_logic;    -- SPI data to FMC
+    spi_sck_o       : out std_logic;    -- SPI clock
+    spi_cs_adc_n_o  : out std_logic;    -- SPI ADC chip select (active low)
+    spi_cs_dac1_n_o : out std_logic;    -- SPI channel 1 offset DAC chip select (active low)
+    spi_cs_dac2_n_o : out std_logic;    -- SPI channel 2 offset DAC chip select (active low)
+    spi_cs_dac3_n_o : out std_logic;    -- SPI channel 3 offset DAC chip select (active low)
+    spi_cs_dac4_n_o : out std_logic;    -- SPI channel 4 offset DAC chip select (active low)
+
+    si570_scl_b : inout std_logic;      -- I2C bus clock (Si570)
+    si570_sda_b : inout std_logic;      -- I2C bus data (Si570)
+
+    mezz_one_wire_b : inout std_logic;  -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
+
+    sys_scl_b : inout std_logic;        -- Mezzanine system I2C clock (EEPROM)
+    sys_sda_b : inout std_logic         -- Mezzanine system I2C data (EEPROM)
+    );
+end fmc_adc_mezzanine;
+
+
+architecture rtl of fmc_adc_mezzanine is
+
+  ------------------------------------------------------------------------------
+  -- SDB crossbar constants declaration
+  --
+  -- WARNING: All address in sdb and crossbar are BYTE addresses!
+  ------------------------------------------------------------------------------
+
+  -- Number of master port(s) on the wishbone crossbar
+  constant c_NUM_WB_MASTERS : integer := 5;
+
+  -- Number of slave port(s) on the wishbone crossbar
+  constant c_NUM_WB_SLAVES : integer := 1;
+
+  -- Wishbone master(s)
+  constant c_WB_MASTER : integer := 0;
+
+  -- Wishbone slave(s)
+  constant c_WB_SLAVE_FMC_SYS_I2C : integer := 0;  -- Mezzanine system I2C interface (EEPROM)
+  constant c_WB_SLAVE_FMC_SPI     : integer := 1;  -- Mezzanine SPI interface
+  constant c_WB_SLAVE_FMC_I2C     : integer := 2;  -- Mezzanine I2C controller
+  constant c_WB_SLAVE_FMC_ADC     : integer := 3;  -- Mezzanine ADC core
+  constant c_WB_SLAVE_FMC_ONEWIRE : integer := 4;  -- Mezzanine onewire interface
+
+  -- Devices sdb description
+  constant c_ONEWIRE_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"0000000000000007",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000602",
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-Onewire.Control ")));
+
+  constant c_I2C_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000001F",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000606",
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-I2C.Control     ")));
+
+  constant c_SPI_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000001F",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000607",
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-SPI.Control     ")));
+
+  constant c_ADC_CSR_SDB_DEVICE : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"4",                 -- 32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"000000000000007F",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"00000608",
+        version   => x"00000001",
+        date      => x"20121116",
+        name      => "WB-FMC-ADC-Core    ")));
+
+  -- sdb header address
+  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
+
+  -- Wishbone crossbar layout
+  constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
+    (
+      0 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001000"),
+      1 => f_sdb_embed_device(c_SPI_SDB_DEVICE, x"00001100"),
+      2 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001200"),
+      3 => f_sdb_embed_device(c_ADC_CSR_SDB_DEVICE, x"00001300"),
+      4 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001400")
+      );
+
+
+  ------------------------------------------------------------------------------
+  -- Signals declaration
+  ------------------------------------------------------------------------------
+
+  -- Wishbone buse(s) from crossbar master port(s)
+  signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
+  signal cnx_master_in  : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
+
+  -- Wishbone buse(s) to crossbar slave port(s)
+  signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
+  signal cnx_slave_in  : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
+
+  -- Mezzanine system I2C for EEPROM
+  signal sys_scl_in   : std_logic;
+  signal sys_scl_out  : std_logic;
+  signal sys_scl_oe_n : std_logic;
+  signal sys_sda_in   : std_logic;
+  signal sys_sda_out  : std_logic;
+  signal sys_sda_oe_n : std_logic;
+
+  -- Mezzanine SPI
+  signal spi_din_t : std_logic_vector(3 downto 0);
+  signal spi_ss_t  : std_logic_vector(7 downto 0);
+
+  -- Mezzanine I2C for Si570
+  signal si570_scl_in   : std_logic;
+  signal si570_scl_out  : std_logic;
+  signal si570_scl_oe_n : std_logic;
+  signal si570_sda_in   : std_logic;
+  signal si570_sda_out  : std_logic;
+  signal si570_sda_oe_n : std_logic;
+
+  -- Mezzanine 1-wire
+  signal mezz_owr_en    : std_logic_vector(0 downto 0);
+  signal mezz_owr_i     : std_logic_vector(0 downto 0);
+
+
+begin
+
+  ------------------------------------------------------------------------------
+  -- CSR wishbone crossbar
+  ------------------------------------------------------------------------------
+  cmp_sdb_crossbar : xwb_sdb_crossbar
+    generic map (
+      g_num_masters => c_NUM_WB_SLAVES,
+      g_num_slaves  => c_NUM_WB_MASTERS,
+      g_registered  => true,
+      g_wraparound  => true,
+      g_layout      => c_INTERCONNECT_LAYOUT,
+      g_sdb_addr    => c_SDB_ADDRESS)
+    port map (
+      clk_sys_i => sys_clk_i,
+      rst_n_i   => sys_rst_n_i,
+      slave_i   => cnx_slave_in,
+      slave_o   => cnx_slave_out,
+      master_i  => cnx_master_in,
+      master_o  => cnx_master_out);
+
+  -- Connect crossbar slave port to entity port
+  cnx_slave_in(c_WB_MASTER).adr <= wb_csr_adr_i;
+  cnx_slave_in(c_WB_MASTER).dat <= wb_csr_dat_i;
+  cnx_slave_in(c_WB_MASTER).sel <= wb_csr_sel_i;
+  cnx_slave_in(c_WB_MASTER).stb <= wb_csr_stb_i;
+  cnx_slave_in(c_WB_MASTER).we  <= wb_csr_we_i;
+  cnx_slave_in(c_WB_MASTER).cyc <= wb_csr_cyc_i;
+
+  wb_csr_dat_o   <= cnx_slave_out(c_WB_MASTER).dat;
+  wb_csr_ack_o   <= cnx_slave_out(c_WB_MASTER).ack;
+  wb_csr_stall_o <= cnx_slave_out(c_WB_MASTER).stall;
+
+  ------------------------------------------------------------------------------
+  -- Mezzanine system managment I2C master
+  --    Access to mezzanine EEPROM
+  ------------------------------------------------------------------------------
+  cmp_fmc_sys_i2c : xwb_i2c_master
+    generic map(
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE
+      )
+    port map (
+      clk_sys_i => sys_clk_i,
+      rst_n_i   => sys_rst_n_i,
+
+      slave_i => cnx_master_out(c_WB_SLAVE_FMC_SYS_I2C),
+      slave_o => cnx_master_in(c_WB_SLAVE_FMC_SYS_I2C),
+      desc_o  => open,
+
+      scl_pad_i    => sys_scl_in,
+      scl_pad_o    => sys_scl_out,
+      scl_padoen_o => sys_scl_oe_n,
+      sda_pad_i    => sys_sda_in,
+      sda_pad_o    => sys_sda_out,
+      sda_padoen_o => sys_sda_oe_n
+      );
+
+  -- Tri-state buffer for SDA and SCL
+  sys_scl_b  <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
+  sys_scl_in <= sys_scl_b;
+
+  sys_sda_b  <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
+  sys_sda_in <= sys_sda_b;
+
+  ------------------------------------------------------------------------------
+  -- Mezzanine SPI master
+  --    Offset DACs control
+  --    ADC control
+  ------------------------------------------------------------------------------
+  cmp_fmc_spi : xwb_spi
+    generic map(
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE
+      )
+    port map (
+      clk_sys_i => sys_clk_i,
+      rst_n_i   => sys_rst_n_i,
+
+      slave_i => cnx_master_out(c_WB_SLAVE_FMC_SPI),
+      slave_o => cnx_master_in(c_WB_SLAVE_FMC_SPI),
+      desc_o  => open,
+
+      pad_cs_o   => spi_ss_t,
+      pad_sclk_o => spi_sck_o,
+      pad_mosi_o => spi_dout_o,
+      pad_miso_i => spi_din_t(spi_din_t'left)
+      );
+
+  -- Assign slave select lines
+  spi_cs_adc_n_o  <= spi_ss_t(0);
+  spi_cs_dac1_n_o <= spi_ss_t(1);
+  spi_cs_dac2_n_o <= spi_ss_t(2);
+  spi_cs_dac3_n_o <= spi_ss_t(3);
+  spi_cs_dac4_n_o <= spi_ss_t(4);
+
+  -- Add some FF after the input pin to solve timing problem
+  p_fmc_spi : process (sys_clk_i)
+  begin
+    if rising_edge(sys_clk_i) then
+      if sys_rst_n_i = '0' then
+        spi_din_t <= (others => '0');
+      else
+        spi_din_t <= spi_din_t(spi_din_t'left-1 downto 0) & spi_din_i;
+      end if;
+    end if;
+  end process p_fmc_spi;
+
+  ------------------------------------------------------------------------------
+  -- Mezzanine I2C
+  --    Si570 control
+  --
+  -- Note: I2C registers are 8-bit wide, but accessed as 32-bit registers
+  ------------------------------------------------------------------------------
+  cmp_fmc_i2c : xwb_i2c_master
+    generic map(
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE
+      )
+    port map (
+      clk_sys_i => sys_clk_i,
+      rst_n_i   => sys_rst_n_i,
+
+      slave_i => cnx_master_out(c_WB_SLAVE_FMC_I2C),
+      slave_o => cnx_master_in(c_WB_SLAVE_FMC_I2C),
+      desc_o  => open,
+
+      scl_pad_i    => si570_scl_in,
+      scl_pad_o    => si570_scl_out,
+      scl_padoen_o => si570_scl_oe_n,
+      sda_pad_i    => si570_sda_in,
+      sda_pad_o    => si570_sda_out,
+      sda_padoen_o => si570_sda_oe_n
+      );
+
+  -- Tri-state buffer for SDA and SCL
+  si570_scl_b  <= si570_scl_out when si570_scl_oe_n = '0' else 'Z';
+  si570_scl_in <= si570_scl_b;
+
+  si570_sda_b  <= si570_sda_out when si570_sda_oe_n = '0' else 'Z';
+  si570_sda_in <= si570_sda_b;
+
+  ------------------------------------------------------------------------------
+  -- ADC core
+  --    Solid State Relays control
+  --    Si570 output enable
+  --    Offset DACs control (CLR_N)
+  --    ADC core control and status
+  ------------------------------------------------------------------------------
+  cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
+    generic map (
+      g_multishot_ram_size => g_multishot_ram_size
+      )
+    port map(
+      sys_clk_i   => sys_clk_i,
+      sys_rst_n_i => sys_rst_n_i,
+
+      wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr(6 downto 2),  -- cnx_master_out.adr is byte address
+      wb_csr_dat_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).dat,
+      wb_csr_dat_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).dat,
+      wb_csr_cyc_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).cyc,
+      wb_csr_sel_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).sel,
+      wb_csr_stb_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).stb,
+      wb_csr_we_i  => cnx_master_out(c_WB_SLAVE_FMC_ADC).we,
+      wb_csr_ack_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).ack,
+
+      wb_ddr_clk_i   => sys_clk_i,
+      wb_ddr_adr_o   => wb_ddr_adr_o,
+      wb_ddr_dat_o   => wb_ddr_dat_o,
+      wb_ddr_sel_o   => wb_ddr_sel_o,
+      wb_ddr_stb_o   => wb_ddr_stb_o,
+      wb_ddr_we_o    => wb_ddr_we_o,
+      wb_ddr_cyc_o   => wb_ddr_cyc_o,
+      wb_ddr_ack_i   => wb_ddr_ack_i,
+      wb_ddr_stall_i => wb_ddr_stall_i,
+
+      trigger_p_o   => trigger_p_o,
+      acq_start_p_o => acq_start_p_o,
+      acq_stop_p_o  => acq_stop_p_o,
+      acq_end_p_o   => acq_end_p_o,
+
+      ext_trigger_p_i => ext_trigger_p_i,
+      ext_trigger_n_i => ext_trigger_n_i,
+
+      adc_dco_p_i  => adc_dco_p_i,
+      adc_dco_n_i  => adc_dco_n_i,
+      adc_fr_p_i   => adc_fr_p_i,
+      adc_fr_n_i   => adc_fr_n_i,
+      adc_outa_p_i => adc_outa_p_i,
+      adc_outa_n_i => adc_outa_n_i,
+      adc_outb_p_i => adc_outb_p_i,
+      adc_outb_n_i => adc_outb_n_i,
+
+      gpio_dac_clr_n_o => gpio_dac_clr_n_o,
+      gpio_led_acq_o   => gpio_led_acq_o,
+      gpio_led_trig_o  => gpio_led_trig_o,
+      gpio_ssr_ch1_o   => gpio_ssr_ch1_o,
+      gpio_ssr_ch2_o   => gpio_ssr_ch2_o,
+      gpio_ssr_ch3_o   => gpio_ssr_ch3_o,
+      gpio_ssr_ch4_o   => gpio_ssr_ch4_o,
+      gpio_si570_oe_o  => gpio_si570_oe_o
+      );
+
+  -- Unused wishbone signals
+  cnx_master_in(c_WB_SLAVE_FMC_ADC).err   <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC_ADC).rty   <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC_ADC).stall <= '0';
+  cnx_master_in(c_WB_SLAVE_FMC_ADC).int   <= '0';
+
+  ------------------------------------------------------------------------------
+  -- Mezzanine 1-wire master
+  --    DS18B20 (thermometer + unique ID)
+  ------------------------------------------------------------------------------
+  cmp_fmc_onewire : xwb_onewire_master
+    generic map(
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE,
+      g_num_ports           => 1,
+      g_ow_btp_normal       => "5.0",
+      g_ow_btp_overdrive    => "1.0"
+      )
+    port map(
+      clk_sys_i => sys_clk_i,
+      rst_n_i   => sys_rst_n_i,
+
+      slave_i => cnx_master_out(c_WB_SLAVE_FMC_ONEWIRE),
+      slave_o => cnx_master_in(c_WB_SLAVE_FMC_ONEWIRE),
+      desc_o  => open,
+
+      owr_pwren_o => open,
+      owr_en_o    => mezz_owr_en,
+      owr_i       => mezz_owr_i
+      );
+
+  mezz_one_wire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
+  mezz_owr_i(0)   <= mezz_one_wire_b;
+
+end rtl;
--- a/hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
+++ b/hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
+--------------------------------------------------------------------------------
+-- CERN (BE-CO-HT)
+-- FMC ADC mezzanine package
+-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
+--------------------------------------------------------------------------------
+--
+-- unit name: fmc_adc_mezzanine_pkg (fmc_adc_mezzanine_pkg.vhd)
+--
+-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--
+-- date: 03-07-2013
+--
+-- version: 1.0
+--
+-- description: Package for FMC ADC mezzanine
+--
+-- dependencies:
+--
+--------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--------------------------------------------------------------------------------
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--------------------------------------------------------------------------------
+-- last changes: see svn log.
+--------------------------------------------------------------------------------
+-- TODO: - 
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+package fmc_adc_mezzanine_pkg is
+
+  ------------------------------------------------------------------------------
+  -- Constants declaration
+  ------------------------------------------------------------------------------
+
+
+  ------------------------------------------------------------------------------
+  -- Components declaration
+  ------------------------------------------------------------------------------
+  component fmc_adc_mezzanine
+    generic(
+      g_multishot_ram_size : natural := 2048
+      );
+    port (
+      -- Clock, reset
+      sys_clk_i   : in std_logic;
+      sys_rst_n_i : in std_logic;
+
+      -- CSR wishbone interface
+      wb_csr_adr_i   : in  std_logic_vector(31 downto 0);
+      wb_csr_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_csr_dat_o   : out std_logic_vector(31 downto 0);
+      wb_csr_cyc_i   : in  std_logic;
+      wb_csr_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_csr_stb_i   : in  std_logic;
+      wb_csr_we_i    : in  std_logic;
+      wb_csr_ack_o   : out std_logic;
+      wb_csr_stall_o : out std_logic;
+
+      -- DDR wishbone interface
+      wb_ddr_clk_i   : in  std_logic;
+      wb_ddr_adr_o   : out std_logic_vector(31 downto 0);
+      wb_ddr_dat_o   : out std_logic_vector(63 downto 0);
+      wb_ddr_sel_o   : out std_logic_vector(7 downto 0);
+      wb_ddr_stb_o   : out std_logic;
+      wb_ddr_we_o    : out std_logic;
+      wb_ddr_cyc_o   : out std_logic;
+      wb_ddr_ack_i   : in  std_logic;
+      wb_ddr_stall_i : in  std_logic;
+
+      -- Events output pulses (for interrupt and time-stamping)
+      trigger_p_o   : out std_logic;
+      acq_start_p_o : out std_logic;
+      acq_stop_p_o  : out std_logic;
+      acq_end_p_o   : out std_logic;
+
+      -- FMC interface
+      ext_trigger_p_i : in std_logic;   -- External trigger
+      ext_trigger_n_i : in std_logic;
+
+      adc_dco_p_i  : in std_logic;                     -- ADC data clock
+      adc_dco_n_i  : in std_logic;
+      adc_fr_p_i   : in std_logic;                     -- ADC frame start
+      adc_fr_n_i   : in std_logic;
+      adc_outa_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (odd bits)
+      adc_outa_n_i : in std_logic_vector(3 downto 0);
+      adc_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
+      adc_outb_n_i : in std_logic_vector(3 downto 0);
+
+      gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
+      gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
+      gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
+      gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
+      gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
+      gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
+      gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
+      gpio_si570_oe_o  : out std_logic;                     -- Si570 (programmable oscillator) output enable
+
+      spi_din_i       : in  std_logic;  -- SPI data from FMC
+      spi_dout_o      : out std_logic;  -- SPI data to FMC
+      spi_sck_o       : out std_logic;  -- SPI clock
+      spi_cs_adc_n_o  : out std_logic;  -- SPI ADC chip select (active low)
+      spi_cs_dac1_n_o : out std_logic;  -- SPI channel 1 offset DAC chip select (active low)
+      spi_cs_dac2_n_o : out std_logic;  -- SPI channel 2 offset DAC chip select (active low)
+      spi_cs_dac3_n_o : out std_logic;  -- SPI channel 3 offset DAC chip select (active low)
+      spi_cs_dac4_n_o : out std_logic;  -- SPI channel 4 offset DAC chip select (active low)
+
+      si570_scl_b : inout std_logic;    -- I2C bus clock (Si570)
+      si570_sda_b : inout std_logic;    -- I2C bus data (Si570)
+
+      mezz_one_wire_b : inout std_logic;  -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
+
+      sys_scl_b : inout std_logic;      -- Mezzanine system I2C clock (EEPROM)
+      sys_sda_b : inout std_logic       -- Mezzanine system I2C data (EEPROM)
+      );
+  end component fmc_adc_mezzanine;
+
+end fmc_adc_mezzanine_pkg;
+
+package body fmc_adc_mezzanine_pkg is
+
+
+
+end fmc_adc_mezzanine_pkg;
--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
@@ -46,7 +46,7 @@ use work.gn4124_core_pkg.all;
 use work.ddr3_ctrl_pkg.all;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
-use work.fmc_adc_100Ms_core_pkg.all;
+use work.fmc_adc_mezzanine_pkg.all;
 use work.sdb_meta_pkg.all;


@@ -241,7 +241,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
  ------------------------------------------------------------------------------

  -- Number of master port(s) on the wishbone crossbar
-  constant c_NUM_WB_MASTERS : integer := 10;
+  constant c_NUM_WB_MASTERS : integer := 6;

  -- Number of slave port(s) on the wishbone crossbar
  constant c_NUM_WB_SLAVES : integer := 1;
@@ -250,17 +250,12 @@ architecture rtl of spec_top_fmc_adc_100Ms is
  constant c_MASTER_GENNUM : integer := 0;

  -- Wishbone slave(s)
-  constant c_SLAVE_DMA         : integer := 0;  -- DMA controller in the Gennum core
-  constant c_SLAVE_ONEWIRE     : integer := 1;  -- Carrier onewire interface
-  constant c_SLAVE_SPEC_CSR    : integer := 2;  -- SPEC control and status registers
-  constant c_SLAVE_TIMETAG     : integer := 3;  -- TIMETAG core for time-tagging
-  constant c_SLAVE_INT         : integer := 4;  -- Interrupt controller
-  constant c_SLAVE_FMC_SYS_I2C : integer := 5;  -- Mezzanine system I2C interface (EEPROM)
-  constant c_SLAVE_FMC_SPI     : integer := 6;  -- Mezzanine SPI interface
-  constant c_SLAVE_FMC_I2C     : integer := 7;  -- Mezzanine I2C controller
-  constant c_SLAVE_FMC_ADC     : integer := 8;  -- Mezzanine ADC core
-  constant c_SLAVE_FMC_ONEWIRE : integer := 9;  -- Mezzanine onewire interface
-
+  constant c_SLAVE_DMA      : integer := 0;  -- DMA controller in the Gennum core
+  constant c_SLAVE_ONEWIRE  : integer := 1;  -- Carrier onewire interface
+  constant c_SLAVE_SPEC_CSR : integer := 2;  -- SPEC control and status registers
+  constant c_SLAVE_TIMETAG  : integer := 3;  -- TIMETAG core for time-tagging
+  constant c_SLAVE_INT      : integer := 4;  -- Interrupt controller
+  constant c_SLAVE_FMC_ADC  : integer := 5;  -- FMC ADC mezzanine

  -- Devices sdb description
  constant c_DMA_SDB_DEVICE : t_sdb_device := (
@@ -343,73 +338,24 @@ architecture rtl of spec_top_fmc_adc_100Ms is
        date      => x"20121116",
        name      => "WB-Int.Control     ")));

-  constant c_I2C_SDB_DEVICE : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
-    abi_ver_major => x"01",
-    abi_ver_minor => x"01",
-    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"4",                 -- 32-bit port granularity
-    sdb_component => (
-      addr_first  => x"0000000000000000",
-      addr_last   => x"000000000000001F",
-      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
-        device_id => x"00000606",
-        version   => x"00000001",
-        date      => x"20121116",
-        name      => "WB-I2C.Control     ")));
-
-  constant c_SPI_SDB_DEVICE : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
-    abi_ver_major => x"01",
-    abi_ver_minor => x"01",
-    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"4",                 -- 32-bit port granularity
-    sdb_component => (
-      addr_first  => x"0000000000000000",
-      addr_last   => x"000000000000001F",
-      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
-        device_id => x"00000607",
-        version   => x"00000001",
-        date      => x"20121116",
-        name      => "WB-SPI.Control     ")));
-
-  constant c_ADC_SDB_DEVICE : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
-    abi_ver_major => x"01",
-    abi_ver_minor => x"01",
-    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"4",                 -- 32-bit port granularity
-    sdb_component => (
-      addr_first  => x"0000000000000000",
-      addr_last   => x"000000000000007F",
-      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
-        device_id => x"00000608",
-        version   => x"00000001",
-        date      => x"20121116",
-        name      => "WB-FMC-ADC-Core    ")));
+  -- f_xwb_bridge_manual_sdb(size, sdb_addr)
+  constant c_FMC_ADC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00002000");

  -- sdb header address
  constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";

  -- Wishbone crossbar layout
-  constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(12 downto 0) :=
+  constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(8 downto 0) :=
    (
-      0  => f_sdb_embed_device(c_DMA_SDB_DEVICE, x"00001000"),
-      1  => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001200"),
-      2  => f_sdb_embed_device(c_SPEC_CSR_SDB_DEVICE, x"00001300"),
-      3  => f_sdb_embed_device(c_TIMETAG_SDB_DEVICE, x"00001400"),
-      4  => f_sdb_embed_device(c_INT_SDB_DEVICE, x"00001500"),
-      5  => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001600"),
-      6  => f_sdb_embed_device(c_SPI_SDB_DEVICE, x"00001700"),
-      7  => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001800"),
-      8  => f_sdb_embed_device(c_ADC_SDB_DEVICE, x"00001900"),
-      9  => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001A00"),
-      10 => f_sdb_embed_repo_url(c_SDB_REPO_URL),
-      11 => f_sdb_embed_synthesis(c_SDB_SYNTHESIS),
-      12 => f_sdb_embed_integration(c_SDB_INTEGRATION)
+      0 => f_sdb_embed_device(c_DMA_SDB_DEVICE, x"00001000"),
+      1 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001100"),
+      2 => f_sdb_embed_device(c_SPEC_CSR_SDB_DEVICE, x"00001200"),
+      3 => f_sdb_embed_device(c_TIMETAG_SDB_DEVICE, x"00001300"),
+      4 => f_sdb_embed_device(c_INT_SDB_DEVICE, x"00001400"),
+      5 => f_sdb_embed_bridge(c_FMC_ADC_SDB_BRIDGE, x"00002000"),
+      6 => f_sdb_embed_repo_url(c_SDB_REPO_URL),
+      7 => f_sdb_embed_synthesis(c_SDB_SYNTHESIS),
+      8 => f_sdb_embed_integration(c_SDB_INTEGRATION)
      );

  ------------------------------------------------------------------------------
@@ -491,22 +437,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
  signal acq_end_irq_p       : std_logic;
  signal acq_end             : std_logic;

-  -- Mezzanine I2C for Si570
-  signal si570_scl_in   : std_logic;
-  signal si570_scl_out  : std_logic;
-  signal si570_scl_oe_n : std_logic;
-  signal si570_sda_in   : std_logic;
-  signal si570_sda_out  : std_logic;
-  signal si570_sda_oe_n : std_logic;
-
-  -- Mezzanine system I2C for EEPROM
-  signal sys_scl_in   : std_logic;
-  signal sys_scl_out  : std_logic;
-  signal sys_scl_oe_n : std_logic;
-  signal sys_sda_in   : std_logic;
-  signal sys_sda_out  : std_logic;
-  signal sys_sda_oe_n : std_logic;
-
  -- LED control from carrier CSR register
  signal led_red   : std_logic;
  signal led_green : std_logic;
@@ -530,13 +460,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
  signal spi_din_t : std_logic_vector(3 downto 0);
  signal spi_ss_t  : std_logic_vector(7 downto 0);

-  -- Mezzanine 1-wire
-  signal mezz_owr_pwren : std_logic_vector(0 downto 0);
-  signal mezz_owr_en    : std_logic_vector(0 downto 0);
-  signal mezz_owr_i     : std_logic_vector(0 downto 0);
-
  -- Carrier 1-wire
-  signal carrier_owr_pwren : std_logic_vector(0 downto 0);
  signal carrier_owr_en    : std_logic_vector(0 downto 0);
  signal carrier_owr_i     : std_logic_vector(0 downto 0);

@@ -765,7 +689,7 @@ begin
      slave_o => cnx_master_in(c_SLAVE_ONEWIRE),
      desc_o  => open,

-      owr_pwren_o => carrier_owr_pwren,
+      owr_pwren_o => open,
      owr_en_o    => carrier_owr_en,
      owr_i       => carrier_owr_i
      );
@@ -928,137 +852,30 @@ begin
  aux_leds_o(3) <= not(irq_sources_2_led(0));

  ------------------------------------------------------------------------------
-  -- Mezzanine system managment I2C master
-  --    Access to mezzanine EEPROM
-  ------------------------------------------------------------------------------
-  cmp_fmc_sys_i2c : xwb_i2c_master
-    generic map(
-      g_interface_mode      => CLASSIC,
-      g_address_granularity => BYTE
-      )
-    port map (
-      clk_sys_i => sys_clk_125,
-      rst_n_i   => sys_rst_n,
-
-      slave_i => cnx_master_out(c_SLAVE_FMC_SYS_I2C),
-      slave_o => cnx_master_in(c_SLAVE_FMC_SYS_I2C),
-      desc_o  => open,
-
-      scl_pad_i    => sys_scl_in,
-      scl_pad_o    => sys_scl_out,
-      scl_padoen_o => sys_scl_oe_n,
-      sda_pad_i    => sys_sda_in,
-      sda_pad_o    => sys_sda_out,
-      sda_padoen_o => sys_sda_oe_n
-      );
-
-  -- Tri-state buffer for SDA and SCL
-  sys_scl_b  <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
-  sys_scl_in <= sys_scl_b;
-
-  sys_sda_b  <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
-  sys_sda_in <= sys_sda_b;
-
-  ------------------------------------------------------------------------------
-  -- Mezzanine SPI master
-  --    Offset DACs control
-  --    ADC control
-  ------------------------------------------------------------------------------
-  cmp_fmc_spi : xwb_spi
-    generic map(
-      g_interface_mode      => CLASSIC,
-      g_address_granularity => BYTE
-      )
-    port map (
-      clk_sys_i => sys_clk_125,
-      rst_n_i   => sys_rst_n,
-
-      slave_i => cnx_master_out(c_SLAVE_FMC_SPI),
-      slave_o => cnx_master_in(c_SLAVE_FMC_SPI),
-      desc_o  => open,
-
-      pad_cs_o   => spi_ss_t,
-      pad_sclk_o => spi_sck_o,
-      pad_mosi_o => spi_dout_o,
-      pad_miso_i => spi_din_t(spi_din_t'left)
-      );
-
-  -- Assign slave select lines
-  spi_cs_adc_n_o  <= spi_ss_t(0);
-  spi_cs_dac1_n_o <= spi_ss_t(1);
-  spi_cs_dac2_n_o <= spi_ss_t(2);
-  spi_cs_dac3_n_o <= spi_ss_t(3);
-  spi_cs_dac4_n_o <= spi_ss_t(4);
-
-  -- Add some FF after the input pin to solve timing problem
-  p_fmc_spi : process (sys_clk_125)
-  begin
-    if rising_edge(sys_clk_125) then
-      if sys_rst_n = '0' then
-        spi_din_t <= (others => '0');
-      else
-        spi_din_t <= spi_din_t(spi_din_t'left-1 downto 0) & spi_din_i;
-      end if;
-    end if;
-  end process p_fmc_spi;
-
-  ------------------------------------------------------------------------------
-  -- Mezzanine I2C
-  --    Si570 control
-  --
-  -- Note: I2C registers are 8-bit wide, but accessed as 32-bit registers
+  -- FMC ADC mezzanine (wb bridge)
+  --    Mezzanine system managment I2C master
+  --    Mezzanine SPI master
+  --    Mezzanine I2C
+  --    ADC core
+  --    Mezzanine 1-wire master
  ------------------------------------------------------------------------------
-  cmp_fmc_i2c : xwb_i2c_master
+  cmp_fmc_adc_mezzanine_0 : fmc_adc_mezzanine
    generic map(
-      g_interface_mode      => CLASSIC,
-      g_address_granularity => BYTE
-      )
-    port map (
-      clk_sys_i => sys_clk_125,
-      rst_n_i   => sys_rst_n,
-
-      slave_i => cnx_master_out(c_SLAVE_FMC_I2C),
-      slave_o => cnx_master_in(c_SLAVE_FMC_I2C),
-      desc_o  => open,
-
-      scl_pad_i    => si570_scl_in,
-      scl_pad_o    => si570_scl_out,
-      scl_padoen_o => si570_scl_oe_n,
-      sda_pad_i    => si570_sda_in,
-      sda_pad_o    => si570_sda_out,
-      sda_padoen_o => si570_sda_oe_n
-      );
-
-  -- Tri-state buffer for SDA and SCL
-  si570_scl_b  <= si570_scl_out when si570_scl_oe_n = '0' else 'Z';
-  si570_scl_in <= si570_scl_b;
-
-  si570_sda_b  <= si570_sda_out when si570_sda_oe_n = '0' else 'Z';
-  si570_sda_in <= si570_sda_b;
-
-  ------------------------------------------------------------------------------
-  -- ADC core
-  --    Solid State Relays control
-  --    Si570 output enable
-  --    Offset DACs control (CLR_N)
-  --    ADC core control and status
-  ------------------------------------------------------------------------------
-  cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
-    generic map (
      g_multishot_ram_size => 2048
      )
    port map(
      sys_clk_i   => sys_clk_125,
      sys_rst_n_i => sys_rst_n,

-      wb_csr_adr_i => cnx_master_out(c_SLAVE_FMC_ADC).adr(6 downto 2),  -- cnx_master_out.adr is byte address
-      wb_csr_dat_i => cnx_master_out(c_SLAVE_FMC_ADC).dat,
-      wb_csr_dat_o => cnx_master_in(c_SLAVE_FMC_ADC).dat,
-      wb_csr_cyc_i => cnx_master_out(c_SLAVE_FMC_ADC).cyc,
-      wb_csr_sel_i => cnx_master_out(c_SLAVE_FMC_ADC).sel,
-      wb_csr_stb_i => cnx_master_out(c_SLAVE_FMC_ADC).stb,
-      wb_csr_we_i  => cnx_master_out(c_SLAVE_FMC_ADC).we,
-      wb_csr_ack_o => cnx_master_in(c_SLAVE_FMC_ADC).ack,
+      wb_csr_adr_i   => cnx_master_out(c_SLAVE_FMC_ADC).adr,
+      wb_csr_dat_i   => cnx_master_out(c_SLAVE_FMC_ADC).dat,
+      wb_csr_dat_o   => cnx_master_in(c_SLAVE_FMC_ADC).dat,
+      wb_csr_cyc_i   => cnx_master_out(c_SLAVE_FMC_ADC).cyc,
+      wb_csr_sel_i   => cnx_master_out(c_SLAVE_FMC_ADC).sel,
+      wb_csr_stb_i   => cnx_master_out(c_SLAVE_FMC_ADC).stb,
+      wb_csr_we_i    => cnx_master_out(c_SLAVE_FMC_ADC).we,
+      wb_csr_ack_o   => cnx_master_in(c_SLAVE_FMC_ADC).ack,
+      wb_csr_stall_o => cnx_master_in(c_SLAVE_FMC_ADC).stall,

      wb_ddr_clk_i   => sys_clk_125,
      wb_ddr_adr_o   => wb_ddr_adr,
@@ -1094,42 +911,30 @@ begin
      gpio_ssr_ch2_o   => gpio_ssr_ch2_o,
      gpio_ssr_ch3_o   => gpio_ssr_ch3_o,
      gpio_ssr_ch4_o   => gpio_ssr_ch4_o,
-      gpio_si570_oe_o  => gpio_si570_oe_o
-      );
+      gpio_si570_oe_o  => gpio_si570_oe_o,

-  -- Unused wishbone signals
-  cnx_master_in(c_SLAVE_FMC_ADC).err   <= '0';
-  cnx_master_in(c_SLAVE_FMC_ADC).rty   <= '0';
-  cnx_master_in(c_SLAVE_FMC_ADC).stall <= '0';
-  cnx_master_in(c_SLAVE_FMC_ADC).int   <= '0';
+      spi_din_i       => spi_din_i,
+      spi_dout_o      => spi_dout_o,
+      spi_sck_o       => spi_sck_o,
+      spi_cs_adc_n_o  => spi_cs_adc_n_o,
+      spi_cs_dac1_n_o => spi_cs_dac1_n_o,
+      spi_cs_dac2_n_o => spi_cs_dac2_n_o,
+      spi_cs_dac3_n_o => spi_cs_dac3_n_o,
+      spi_cs_dac4_n_o => spi_cs_dac4_n_o,

-  ------------------------------------------------------------------------------
-  -- Mezzanine 1-wire master
-  --    DS18B20 (thermometer + unique ID)
-  ------------------------------------------------------------------------------
-  cmp_fmc_onewire : xwb_onewire_master
-    generic map(
-      g_interface_mode      => CLASSIC,
-      g_address_granularity => BYTE,
-      g_num_ports           => 1,
-      g_ow_btp_normal       => "5.0",
-      g_ow_btp_overdrive    => "1.0"
-      )
-    port map(
-      clk_sys_i => sys_clk_125,
-      rst_n_i   => sys_rst_n,
+      si570_scl_b => si570_scl_b,
+      si570_sda_b => si570_sda_b,

-      slave_i => cnx_master_out(c_SLAVE_FMC_ONEWIRE),
-      slave_o => cnx_master_in(c_SLAVE_FMC_ONEWIRE),
-      desc_o  => open,
+      mezz_one_wire_b => mezz_one_wire_b,

-      owr_pwren_o => mezz_owr_pwren,
-      owr_en_o    => mezz_owr_en,
-      owr_i       => mezz_owr_i
+      sys_scl_b => sys_scl_b,
+      sys_sda_b => sys_sda_b
      );

-  mezz_one_wire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
-  mezz_owr_i(0)   <= mezz_one_wire_b;
+  -- Unused wishbone signals
+  cnx_master_in(c_SLAVE_FMC_ADC).err <= '0';
+  cnx_master_in(c_SLAVE_FMC_ADC).rty <= '0';
+  cnx_master_in(c_SLAVE_FMC_ADC).int <= '0';

  ------------------------------------------------------------------------------
  -- DMA wishbone bus slaves
@@ -1231,7 +1036,7 @@ begin
  GPIO(1) <= '0';                       -- connection to GN4124

  ------------------------------------------------------------------------------
-  -- FPGA programmed led (heart beat)
+  -- FPGA loaded led (heart beat)
  ------------------------------------------------------------------------------
  p_led_pwn_update_cnt : process (sys_clk_125)
  begin

--- a/hdl/spec/spec_top_fmc_adc_100Ms.ucf
+++ b/hdl/spec/spec_top_fmc_adc_100Ms.ucf
@@ -546,8 +546,8 @@ NET "AUX_LEDS_O[3]" IOSTANDARD = "LVCMOS18";
 INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
 INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;

-INST "cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/s_out" IOB=FALSE;
-INST "cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
+INST "cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/s_out" IOB=FALSE;
+INST "cmp_fmc_adc_mezzanine_0/cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/clgen/clk_out" IOB=FALSE;


 #===============================================================================

--- a/hdl/spec/syn/spec_fmc_adc_100Ms.xise
+++ b/hdl/spec/syn/spec_fmc_adc_100Ms.xise
@@ -90,6 +90,7 @@
    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
@@ -214,6 +215,7 @@
    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -725,10 +727,10 @@
    <file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
    </file>
-    <file xil_pn:name="../rtl/utc_core_regs.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../rtl/timetag_core_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
    </file>
-    <file xil_pn:name="../rtl/utc_core.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../rtl/timetag_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
    </file>
    <file xil_pn:name="../rtl/irq_controller_regs.vhd" xil_pn:type="FILE_VHDL">
@@ -737,360 +739,366 @@
    <file xil_pn:name="../rtl/irq_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
    </file>
-    <file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
    </file>
-    <file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
    </file>
-    <file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../rtl/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
    </file>
-    <file xil_pn:name="../rtl/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
    </file>
-    <file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="134"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
    </file>
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      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
    </file>
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      <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
    </file>
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      <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
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      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="169"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="170"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="171"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
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      <association xil_pn:name="Implementation" xil_pn:seqID="172"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="173"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="174"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="175"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="176"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="177"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="178"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="179"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="180"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="Implementation" xil_pn:seqID="181"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="182"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="183"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="184"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="185"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="186"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="187"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="188"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="189"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="190"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
    </file>
-    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="193"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="194"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="195"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="196"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="198"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="199"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="200"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="201"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="202"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="203"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="204"/>
    </file>
-    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="205"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="206"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="207"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="208"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="209"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="210"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="211"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="213"/>
    </file>
-    <file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="219"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="220"/>
    </file>
-    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="221"/>
    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="222"/>
+    </file>
+    <file xil_pn:name="../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="223"/>
+    </file>
  </files>

  <bindings/>