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FMC ADC 100M 14b 4cha - Gateware
Commit 76e6aded authored by Matthieu Cattin's avatar Matthieu Cattin
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sim: try to reproduce gennum hang bug in simulation.

parent 87b58b49
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Showing with 323 additions and 309 deletions
hdl/spec/sim/cmd0.vec
View file @ 76e6aded
...@@ -165,34 +165,48 @@ wr 0000000020000028 F 00000000 ...@@ -165,34 +165,48 @@ wr 0000000020000028 F 00000000
-- DMA length -- DMA length
wr 000000002000002C F 00001000 wr 000000002000002C F 00001000
-- Next item address (lsb) -- Next item address (lsb)
wr 0000000020000030 F 20000030 wr 0000000020000030 F 20000040
-- Next item address (msb) -- Next item address (msb)
wr 0000000020000034 F 00000000 wr 0000000020000034 F 00000000
-- DMA attributes (from carrier to host, last item) -- DMA attributes (from carrier to host, last item)
wr 0000000020000038 F 00000000 wr 0000000020000038 F 00000001
wait %d2000 -- DMA item stored in host memory
------------------------------
-- Carrier start address
wr 0000000020000040 F 00003000
-- Host start address (lsb)
wr 0000000020000044 F 40003000
-- Host start address (msb)
wr 0000000020000048 F 00000000
-- DMA length
wr 000000002000004C F 00001000
-- Next item address (lsb)
wr 0000000020000050 F 20000060
-- Next item address (msb)
wr 0000000020000054 F 00000000
-- DMA attributes (from carrier to host, last item)
wr 0000000020000058 F 00000001
-- DMA -- DMA item stored in host memory
------------------------------ ------------------------------
-- Carrier start address -- Carrier start address
wr FF00000000001008 F 00000000 wr 0000000020000060 F 00004000
-- Host start address (lsb) -- Host start address (lsb)
wr FF0000000000100C F 40000000 wr 0000000020000064 F 40004000
-- Host start address (msb) -- Host start address (msb)
wr FF00000000001010 F 00000000 wr 0000000020000068 F 00000000
-- DMA length -- DMA length
wr FF00000000001014 F 00001000 wr 000000002000006C F 00001000
-- Next item address (lsb) -- Next item address (lsb)
wr FF00000000001018 F 20000000 wr 0000000020000070 F 20000080
-- Next item address (msb) -- Next item address (msb)
wr FF0000000000101C F 00000000 wr 0000000020000074 F 00000000
-- DMA attributes (from carrier to host, last item) -- DMA attributes (from carrier to host, last item)
wr FF00000000001020 F 00000001 wr 0000000020000078 F 00000000
-- Start DMA
--wr FF0000000001000 F 00000001 wait %d2000
wait %d100
-- onewire config -- onewire config
wr FF00000000001A04 F 007C0270 wr FF00000000001A04 F 007C0270
...@@ -241,13 +255,13 @@ wr FF00000000001964 F 00008000 ...@@ -241,13 +255,13 @@ wr FF00000000001964 F 00008000
wr FF00000000001968 F 00000000 wr FF00000000001968 F 00000000
-- Enable test data and sampling clock -- Enable test data and sampling clock
--wr FF00000000001900 F 00000024 wr FF00000000001900 F 00000024
-- Enable sampling clock -- Enable sampling clock
wr FF00000000001900 F 00000004 --wr FF00000000001900 F 00000004
-- start acquisition -- start acquisition
--wr FF00000000001900 F 00000025 wr FF00000000001900 F 00000025
wr FF00000000001900 F 00000005 --wr FF00000000001900 F 00000005
wait %d800 wait %d800
-- sw trigger -- sw trigger
...@@ -269,7 +283,7 @@ wait %d800 ...@@ -269,7 +283,7 @@ wait %d800
-- sw trigger -- sw trigger
--wr FF00000000001910 F FFFFFFFF --wr FF00000000001910 F FFFFFFFF
wait %d700 wait %d1000
-- DMA -- DMA
------------------------------ ------------------------------
...@@ -332,49 +346,29 @@ wait %d1000 ...@@ -332,49 +346,29 @@ wait %d1000
-- FMC I2C (prescaler) -- FMC I2C (prescaler)
wr FF00000000080000 F 000000F9 --wr FF00000000080000 F 000000F9
rd FF00000000080000 F 000000F9 FFFFFFFF --rd FF00000000080000 F 000000F9 FFFFFFFF
wait %d640 wait %d640
-- Carrier CSR (read carrier type and PCB version) -- Carrier CSR (read carrier type and PCB version)
rd FF00000000030000 F 00010001 FFFFFFFF --rd FF00000000030000 F 00010001 FFFFFFFF
-- Carrier CSR (switch front panel LED ON) -- Carrier CSR (switch front panel LED ON)
wr FF00000000030010 F 00000003 --wr FF00000000030010 F 00000003
rd FF00000000030010 F 00000003 FFFFFFFF --rd FF00000000030010 F 00000003 FFFFFFFF
wait %d640 wait %d640
-- FMC SPI (divider = 100) -- FMC SPI (divider = 100)
wr FF00000000070014 F 00000064 --wr FF00000000070014 F 00000064
-- FMC SPI (select ADC) -- FMC SPI (select ADC)
wr FF00000000070018 F 00000001 --wr FF00000000070018 F 00000001
-- FMC SPI (data) -- FMC SPI (data)
wr FF00000000070000 F 000081FF --wr FF00000000070000 F 000081FF
-- FMC SPI (ass, tx_neg, go, len=16) -- FMC SPI (ass, tx_neg, go, len=16)
wr FF00000000070010 F 00002510 --wr FF00000000070010 F 00002510
wait %d300 wait %d300
-- DDR access trough DMA wishbone
wr 0000000020000000 F 00000000
wr 0000000020000004 F 40000000
wr 0000000020000008 F 00000000
-- DMA length
wr 000000002000000C F 000000C0
wr 0000000020000010 F 00000000
wr 0000000020000014 F 00000000
wr 0000000020000018 F 00000000
-- wrb FF00000010004004 F 00000000
wr FF00000000000008 F 00000000
wr FF0000000000000C F 40000000
wr FF00000000000010 F 00000000
-- DMA length
wr FF00000000000014 F 000000C0
wr FF00000000000018 F 20000000
wr FF0000000000001C F 00000000
wr FF00000000000020 F 00000003
wr FF00000000000000 F 00000001
-- Now read back what was just written -- Now read back what was just written
-- the following three reads will go out as a single request -- the following three reads will go out as a single request
......
hdl/spec/sim/testbench/tb_spec.vhd
View file @ 76e6aded
...@@ -46,7 +46,7 @@ architecture TEST of TB_SPEC is ...@@ -46,7 +46,7 @@ architecture TEST of TB_SPEC is
generic generic
( (
STRING_MAX : integer := 256; -- Command string maximum length STRING_MAX : integer := 256; -- Command string maximum length
T_LCLK : time := 10 ns; -- Local Bus Clock Period T_LCLK : time := 5 ns; -- Local Bus Clock Period
T_P2L_CLK_DLY : time := 2 ns; -- Delay from LCLK to P2L_CLK T_P2L_CLK_DLY : time := 2 ns; -- Delay from LCLK to P2L_CLK
INSTANCE_LABEL : string := "GN412X_BFM"; -- Label string to be used as a prefix for messages from the model INSTANCE_LABEL : string := "GN412X_BFM"; -- Label string to be used as a prefix for messages from the model
MODE_PRIMARY : boolean := true -- TRUE for BFM acting as GN412x, FALSE for BFM acting as the DUT MODE_PRIMARY : boolean := true -- TRUE for BFM acting as GN412x, FALSE for BFM acting as the DUT
...@@ -492,7 +492,7 @@ begin ...@@ -492,7 +492,7 @@ begin
generic map generic map
( (
STRING_MAX => STRING_MAX, STRING_MAX => STRING_MAX,
T_LCLK => 6.25 ns, T_LCLK => 5 ns,
T_P2L_CLK_DLY => 2 ns, T_P2L_CLK_DLY => 2 ns,
INSTANCE_LABEL => "U0(Primary GN412x): ", INSTANCE_LABEL => "U0(Primary GN412x): ",
MODE_PRIMARY => true MODE_PRIMARY => true
......
hdl/spec/sim/wave_datapath.do
View file @ 76e6aded
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {Wishbone CSR interface} add wave -noupdate -divider {Wishbone CSR interface}
add wave -noupdate /tb_spec/u1/sys_clk_125 add wave -noupdate /tb_spec/U1/sys_clk_125
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_adr
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dat_o
add wave -noupdate /tb_spec/u1/wb_stb
add wave -noupdate /tb_spec/u1/wb_we
add wave -noupdate /tb_spec/u1/wb_sel
add wave -noupdate -divider trigger add wave -noupdate -divider trigger
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sw_trig_en add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sw_trig add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/trig add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_d add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/trig_align add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -divider {acq fsm} add wave -noupdate -divider {acq fsm}
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/post_trig_done add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_done
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_cnt add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_value add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_decr add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/shots_done add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/acq_fsm_current_state add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate -divider datapath add wave -noupdate -divider datapath
add wave -noupdate /tb_spec/u1/adc_dco_n_i add wave -noupdate -radix hexadecimal /tb_spec/ADC_DATA
add wave -noupdate /tb_spec/u1/adc_dco_p_i add wave -noupdate /tb_spec/U1/adc_dco_n_i
add wave -noupdate /tb_spec/u1/adc_fr_p_i add wave -noupdate /tb_spec/U1/adc_dco_p_i
add wave -noupdate /tb_spec/u1/adc_outa_p_i(0) add wave -noupdate /tb_spec/U1/adc_fr_p_i
add wave -noupdate /tb_spec/u1/adc_outb_p_i(0) add wave -noupdate /tb_spec/U1/adc_outa_p_i(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_fr add wave -noupdate /tb_spec/U1/adc_outb_p_i(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_data add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/locked_out add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/fs_clk add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/locked_out
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/fs_rst_n add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_synced add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_rst_n
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_100ms_core/decim_cnt add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate -radix decimal /tb_spec/u1/cmp_fmc_adc_100ms_core/decim_factor add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/decim_en add wave -noupdate -radix decimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_wr add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_din add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_full add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_din
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_dreq add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_dout add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_dout(48) add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dout
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_empty add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dout(48)
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_rd add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_empty
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/sync_fifo_valid add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/serdes_out_data add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_wr add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_wr_en add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_din add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_full add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_dreq add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_rd add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_dout add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_empty add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_fifo_valid add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/ram_addr_cnt add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate -divider {adc to ddr WB} add wave -noupdate -divider {adc to ddr WB}
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_ack_i add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_clk_i add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_cyc_o add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_dat_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_stb_o add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_we_o add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_adr_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_100ms_core/wb_ddr_stall_i add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i
add wave -noupdate -divider {ddr controller} add wave -noupdate -divider {ddr controller}
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/status_o(0) add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/status_o(0)
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/wb0_clk_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/wb0_clk_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/rst_n_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/rst_n_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_wr_empty add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_empty
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/p0_wr_count add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/p0_wr_count
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_wr_full add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_full
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p0_wr_data add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p0_wr_data
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_wr_en add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_bl add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p0_cmd_bl
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_byte_addr add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p0_cmd_byte_addr
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_empty add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_cmd_empty
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_full add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_cmd_full
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_en add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_cmd_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_cmd_bl add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_cmd_bl
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_cmd_byte_addr add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_cmd_byte_addr
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_cmd_empty add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_cmd_empty
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_cmd_en add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_cmd_en
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_cmd_full add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_cmd_full
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_rd_error add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_rd_error
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_rd_overflow add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_rd_overflow
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_rd_full add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_rd_full
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_rd_count add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_rd_count
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_rd_data add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_rd_data
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_rd_empty add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_rd_empty
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_rd_en add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_rd_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_wr_count add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_wr_count
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p1_wr_data add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/p1_wr_data
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_wr_en add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_wr_en
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/p1_wr_full add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p1_wr_full
add wave -noupdate -divider {ddr to gennum WB} add wave -noupdate -divider {ddr to gennum WB}
add wave -noupdate /tb_spec/u1/sys_clk_125 add wave -noupdate /tb_spec/U1/sys_clk_125
add wave -noupdate /tb_spec/u1/wb_dma_ack add wave -noupdate /tb_spec/U1/wb_dma_ack
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dma_adr add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_dma_adr
add wave -noupdate /tb_spec/u1/wb_dma_cyc add wave -noupdate /tb_spec/U1/wb_dma_cyc
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dma_dat_i add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_dma_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dma_dat_o add wave -noupdate -radix hexadecimal /tb_spec/U1/wb_dma_dat_o
add wave -noupdate /tb_spec/u1/wb_dma_stall add wave -noupdate /tb_spec/U1/wb_dma_stall
add wave -noupdate /tb_spec/u1/wb_dma_stb add wave -noupdate /tb_spec/U1/wb_dma_stb
add wave -noupdate /tb_spec/u1/wb_dma_we add wave -noupdate /tb_spec/U1/wb_dma_we
add wave -noupdate -divider l2p add wave -noupdate -divider l2p
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_start_l2p_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_start_l2p_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_len_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_len_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_header
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_done_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_empty
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/ldm_arb_data add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/dma_ctrl_done_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/ldm_arb_dframe add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/ldm_arb_req add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/ldm_arb_data
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/ldm_arb_valid add wave -noupdate /tb_spec/U1/cmp_gn4124_core/ldm_arb_dframe
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/ldm_arb_req
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/ldm_arb_valid
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/arb_ldm_gnt
add wave -noupdate -divider p2l add wave -noupdate -divider p2l
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/to_wb_fifo_din add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/to_wb_fifo_din
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/to_wb_fifo_wr add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/to_wb_fifo_wr
add wave -noupdate -divider {GN4124 LOCAL BUS} add wave -noupdate -divider {GN4124 LOCAL BUS}
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/l2p_data_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/l2p_data_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/l2p_dframe_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/l2p_dframe_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/l2p_valid_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/l2p_valid_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/l2p_edb_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/l2p_edb_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/l_wr_rdy_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/l_wr_rdy_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/p2l_data_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/p2l_data_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p2l_dframe_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p2l_dframe_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p2l_rdy_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p2l_rdy_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p2l_valid_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p2l_valid_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p_rd_d_rdy_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p_rd_d_rdy_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p_wr_rdy_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p_wr_rdy_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/p_wr_req_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/p_wr_req_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/tx_error_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/tx_error_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/vc_rdy_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/vc_rdy_i
add wave -noupdate -divider {gennum global} add wave -noupdate -divider {gennum global}
add wave -noupdate -expand /tb_spec/u1/irq_sources add wave -noupdate -expand /tb_spec/U1/irq_sources
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1990664 ps} 0} WaveRestoreCursors {{Cursor 1} {44575961 ps} 0}
configure wave -namecolwidth 496 configure wave -namecolwidth 496
configure wave -valuecolwidth 172 configure wave -valuecolwidth 172
configure wave -justifyvalue left configure wave -justifyvalue left
...@@ -158,4 +157,4 @@ configure wave -griddelta 40 ...@@ -158,4 +157,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {0 ps} {34650 ns} WaveRestoreZoom {44465609 ps} {44570867 ps}
hdl/spec/sim/wave_gnum.do
View file @ 76e6aded
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_spec/rstout18n add wave -noupdate /tb_spec/RSTOUT18n
add wave -noupdate /tb_spec/u1/ddr3_calib_done add wave -noupdate /tb_spec/U1/ddr3_calib_done
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/des_pd_valid add wave -noupdate /tb_spec/U1/cmp_gn4124_core/des_pd_valid
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/des_pd_dframe add wave -noupdate /tb_spec/U1/cmp_gn4124_core/des_pd_dframe
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/des_pd_data add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/des_pd_data
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/arb_ser_valid add wave -noupdate /tb_spec/U1/cmp_gn4124_core/arb_ser_valid
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/arb_ser_dframe add wave -noupdate /tb_spec/U1/cmp_gn4124_core/arb_ser_dframe
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/arb_ser_data add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/arb_ser_data
add wave -noupdate -divider {DDR ADC} add wave -noupdate -divider {DDR ADC}
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr_o
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl_o add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl_o
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr_o add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_empty_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_empty_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_en_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_en_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_data_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_data_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_en_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_en_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stb_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stb_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_we_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_addr_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_addr_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_data_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_ack_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_ack_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stall_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stall_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_f_edge add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_r_edge add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_cyc_r_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stb_f_edge add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stb_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_we_f_edge add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_we_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt
add wave -noupdate -divider {DDR GNUM} add wave -noupdate -divider {DDR GNUM}
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_burst_cnt add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_burst_cnt
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl_o add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_en_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/ddr_rd_en_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_ack_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_ack_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_addr_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_addr_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_clk_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_clk_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_f_edge add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_r_edge add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_cyc_r_edge
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stall_o add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stall_o
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stb_f_edge add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stb_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stb_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stb_i
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_we_f_edge add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_we_f_edge
add wave -noupdate /tb_spec/u1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_we_i add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_we_i
add wave -noupdate -divider {P2L DMA master} add wave -noupdate -divider {P2L DMA master}
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_carrier_addr_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_carrier_addr_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_done_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_done_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_done_t add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_done_t
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_error_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_error_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_host_addr_l_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_host_addr_l_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_len_i add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_len_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_start_next_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_start_next_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_start_p2l_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/dma_ctrl_start_p2l_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_data_cnt add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/p2l_data_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_last_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_last_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_valid_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_data_valid_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_hdr_length_i add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_hdr_length_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_hdr_start_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_hdr_start_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_master_cpld_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_master_cpld_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_master_cpln_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/pd_pdm_master_cpln_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_header add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_header
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/is_next_item add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/is_next_item
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_attrib_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_attrib_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_carrier_addr_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_carrier_addr_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_host_addr_h_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_host_addr_h_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_host_addr_l_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_host_addr_l_o
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_len_o add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_len_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_next_h_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_next_h_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_next_l_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_next_l_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_valid_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_p2l_dma_master/next_item_valid_o
add wave -noupdate -divider {L2P DMA master} add wave -noupdate -divider {L2P DMA master}
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_empty add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/target_addr_cnt
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_clk_i add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_ack_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_full
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_cyc_o add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_dat_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_valid
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_stb_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_rd
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_we_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_empty
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_dout
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_clk_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_cyc_o
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/target_addr_cnt add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_stb_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_stall_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_dat_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_ack_i
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_wr
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_din
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_empty
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_dframe_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_req_o
add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_l2p_dma_master/arb_ldm_gnt_i
add wave -noupdate -divider {DMA controller} add wave -noupdate -divider {DMA controller}
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_reg add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_hstartl_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_hstarth_reg add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_hstarth_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_len_reg add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_len_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_nextl_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_nexth_reg add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_nexth_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_load add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_nextl_load add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_nextl_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_nexth_load add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_nexth_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_len_load add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_len_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_hstartl_load add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_hstartl_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_hstarth_load add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_hstarth_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_cstart_load add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_cstart_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_attrib_load add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_attrib_load
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_done_irq add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_done_irq
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_error_irq add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_error_irq
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_l2p_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_l2p_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_next_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_next_o
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_p2l_o add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_ctrl_start_p2l_o
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/dma_len_reg add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/dma_len_reg
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_attrib_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_attrib_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_carrier_addr_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_carrier_addr_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_host_addr_h_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_host_addr_h_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_host_addr_l_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_host_addr_l_i
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_len_i add wave -noupdate -radix unsigned /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_len_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_next_h_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_next_h_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_next_l_i add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_next_l_i
add wave -noupdate /tb_spec/u1/cmp_gn4124_core/cmp_dma_controller/next_item_valid_i add wave -noupdate /tb_spec/U1/cmp_gn4124_core/cmp_dma_controller/next_item_valid_i
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {42220934 ps} 0} {{Cursor 2} {13856000 ps} 0} WaveRestoreCursors {{Cursor 1} {30090961 ps} 0} {{Cursor 2} {22107797 ps} 0}
configure wave -namecolwidth 496 configure wave -namecolwidth 496
configure wave -valuecolwidth 172 configure wave -valuecolwidth 172
configure wave -justifyvalue left configure wave -justifyvalue left
...@@ -145,4 +166,4 @@ configure wave -griddelta 40 ...@@ -145,4 +166,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {10050 ns} {11935099 ps} WaveRestoreZoom {22026423 ps} {22191901 ps}
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