@@ -170,16 +170,13 @@ The GN4124 bridge is used to access the FPGA registers, but also to generate MSI
The BAR 4 (Base Address Register) allows access to the GN4124 internal registers.
The BAR 0 is connected to the local bus and therefore allows access to the FPGA.
The GN4124 core is made of a local bus interface with the GN4124 chip, a Wishbone bus master mapped to BAR0 and a DMA controller. The DMA controller has two Wishbone ports. A Wishbone slave to configure the DMA controller and a Wishbone master to access the DDR memory.
The GN4124 core is made of a local bus interface with the GN4124 chip, a Wishbone bus master mapped to BAR0 and a DMA controller. The DMA controller has two Wishbone ports, a Wishbone slave to configure the DMA controller and a Wishbone master to access the DDR memory.
The GN4124 Wishbone interfaces (masters and slave) are 32-bit data width and 32-bit word aligned addresses.
@table @b
@item TODO
wb addr alignment
@item TODO
ddr memory access (interleaved, no address converter)
@item TODO
wb buses size
@end table
@quotation Note
It is not possible to insert an address converter (for non-interleaved data read) between the GN4124 core and the memory controller.
Because the DDR memory access is not efficiant when reading non-consecutive addresses.
The undersampling block is simply validating one in N samples and forwarding it to the acquisition logic.
The number (N) is configured in the "Sample rate" register.
The number (N) is configured in the @i{Sample rate} register.
If N > 1, then the trigger pulse is aligned to the next valid sample.
If N = 1 all the samples are valid and therefore the trigger is always aligned.
A value of N = 0 is treated as N = 1 in the firmware.
...
...
@@ -595,10 +594,10 @@ The @ref{fig:adc_core_sys_clk} shows the ADC core acquisition logic.
The heart of the acquisition logic is a state machine driven by user commands (start, stop), the trigger signal and counters events (e.g. pre-trig done, etc...).
The ADC samples are routed along a datapath (bold arrows), which depends on the acquisition mode.
It is explained in detail in the @ref{Single-shot mode} and @ref{Multi-shot mode}.
The four channels data and the trigger are concatenated together and fed to a FIFO to synchronise between the sampling clock domain and the system clock domain.
The four channels data and the trigger are concatenated together and fed to a FIFO to be synchronised between the sampling clock domain and the system clock domain.
Even if the LTC2174 ADC is 14-bit, the data of each channel is stored in a 16-bit word.
The 14 bits of ADC data takes the MSB part of the 16-bit word and the two LSBs are set to 0.
Along the datapath, we call a sample a 64-bit vector containing a sample for each channel.
Along the datapath, we call @i{sample} a 64-bit vector containing a sample for each channel.
At the output of the ADC core, a flow control FIFO allows to cope with the memory controller temporary unavailabilities (due to DDR refresh cycles).
@float Figure,fig:adc_core_sys_clk
...
...
@@ -625,6 +624,8 @@ After that, it goes in @code{WAIT_TRIG} state and continue recording sample to m
When a valid trigger is detected, the state machine moves to @code{POST_TRIG}.
It will stays in this state until the programmed number of post-trigger samples is reached.
Then, depending on the mode, the state machine either goes back to @code{IDLE} (single-shot mode) or to @code{PRE_TRIG} (multi-shot mode).
When the acquisition is terminated (state machine back to @code{IDLE}) and all samples have been written to the DDR memory, only then the software can retrieve the samples using DMA transfer.
An interrupt is generated when the acquisition ends.
@quotation Note
Start commands are taken into account only in @code{IDLE} state.
...
...
@@ -634,6 +635,10 @@ Start commands are taken into account only in @code{IDLE} state.
Trigger are taken into account only in @code{WAIT_TRIG} state.
@end quotation
@quotation Note
A stop command will bring the state machine back to @code{IDLE} from any state.
@end quotation
@float Figure,fig:acq_fsm
@center @image{../../figures/acq_fsm, 10cm,,,pdf}
@caption{Acquisition state machine.}
...
...
@@ -643,24 +648,49 @@ There are two LED on the fmc-adc front panel.
The LED labeled @code{ACQ} is turned ON when the acquisition state machine is @b{not} in the @code{IDLE} state.
The LED labeled @code{TRIG} flashes when a valid trigger is detected @b{and} the acquisition state machine is in the @code{WAIT_TRIG} state.
The multi-shot acquisition process is almost identical to the single-shot one, except that once the acquisition is started it will go around the state machine as many time as the number of configured shots.
It means that if the board is configured for N shots, it will generate N trigger interrupts and then another interrupt at the end of the acquisition.
Unlike the single-mode acquisition, in multi-shot, the DDR memory is not used as a circular buffer.
Instead, two dual port RAM (dpram) are implemented inside the FPGA.
Those dprams are alternatively used as circular buffer for each shot.
Even shots uses dpram0 and odd shots dpram1.
@quotation Note
The dprams are 2048 samples deep. It means that the total number of samples (pre-trigger + post-trigger) for a shot cannot exceed 2048.
@end quotation
When a shot is finished, the correcponding dpram samples are written to the DDR memory.
Only the pre-trigger and post-trigger samples are written.
The first shot is written starting at address @code{0x0}.
Then the second shot is written right after the last post-trigger sample of the first shot.
The @ref{fig:mem_multi_shot} shows the shots organisation in the DDR memory.
