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FMC ADC 100M 14b 4cha - Gateware
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migrate complete RTL and SPEC ref memory map and interconnect to Cheby

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<HTML>
<HEAD>
<TITLE>alt_trigin</TITLE>
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</HEAD>
<BODY>
<h1 class="heading">alt_trigin</h1>
<h3>FMC ADC alt trigger out registers</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#version">version</a></td>
<td class="td_code">version</td>
<td class="td_code">version</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x04</td>
<td>REG</td>
<td><A href="#ctrl">ctrl</a></td>
<td class="td_code">ctrl</td>
<td class="td_code">ctrl</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#seconds">seconds</a></td>
<td class="td_code">seconds</td>
<td class="td_code">seconds</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#cycles">cycles</a></td>
<td class="td_code">cycles</td>
<td class="td_code">cycles</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="version"></a>
<h3><a name="sect_3_1">2.1. version</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">version</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">version</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Core version
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[7:0]</td>
</tr>
</table>
<ul>
<li><b>
version
</b>[<i>ro</i>]: Core version
</ul>
<a name="ctrl"></a>
<h3><a name="sect_3_2">2.2. ctrl</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Control register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">enable</td>
</tr>
</table>
<ul>
<li><b>
enable
</b>[<i>rw</i>]: Enable trigger, cleared when triggered
</ul>
<a name="seconds"></a>
<h3><a name="sect_3_3">2.3. seconds</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">seconds</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">seconds</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) to trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">63</td>
<td class="td_bit" colspan="1">62</td>
<td class="td_bit" colspan="1">61</td>
<td class="td_bit" colspan="1">60</td>
<td class="td_bit" colspan="1">59</td>
<td class="td_bit" colspan="1">58</td>
<td class="td_bit" colspan="1">57</td>
<td class="td_bit" colspan="1">56</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[63:56]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">55</td>
<td class="td_bit" colspan="1">54</td>
<td class="td_bit" colspan="1">53</td>
<td class="td_bit" colspan="1">52</td>
<td class="td_bit" colspan="1">51</td>
<td class="td_bit" colspan="1">50</td>
<td class="td_bit" colspan="1">49</td>
<td class="td_bit" colspan="1">48</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[55:48]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">47</td>
<td class="td_bit" colspan="1">46</td>
<td class="td_bit" colspan="1">45</td>
<td class="td_bit" colspan="1">44</td>
<td class="td_bit" colspan="1">43</td>
<td class="td_bit" colspan="1">42</td>
<td class="td_bit" colspan="1">41</td>
<td class="td_bit" colspan="1">40</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[47:40]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">39</td>
<td class="td_bit" colspan="1">38</td>
<td class="td_bit" colspan="1">37</td>
<td class="td_bit" colspan="1">36</td>
<td class="td_bit" colspan="1">35</td>
<td class="td_bit" colspan="1">34</td>
<td class="td_bit" colspan="1">33</td>
<td class="td_bit" colspan="1">32</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[39:32]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[7:0]</td>
</tr>
</table>
<ul>
<li><b>
seconds
</b>[<i>rw</i>]: Time (seconds) to trigger
</ul>
<a name="cycles"></a>
<h3><a name="sect_3_4">2.4. cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">cycles</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">cycles</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Time (cycles) to trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[7:0]</td>
</tr>
</table>
<ul>
<li><b>
cycles
</b>[<i>rw</i>]: Time (cycles) to trigger
</ul>
</BODY>
</HTML>
doc/manual/fmc_adc_alt_trigout.html deleted 100644 → 0
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<HTML>
<HEAD>
<TITLE>alt_trigout</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
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padding:3px; }
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.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">alt_trigout</h1>
<h3>FMC ADC alt trigger out registers</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#status">status</a></td>
<td class="td_code">status</td>
<td class="td_code">status</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#ts_mask_sec">ts_mask_sec</a></td>
<td class="td_code">ts_mask_sec</td>
<td class="td_code">ts_mask_sec</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#ts_cycles">ts_cycles</a></td>
<td class="td_code">ts_cycles</td>
<td class="td_code">ts_cycles</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="status"></a>
<h3><a name="sect_3_1">2.1. status</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">status</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">status</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Status register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ts_present</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">wr_valid</td>
<td class="td_field" colspan="1">wr_link</td>
<td class="td_field" colspan="1">wr_enable</td>
</tr>
</table>
<ul>
<li><b>
wr_enable
</b>[<i>ro</i>]: Set when WR is enabled
<li><b>
wr_link
</b>[<i>ro</i>]: WR link status
<li><b>
wr_valid
</b>[<i>ro</i>]: Set when WR time is valid
<li><b>
ts_present
</b>[<i>ro</i>]: Set when the timestamp fifo is not empty
</ul>
<a name="ts_mask_sec"></a>
<h3><a name="sect_3_2">2.2. ts_mask_sec</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) of the last event
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">63</td>
<td class="td_bit" colspan="1">62</td>
<td class="td_bit" colspan="1">61</td>
<td class="td_bit" colspan="1">60</td>
<td class="td_bit" colspan="1">59</td>
<td class="td_bit" colspan="1">58</td>
<td class="td_bit" colspan="1">57</td>
<td class="td_bit" colspan="1">56</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ext_mask</td>
</tr>
<tr>
<td class="td_bit" colspan="1">55</td>
<td class="td_bit" colspan="1">54</td>
<td class="td_bit" colspan="1">53</td>
<td class="td_bit" colspan="1">52</td>
<td class="td_bit" colspan="1">51</td>
<td class="td_bit" colspan="1">50</td>
<td class="td_bit" colspan="1">49</td>
<td class="td_bit" colspan="1">48</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ch4_mask</td>
<td class="td_field" colspan="1">ch3_mask</td>
<td class="td_field" colspan="1">ch2_mask</td>
<td class="td_field" colspan="1">ch1_mask</td>
</tr>
<tr>
<td class="td_bit" colspan="1">47</td>
<td class="td_bit" colspan="1">46</td>
<td class="td_bit" colspan="1">45</td>
<td class="td_bit" colspan="1">44</td>
<td class="td_bit" colspan="1">43</td>
<td class="td_bit" colspan="1">42</td>
<td class="td_bit" colspan="1">41</td>
<td class="td_bit" colspan="1">40</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">39</td>
<td class="td_bit" colspan="1">38</td>
<td class="td_bit" colspan="1">37</td>
<td class="td_bit" colspan="1">36</td>
<td class="td_bit" colspan="1">35</td>
<td class="td_bit" colspan="1">34</td>
<td class="td_bit" colspan="1">33</td>
<td class="td_bit" colspan="1">32</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[39:32]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[7:0]</td>
</tr>
</table>
<ul>
<li><b>
ts_sec
</b>[<i>ro</i>]: Seconds part of the timestamp
<li><b>
ch1_mask
</b>[<i>ro</i>]: Set if channel 1 triggered
<li><b>
ch2_mask
</b>[<i>ro</i>]: Set if channel 2 triggered
<li><b>
ch3_mask
</b>[<i>ro</i>]: Set if channel 3 triggered
<li><b>
ch4_mask
</b>[<i>ro</i>]: Set if channel 4 triggered
<li><b>
ext_mask
</b>[<i>ro</i>]: Set if external trigger
</ul>
<a name="ts_cycles"></a>
<h3><a name="sect_3_3">2.3. ts_cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Cycles part of timestamp fifo.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">cycles[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[7:0]</td>
</tr>
</table>
<ul>
<li><b>
cycles
</b>[<i>ro</i>]: Cycles
</ul>
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<BODY>
<h1 class="heading">aux_trigin</h1>
<h3>FMC ADC aux trigger out registers</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#version">version</a></td>
<td class="td_code">version</td>
<td class="td_code">version</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x04</td>
<td>REG</td>
<td><A href="#ctrl">ctrl</a></td>
<td class="td_code">ctrl</td>
<td class="td_code">ctrl</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#seconds">seconds</a></td>
<td class="td_code">seconds</td>
<td class="td_code">seconds</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#cycles">cycles</a></td>
<td class="td_code">cycles</td>
<td class="td_code">cycles</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="version"></a>
<h3><a name="sect_3_1">2.1. version</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">version</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">version</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Core version
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[7:0]</td>
</tr>
</table>
<ul>
<li><b>
version
</b>[<i>ro</i>]: Core version
</ul>
<a name="ctrl"></a>
<h3><a name="sect_3_2">2.2. ctrl</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Control register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">enable</td>
</tr>
</table>
<ul>
<li><b>
enable
</b>[<i>rw</i>]: Enable trigger, cleared when triggered
</ul>
<a name="seconds"></a>
<h3><a name="sect_3_3">2.3. seconds</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">seconds</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">seconds</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) to trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">63</td>
<td class="td_bit" colspan="1">62</td>
<td class="td_bit" colspan="1">61</td>
<td class="td_bit" colspan="1">60</td>
<td class="td_bit" colspan="1">59</td>
<td class="td_bit" colspan="1">58</td>
<td class="td_bit" colspan="1">57</td>
<td class="td_bit" colspan="1">56</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[63:56]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">55</td>
<td class="td_bit" colspan="1">54</td>
<td class="td_bit" colspan="1">53</td>
<td class="td_bit" colspan="1">52</td>
<td class="td_bit" colspan="1">51</td>
<td class="td_bit" colspan="1">50</td>
<td class="td_bit" colspan="1">49</td>
<td class="td_bit" colspan="1">48</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[55:48]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">47</td>
<td class="td_bit" colspan="1">46</td>
<td class="td_bit" colspan="1">45</td>
<td class="td_bit" colspan="1">44</td>
<td class="td_bit" colspan="1">43</td>
<td class="td_bit" colspan="1">42</td>
<td class="td_bit" colspan="1">41</td>
<td class="td_bit" colspan="1">40</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[47:40]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">39</td>
<td class="td_bit" colspan="1">38</td>
<td class="td_bit" colspan="1">37</td>
<td class="td_bit" colspan="1">36</td>
<td class="td_bit" colspan="1">35</td>
<td class="td_bit" colspan="1">34</td>
<td class="td_bit" colspan="1">33</td>
<td class="td_bit" colspan="1">32</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[39:32]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[7:0]</td>
</tr>
</table>
<ul>
<li><b>
seconds
</b>[<i>rw</i>]: Time (seconds) to trigger
</ul>
<a name="cycles"></a>
<h3><a name="sect_3_4">2.4. cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">cycles</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">cycles</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Time (cycles) to trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[7:0]</td>
</tr>
</table>
<ul>
<li><b>
cycles
</b>[<i>rw</i>]: Time (cycles) to trigger
</ul>
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<HEAD>
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<BODY>
<h1 class="heading">aux_trigout</h1>
<h3>FMC ADC aux trigger out registers</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#status">status</a></td>
<td class="td_code">status</td>
<td class="td_code">status</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#ts_mask_sec">ts_mask_sec</a></td>
<td class="td_code">ts_mask_sec</td>
<td class="td_code">ts_mask_sec</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#ts_cycles">ts_cycles</a></td>
<td class="td_code">ts_cycles</td>
<td class="td_code">ts_cycles</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="status"></a>
<h3><a name="sect_3_1">2.1. status</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">status</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">status</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Status register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ts_present</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">wr_valid</td>
<td class="td_field" colspan="1">wr_link</td>
<td class="td_field" colspan="1">wr_enable</td>
</tr>
</table>
<ul>
<li><b>
wr_enable
</b>[<i>ro</i>]: Set when WR is enabled
<li><b>
wr_link
</b>[<i>ro</i>]: WR link status
<li><b>
wr_valid
</b>[<i>ro</i>]: Set when WR time is valid
<li><b>
ts_present
</b>[<i>ro</i>]: Set when the timestamp fifo is not empty
</ul>
<a name="ts_mask_sec"></a>
<h3><a name="sect_3_2">2.2. ts_mask_sec</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) of the last event
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">63</td>
<td class="td_bit" colspan="1">62</td>
<td class="td_bit" colspan="1">61</td>
<td class="td_bit" colspan="1">60</td>
<td class="td_bit" colspan="1">59</td>
<td class="td_bit" colspan="1">58</td>
<td class="td_bit" colspan="1">57</td>
<td class="td_bit" colspan="1">56</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ext_mask</td>
</tr>
<tr>
<td class="td_bit" colspan="1">55</td>
<td class="td_bit" colspan="1">54</td>
<td class="td_bit" colspan="1">53</td>
<td class="td_bit" colspan="1">52</td>
<td class="td_bit" colspan="1">51</td>
<td class="td_bit" colspan="1">50</td>
<td class="td_bit" colspan="1">49</td>
<td class="td_bit" colspan="1">48</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ch4_mask</td>
<td class="td_field" colspan="1">ch3_mask</td>
<td class="td_field" colspan="1">ch2_mask</td>
<td class="td_field" colspan="1">ch1_mask</td>
</tr>
<tr>
<td class="td_bit" colspan="1">47</td>
<td class="td_bit" colspan="1">46</td>
<td class="td_bit" colspan="1">45</td>
<td class="td_bit" colspan="1">44</td>
<td class="td_bit" colspan="1">43</td>
<td class="td_bit" colspan="1">42</td>
<td class="td_bit" colspan="1">41</td>
<td class="td_bit" colspan="1">40</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">39</td>
<td class="td_bit" colspan="1">38</td>
<td class="td_bit" colspan="1">37</td>
<td class="td_bit" colspan="1">36</td>
<td class="td_bit" colspan="1">35</td>
<td class="td_bit" colspan="1">34</td>
<td class="td_bit" colspan="1">33</td>
<td class="td_bit" colspan="1">32</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[39:32]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[7:0]</td>
</tr>
</table>
<ul>
<li><b>
ts_sec
</b>[<i>ro</i>]: Seconds part of the timestamp
<li><b>
ch1_mask
</b>[<i>ro</i>]: Set if channel 1 triggered
<li><b>
ch2_mask
</b>[<i>ro</i>]: Set if channel 2 triggered
<li><b>
ch3_mask
</b>[<i>ro</i>]: Set if channel 3 triggered
<li><b>
ch4_mask
</b>[<i>ro</i>]: Set if channel 4 triggered
<li><b>
ext_mask
</b>[<i>ro</i>]: Set if external trigger
</ul>
<a name="ts_cycles"></a>
<h3><a name="sect_3_3">2.3. ts_cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Cycles part of timestamp fifo.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">cycles[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[7:0]</td>
</tr>
</table>
<ul>
<li><b>
cycles
</b>[<i>ro</i>]: Cycles
</ul>
</BODY>
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<HEAD>
<TITLE>spec_carrier_csr</TITLE>
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<BODY>
<h1 class="heading">spec_carrier_csr</h1>
<h3>Carrier control and status registers</h3>
<p>Wishbone slave for control and status registers related to the FMC carrier</p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x0</td>
<td>REG</td>
<td><A href="#carrier">carrier</a></td>
<td class="td_code">carrier</td>
<td class="td_code">carrier</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x4</td>
<td>REG</td>
<td><A href="#stat">stat</a></td>
<td class="td_code">stat</td>
<td class="td_code">stat</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x8</td>
<td>REG</td>
<td><A href="#ctrl">ctrl</a></td>
<td class="td_code">ctrl</td>
<td class="td_code">ctrl</td>
</tr>
<tr class="tr_even">
<td class="td_code">0xc</td>
<td>REG</td>
<td><A href="#rst">rst</a></td>
<td class="td_code">rst</td>
<td class="td_code">rst</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="carrier"></a>
<h3><a name="sect_3_1">2.1. carrier</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">carrier</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">carrier</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Carrier type and PCB version
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">type[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">type[7:0]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">reserved[11:4]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="4">reserved[3:0]</td>
<td class="td_field" colspan="4">pcb_rev[3:0]</td>
</tr>
</table>
<ul>
<li><b>
pcb_rev
</b>[<i>ro</i>]: PCB revision
<br>Binary coded PCB layout revision.
<li><b>
reserved
</b>[<i>ro</i>]: Reserved register
<br>Ignore on read, write with 0's.
<li><b>
type
</b>[<i>ro</i>]: Carrier type
<br>Carrier type identifier<br>1 = SPEC<br>2 = SVEC<br>3 = VFC<br>4 = SPEXI
</ul>
<a name="stat"></a>
<h3><a name="sect_3_2">2.2. stat</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">stat</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">stat</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Status
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ddr3_cal_done</td>
<td class="td_field" colspan="1">sys_pll_lck</td>
<td class="td_field" colspan="1">p2l_pll_lck</td>
<td class="td_field" colspan="1">fmc_pres</td>
</tr>
</table>
<ul>
<li><b>
fmc_pres
</b>[<i>ro</i>]: FMC presence
<br>0: FMC slot is populated<br>1: FMC slot is not populated.
<li><b>
p2l_pll_lck
</b>[<i>ro</i>]: GN4142 core P2L PLL status
<br>0: not locked<br>1: locked.
<li><b>
sys_pll_lck
</b>[<i>ro</i>]: System clock PLL status
<br>0: not locked<br>1: locked.
<li><b>
ddr3_cal_done
</b>[<i>ro</i>]: DDR3 calibration status
<br>0: not done<br>1: done.
</ul>
<a name="ctrl"></a>
<h3><a name="sect_3_3">2.3. ctrl</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Control
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">led_red</td>
<td class="td_field" colspan="1">led_green</td>
</tr>
</table>
<ul>
<li><b>
led_green
</b>[<i>rw</i>]: Green LED
<br>Manual control of the front panel green LED (unused in the fmc-adc application)
<li><b>
led_red
</b>[<i>rw</i>]: Red LED
<br>Manual control of the front panel red LED (unused in the fmc-adc application)
</ul>
<a name="rst"></a>
<h3><a name="sect_3_4">2.4. rst</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">rst</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0xc</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">rst</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0xc</td></tr>
</table>
<p>
Reset Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">fmc0</td>
</tr>
</table>
<ul>
<li><b>
fmc0
</b>[<i>wo</i>]: State of the reset line
<br>write 0: Normal FMC operation<br>write 1: FMC is held in reset
</ul>
</BODY>
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<HTML>
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<h1 class="heading">svec_carrier_csr</h1>
<h3>SVEC carrier control and status registers</h3>
<p>Wishbone slave for control and status registers related to the SVEC FMC carrier</p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x0</td>
<td>REG</td>
<td><A href="#carrier">carrier</a></td>
<td class="td_code">carrier</td>
<td class="td_code">carrier</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x4</td>
<td>REG</td>
<td><A href="#stat">stat</a></td>
<td class="td_code">stat</td>
<td class="td_code">stat</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x8</td>
<td>REG</td>
<td><A href="#ctrl">ctrl</a></td>
<td class="td_code">ctrl</td>
<td class="td_code">ctrl</td>
</tr>
<tr class="tr_even">
<td class="td_code">0xc</td>
<td>REG</td>
<td><A href="#rst">rst</a></td>
<td class="td_code">rst</td>
<td class="td_code">rst</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="carrier"></a>
<h3><a name="sect_3_1">2.1. carrier</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">carrier</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">carrier</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Carrier type and PCB version
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">type[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">type[7:0]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">reserved[10:3]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="3">reserved[2:0]</td>
<td class="td_field" colspan="5">pcb_rev[4:0]</td>
</tr>
</table>
<ul>
<li><b>
pcb_rev
</b>[<i>ro</i>]: PCB revision
<br>Binary coded PCB layout revision.
<li><b>
reserved
</b>[<i>ro</i>]: Reserved register
<br>Ignore on read, write with 0's.
<li><b>
type
</b>[<i>ro</i>]: Carrier type
<br>Carrier type identifier<br>1 = SPEC<br>2 = SVEC<br>3 = VFC<br>4 = SPEXI
</ul>
<a name="stat"></a>
<h3><a name="sect_3_2">2.2. stat</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">stat</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">stat</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Status
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ddr1_cal_done</td>
<td class="td_field" colspan="1">ddr0_cal_done</td>
<td class="td_field" colspan="1">sys_pll_lck</td>
<td class="td_field" colspan="1">fmc1_pres</td>
<td class="td_field" colspan="1">fmc0_pres</td>
</tr>
</table>
<ul>
<li><b>
fmc0_pres
</b>[<i>ro</i>]: FMC 1 presence
<br>0: FMC slot 1 is populated<br>1: FMC slot 1 is not populated.
<li><b>
fmc1_pres
</b>[<i>ro</i>]: FMC 2 presence
<br>0: FMC slot 2 is populated<br>1: FMC slot 2 is not populated.
<li><b>
sys_pll_lck
</b>[<i>ro</i>]: System clock PLL status
<br>0: not locked<br>1: locked.
<li><b>
ddr0_cal_done
</b>[<i>ro</i>]: DDR3 bank 4 calibration status
<br>0: not done<br>1: done.
<li><b>
ddr1_cal_done
</b>[<i>ro</i>]: DDR3 bank 5 calibration status
<br>0: not done<br>1: done.
</ul>
<a name="ctrl"></a>
<h3><a name="sect_3_3">2.3. ctrl</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Control
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">fp_leds_man[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">fp_leds_man[7:0]</td>
</tr>
</table>
<ul>
<li><b>
fp_leds_man
</b>[<i>rw</i>]: Front panel LED manual control
<br>Height front panel LED, two bits per LED.<br>00 = OFF<br>01 = Green<br>10 = Red<br>11 = Orange
</ul>
<a name="rst"></a>
<h3><a name="sect_3_4">2.4. rst</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">rst</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0xc</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">rst</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0xc</td></tr>
</table>
<p>
Reset Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">fmc1</td>
<td class="td_field" colspan="1">fmc0</td>
</tr>
</table>
<ul>
<li><b>
fmc0
</b>[<i>wo</i>]: State of the FMC 1 reset line
<br>write 0: Normal FMC operation<br>write 1: FMC is held in reset
<li><b>
fmc1
</b>[<i>wo</i>]: State of the FMC 2 reset line
<br>write 0: Normal FMC operation<br>write 1: FMC is held in reset
</ul>
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<h1 class="heading">timetag_core_regs</h1>
<h3>Time-tagging core registers</h3>
<p>Wishbone slave for registers related to time-tagging core</p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>HW address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#seconds_upper">seconds_upper</a></td>
<td class="td_code">seconds_upper</td>
<td class="td_code">seconds_upper</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x04</td>
<td>REG</td>
<td><A href="#seconds_lower">seconds_lower</a></td>
<td class="td_code">seconds_lower</td>
<td class="td_code">seconds_lower</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#coarse">coarse</a></td>
<td class="td_code">coarse</td>
<td class="td_code">coarse</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x0c</td>
<td>REG</td>
<td><A href="#time_trig_seconds_upper">time_trig_seconds_upper</a></td>
<td class="td_code">time_trig_seconds_upper</td>
<td class="td_code">time_trig_seconds_upper</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#time_trig_seconds_lower">time_trig_seconds_lower</a></td>
<td class="td_code">time_trig_seconds_lower</td>
<td class="td_code">time_trig_seconds_lower</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x14</td>
<td>REG</td>
<td><A href="#time_trig_coarse">time_trig_coarse</a></td>
<td class="td_code">time_trig_coarse</td>
<td class="td_code">time_trig_coarse</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x18</td>
<td>REG</td>
<td><A href="#trig_tag_seconds_upper">trig_tag_seconds_upper</a></td>
<td class="td_code">trig_tag_seconds_upper</td>
<td class="td_code">trig_tag_seconds_upper</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x1c</td>
<td>REG</td>
<td><A href="#trig_tag_seconds_lower">trig_tag_seconds_lower</a></td>
<td class="td_code">trig_tag_seconds_lower</td>
<td class="td_code">trig_tag_seconds_lower</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x20</td>
<td>REG</td>
<td><A href="#trig_tag_coarse">trig_tag_coarse</a></td>
<td class="td_code">trig_tag_coarse</td>
<td class="td_code">trig_tag_coarse</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x24</td>
<td>REG</td>
<td><A href="#acq_start_tag_seconds_upper">acq_start_tag_seconds_upper</a></td>
<td class="td_code">acq_start_tag_seconds_upper</td>
<td class="td_code">acq_start_tag_seconds_upper</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x28</td>
<td>REG</td>
<td><A href="#acq_start_tag_seconds_lower">acq_start_tag_seconds_lower</a></td>
<td class="td_code">acq_start_tag_seconds_lower</td>
<td class="td_code">acq_start_tag_seconds_lower</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x2c</td>
<td>REG</td>
<td><A href="#acq_start_tag_coarse">acq_start_tag_coarse</a></td>
<td class="td_code">acq_start_tag_coarse</td>
<td class="td_code">acq_start_tag_coarse</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x30</td>
<td>REG</td>
<td><A href="#acq_stop_tag_seconds_upper">acq_stop_tag_seconds_upper</a></td>
<td class="td_code">acq_stop_tag_seconds_upper</td>
<td class="td_code">acq_stop_tag_seconds_upper</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x34</td>
<td>REG</td>
<td><A href="#acq_stop_tag_seconds_lower">acq_stop_tag_seconds_lower</a></td>
<td class="td_code">acq_stop_tag_seconds_lower</td>
<td class="td_code">acq_stop_tag_seconds_lower</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x38</td>
<td>REG</td>
<td><A href="#acq_stop_tag_coarse">acq_stop_tag_coarse</a></td>
<td class="td_code">acq_stop_tag_coarse</td>
<td class="td_code">acq_stop_tag_coarse</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x3c</td>
<td>REG</td>
<td><A href="#acq_end_tag_seconds_upper">acq_end_tag_seconds_upper</a></td>
<td class="td_code">acq_end_tag_seconds_upper</td>
<td class="td_code">acq_end_tag_seconds_upper</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x40</td>
<td>REG</td>
<td><A href="#acq_end_tag_seconds_lower">acq_end_tag_seconds_lower</a></td>
<td class="td_code">acq_end_tag_seconds_lower</td>
<td class="td_code">acq_end_tag_seconds_lower</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x44</td>
<td>REG</td>
<td><A href="#acq_end_tag_coarse">acq_end_tag_coarse</a></td>
<td class="td_code">acq_end_tag_coarse</td>
<td class="td_code">acq_end_tag_coarse</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="seconds_upper"></a>
<h3><a name="sect_3_1">2.1. seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Timetag seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
seconds_upper
</b>[<i>rw</i>]: Timetag seconds
</ul>
<a name="seconds_lower"></a>
<h3><a name="sect_3_2">2.2. seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Timetag seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
seconds_lower
</b>[<i>rw</i>]: Timetag seconds register (lower)
</ul>
<a name="coarse"></a>
<h3><a name="sect_3_3">2.3. coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Timetag coarse time register, system clock ticks (125MHz)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
coarse
</b>[<i>rw</i>]: Timetag coarse time
</ul>
<a name="time_trig_seconds_upper"></a>
<h3><a name="sect_3_4">2.4. time_trig_seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">time_trig_seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0xc</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">time_trig_seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0xc</td></tr>
</table>
<p>
Time trigger seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
time_trig_seconds_upper
</b>[<i>rw</i>]: Time trigger seconds
</ul>
<a name="time_trig_seconds_lower"></a>
<h3><a name="sect_3_5">2.5. time_trig_seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">time_trig_seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">time_trig_seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Time trigger seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
time_trig_seconds_lower
</b>[<i>rw</i>]: Time trigger seconds register (lower)
</ul>
<a name="time_trig_coarse"></a>
<h3><a name="sect_3_6">2.6. time_trig_coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">time_trig_coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x14</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">time_trig_coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x14</td></tr>
</table>
<p>
Time trigger coarse time register, system clock ticks (125MHz)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">time_trig_coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">time_trig_coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
time_trig_coarse
</b>[<i>rw</i>]: Time trigger coarse value
</ul>
<a name="trig_tag_seconds_upper"></a>
<h3><a name="sect_3_7">2.7. trig_tag_seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">trig_tag_seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x18</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">trig_tag_seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x18</td></tr>
</table>
<p>
Trigger time-tag seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
trig_tag_seconds_upper
</b>[<i>ro</i>]: Trigger time-tag seconds
<br>Holds time-tag seconds of the last trigger event
</ul>
<a name="trig_tag_seconds_lower"></a>
<h3><a name="sect_3_8">2.8. trig_tag_seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">trig_tag_seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x1c</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">trig_tag_seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x1c</td></tr>
</table>
<p>
Trigger time-tag seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
trig_tag_seconds_lower
</b>[<i>ro</i>]: Trigger time-tag seconds register (lower)
</ul>
<a name="trig_tag_coarse"></a>
<h3><a name="sect_3_9">2.9. trig_tag_coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">trig_tag_coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x20</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">trig_tag_coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x20</td></tr>
</table>
<p>
Trigger time-tag coarse time (system clock ticks 125MHz) register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">trig_tag_coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">trig_tag_coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
trig_tag_coarse
</b>[<i>ro</i>]: Trigger time-tag coarse time
<br>Holds time-tag coarse time of the last trigger event
</ul>
<a name="acq_start_tag_seconds_upper"></a>
<h3><a name="sect_3_10">2.10. acq_start_tag_seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_start_tag_seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x24</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_start_tag_seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x24</td></tr>
</table>
<p>
Acquisition start time-tag seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_start_tag_seconds_upper
</b>[<i>ro</i>]: Acquisition start time-tag seconds
<br>Holds time-tag seconds of the last acquisition start event
</ul>
<a name="acq_start_tag_seconds_lower"></a>
<h3><a name="sect_3_11">2.11. acq_start_tag_seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_start_tag_seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x28</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_start_tag_seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x28</td></tr>
</table>
<p>
Acquisition start time-tag seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_start_tag_seconds_lower
</b>[<i>ro</i>]: Acquisition start time-tag seconds register (lower)
</ul>
<a name="acq_start_tag_coarse"></a>
<h3><a name="sect_3_12">2.12. acq_start_tag_coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_start_tag_coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x2c</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_start_tag_coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x2c</td></tr>
</table>
<p>
Acquisition start time-tag coarse time (system clock ticks 125MHz) register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">acq_start_tag_coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_start_tag_coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_start_tag_coarse
</b>[<i>ro</i>]: Acquisition start time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition start event
</ul>
<a name="acq_stop_tag_seconds_upper"></a>
<h3><a name="sect_3_13">2.13. acq_stop_tag_seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_stop_tag_seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x30</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_stop_tag_seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x30</td></tr>
</table>
<p>
Acquisition stop time-tag seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_stop_tag_seconds_upper
</b>[<i>ro</i>]: Acquisition stop time-tag seconds
<br>Holds time-tag seconds of the last acquisition stop event
</ul>
<a name="acq_stop_tag_seconds_lower"></a>
<h3><a name="sect_3_14">2.14. acq_stop_tag_seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_stop_tag_seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x34</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_stop_tag_seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x34</td></tr>
</table>
<p>
Acquisition stop time-tag seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_stop_tag_seconds_lower
</b>[<i>ro</i>]: Acquisition stop time-tag seconds register (lower)
</ul>
<a name="acq_stop_tag_coarse"></a>
<h3><a name="sect_3_15">2.15. acq_stop_tag_coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_stop_tag_coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x38</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_stop_tag_coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x38</td></tr>
</table>
<p>
Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">acq_stop_tag_coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_stop_tag_coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_stop_tag_coarse
</b>[<i>ro</i>]: Acquisition stop time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition stop event
</ul>
<a name="acq_end_tag_seconds_upper"></a>
<h3><a name="sect_3_16">2.16. acq_end_tag_seconds_upper</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_end_tag_seconds_upper</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x3c</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_end_tag_seconds_upper</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x3c</td></tr>
</table>
<p>
Acquisition end time-tag seconds register (upper)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_seconds_upper[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_end_tag_seconds_upper
</b>[<i>ro</i>]: Acquisition end time-tag seconds
<br>Holds time-tag seconds of the last acquisition end event
</ul>
<a name="acq_end_tag_seconds_lower"></a>
<h3><a name="sect_3_17">2.17. acq_end_tag_seconds_lower</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_end_tag_seconds_lower</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x40</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_end_tag_seconds_lower</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x40</td></tr>
</table>
<p>
Acquisition end time-tag seconds register (lower)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_seconds_lower[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_seconds_lower[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_seconds_lower[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_seconds_lower[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_end_tag_seconds_lower
</b>[<i>ro</i>]: Acquisition end time-tag seconds register (lower)
</ul>
<a name="acq_end_tag_coarse"></a>
<h3><a name="sect_3_18">2.18. acq_end_tag_coarse</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">acq_end_tag_coarse</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x44</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">acq_end_tag_coarse</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x44</td></tr>
</table>
<p>
Acquisition end time-tag coarse time (system clock ticks 125MHz) register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">acq_end_tag_coarse[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_coarse[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_coarse[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">acq_end_tag_coarse[7:0]</td>
</tr>
</table>
<ul>
<li><b>
acq_end_tag_coarse
</b>[<i>ro</i>]: Acquisition end time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition end event
</ul>
</BODY>
</HTML>
hdl/rtl/Makefile → hdl/cheby/Makefile
View file @ 920b7a16
SIM =../testbench/include
DOC =../../doc/manual
SW =../../software/include/hw
SOURCES = $(wildcard *.cheby)
......@@ -13,6 +12,5 @@ $(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< \
--gen-doc=$(DOC)/$(@:.vhd=.html) \
--gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h)
hdl/rtl/fmc_adc_100Ms_csr.cheby → hdl/cheby/fmc_adc_100Ms_csr.cheby
View file @ 920b7a16
memory-map:
bus: wb-32-be
name: fmc_adc_100ms_csr
size: 0x200
description: FMC ADC 100MS/s core registers
comment: |
Wishbone slave for FMC ADC 100MS/s core
......
hdl/cheby/fmc_adc_mezzanine_mmap.cheby 0 → 100644
View file @ 920b7a16
memory-map:
name: fmc_adc_mezzanine_mmap
bus: wb-32-be
description: FMC-ADC-100M mezzanine memory map
size: 0x2000
x-hdl:
busgroup: True
children:
- submap:
name: fmc_adc_100m_csr
address: 0x1000
description: FMC ADC 100M CSR
filename: fmc_adc_100Ms_csr.cheby
- submap:
name: fmc_i2c_master
address: 0x1400
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
description: Mezzanine system management I2C master
- submap:
name: fmc_adc_eic
address: 0x1500
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
description: FMC ADC Embedded Interrupt Controller
- submap:
name: si570_i2c_master
address: 0x1600
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
description: Si570 control I2C master
- submap:
name: ds18b20_onewire_master
address: 0x1700
size: 0x100
interface: wb-32-be
x-hdl:
busgroup: True
description: DS18B20 OneWire master
- submap:
name: fmc_spi_master
address: 0x1800
size: 0x20
interface: wb-32-be
x-hdl:
busgroup: True
description: Mezzanine SPI master (ADC control + DAC offsets)
- submap:
name: timetag_core
address: 0x1900
description: Timetag Core
filename: timetag_core_regs.cheby
hdl/cheby/fmc_adc_mezzanine_mmap.vhd 0 → 100644
View file @ 920b7a16
-- Do not edit; this file was generated by Cheby using these options:
-- -i fmc_adc_mezzanine_mmap.cheby --gen-hdl=fmc_adc_mezzanine_mmap.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity fmc_adc_mezzanine_mmap is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- FMC ADC 100M CSR
fmc_adc_100m_csr_i : in t_wishbone_master_in;
fmc_adc_100m_csr_o : out t_wishbone_master_out;
-- Mezzanine system management I2C master
fmc_i2c_master_i : in t_wishbone_master_in;
fmc_i2c_master_o : out t_wishbone_master_out;
-- FMC ADC Embedded Interrupt Controller
fmc_adc_eic_i : in t_wishbone_master_in;
fmc_adc_eic_o : out t_wishbone_master_out;
-- Si570 control I2C master
si570_i2c_master_i : in t_wishbone_master_in;
si570_i2c_master_o : out t_wishbone_master_out;
-- DS18B20 OneWire master
ds18b20_onewire_master_i : in t_wishbone_master_in;
ds18b20_onewire_master_o : out t_wishbone_master_out;
-- Mezzanine SPI master (ADC control + DAC offsets)
fmc_spi_master_i : in t_wishbone_master_in;
fmc_spi_master_o : out t_wishbone_master_out;
-- Timetag Core
timetag_core_i : in t_wishbone_master_in;
timetag_core_o : out t_wishbone_master_out
);
end fmc_adc_mezzanine_mmap;
architecture syn of fmc_adc_mezzanine_mmap is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal fmc_adc_100m_csr_re : std_logic;
signal fmc_adc_100m_csr_wt : std_logic;
signal fmc_adc_100m_csr_rt : std_logic;
signal fmc_adc_100m_csr_tr : std_logic;
signal fmc_adc_100m_csr_wack : std_logic;
signal fmc_adc_100m_csr_rack : std_logic;
signal fmc_i2c_master_re : std_logic;
signal fmc_i2c_master_wt : std_logic;
signal fmc_i2c_master_rt : std_logic;
signal fmc_i2c_master_tr : std_logic;
signal fmc_i2c_master_wack : std_logic;
signal fmc_i2c_master_rack : std_logic;
signal fmc_adc_eic_re : std_logic;
signal fmc_adc_eic_wt : std_logic;
signal fmc_adc_eic_rt : std_logic;
signal fmc_adc_eic_tr : std_logic;
signal fmc_adc_eic_wack : std_logic;
signal fmc_adc_eic_rack : std_logic;
signal si570_i2c_master_re : std_logic;
signal si570_i2c_master_wt : std_logic;
signal si570_i2c_master_rt : std_logic;
signal si570_i2c_master_tr : std_logic;
signal si570_i2c_master_wack : std_logic;
signal si570_i2c_master_rack : std_logic;
signal ds18b20_onewire_master_re : std_logic;
signal ds18b20_onewire_master_wt : std_logic;
signal ds18b20_onewire_master_rt : std_logic;
signal ds18b20_onewire_master_tr : std_logic;
signal ds18b20_onewire_master_wack : std_logic;
signal ds18b20_onewire_master_rack : std_logic;
signal fmc_spi_master_re : std_logic;
signal fmc_spi_master_wt : std_logic;
signal fmc_spi_master_rt : std_logic;
signal fmc_spi_master_tr : std_logic;
signal fmc_spi_master_wack : std_logic;
signal fmc_spi_master_rack : std_logic;
signal timetag_core_re : std_logic;
signal timetag_core_wt : std_logic;
signal timetag_core_rt : std_logic;
signal timetag_core_tr : std_logic;
signal timetag_core_wack : std_logic;
signal timetag_core_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- Assignments for submap fmc_adc_100m_csr
fmc_adc_100m_csr_tr <= fmc_adc_100m_csr_wt or fmc_adc_100m_csr_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_adc_100m_csr_rt <= '0';
else
fmc_adc_100m_csr_rt <= (fmc_adc_100m_csr_rt or fmc_adc_100m_csr_re) and not fmc_adc_100m_csr_rack;
end if;
end if;
end process;
fmc_adc_100m_csr_o.cyc <= fmc_adc_100m_csr_tr;
fmc_adc_100m_csr_o.stb <= fmc_adc_100m_csr_tr;
fmc_adc_100m_csr_wack <= fmc_adc_100m_csr_i.ack and fmc_adc_100m_csr_wt;
fmc_adc_100m_csr_rack <= fmc_adc_100m_csr_i.ack and fmc_adc_100m_csr_rt;
fmc_adc_100m_csr_o.adr <= ((22 downto 0 => '0') & wb_i.adr(8 downto 2)) & (1 downto 0 => '0');
fmc_adc_100m_csr_o.sel <= (others => '1');
fmc_adc_100m_csr_o.we <= fmc_adc_100m_csr_wt;
fmc_adc_100m_csr_o.dat <= wb_i.dat;
-- Assignments for submap fmc_i2c_master
fmc_i2c_master_tr <= fmc_i2c_master_wt or fmc_i2c_master_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_i2c_master_rt <= '0';
else
fmc_i2c_master_rt <= (fmc_i2c_master_rt or fmc_i2c_master_re) and not fmc_i2c_master_rack;
end if;
end if;
end process;
fmc_i2c_master_o.cyc <= fmc_i2c_master_tr;
fmc_i2c_master_o.stb <= fmc_i2c_master_tr;
fmc_i2c_master_wack <= fmc_i2c_master_i.ack and fmc_i2c_master_wt;
fmc_i2c_master_rack <= fmc_i2c_master_i.ack and fmc_i2c_master_rt;
fmc_i2c_master_o.adr <= ((23 downto 0 => '0') & wb_i.adr(7 downto 2)) & (1 downto 0 => '0');
fmc_i2c_master_o.sel <= (others => '1');
fmc_i2c_master_o.we <= fmc_i2c_master_wt;
fmc_i2c_master_o.dat <= wb_i.dat;
-- Assignments for submap fmc_adc_eic
fmc_adc_eic_tr <= fmc_adc_eic_wt or fmc_adc_eic_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_adc_eic_rt <= '0';
else
fmc_adc_eic_rt <= (fmc_adc_eic_rt or fmc_adc_eic_re) and not fmc_adc_eic_rack;
end if;
end if;
end process;
fmc_adc_eic_o.cyc <= fmc_adc_eic_tr;
fmc_adc_eic_o.stb <= fmc_adc_eic_tr;
fmc_adc_eic_wack <= fmc_adc_eic_i.ack and fmc_adc_eic_wt;
fmc_adc_eic_rack <= fmc_adc_eic_i.ack and fmc_adc_eic_rt;
fmc_adc_eic_o.adr <= ((27 downto 0 => '0') & wb_i.adr(3 downto 2)) & (1 downto 0 => '0');
fmc_adc_eic_o.sel <= (others => '1');
fmc_adc_eic_o.we <= fmc_adc_eic_wt;
fmc_adc_eic_o.dat <= wb_i.dat;
-- Assignments for submap si570_i2c_master
si570_i2c_master_tr <= si570_i2c_master_wt or si570_i2c_master_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
si570_i2c_master_rt <= '0';
else
si570_i2c_master_rt <= (si570_i2c_master_rt or si570_i2c_master_re) and not si570_i2c_master_rack;
end if;
end if;
end process;
si570_i2c_master_o.cyc <= si570_i2c_master_tr;
si570_i2c_master_o.stb <= si570_i2c_master_tr;
si570_i2c_master_wack <= si570_i2c_master_i.ack and si570_i2c_master_wt;
si570_i2c_master_rack <= si570_i2c_master_i.ack and si570_i2c_master_rt;
si570_i2c_master_o.adr <= ((23 downto 0 => '0') & wb_i.adr(7 downto 2)) & (1 downto 0 => '0');
si570_i2c_master_o.sel <= (others => '1');
si570_i2c_master_o.we <= si570_i2c_master_wt;
si570_i2c_master_o.dat <= wb_i.dat;
-- Assignments for submap ds18b20_onewire_master
ds18b20_onewire_master_tr <= ds18b20_onewire_master_wt or ds18b20_onewire_master_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ds18b20_onewire_master_rt <= '0';
else
ds18b20_onewire_master_rt <= (ds18b20_onewire_master_rt or ds18b20_onewire_master_re) and not ds18b20_onewire_master_rack;
end if;
end if;
end process;
ds18b20_onewire_master_o.cyc <= ds18b20_onewire_master_tr;
ds18b20_onewire_master_o.stb <= ds18b20_onewire_master_tr;
ds18b20_onewire_master_wack <= ds18b20_onewire_master_i.ack and ds18b20_onewire_master_wt;
ds18b20_onewire_master_rack <= ds18b20_onewire_master_i.ack and ds18b20_onewire_master_rt;
ds18b20_onewire_master_o.adr <= ((23 downto 0 => '0') & wb_i.adr(7 downto 2)) & (1 downto 0 => '0');
ds18b20_onewire_master_o.sel <= (others => '1');
ds18b20_onewire_master_o.we <= ds18b20_onewire_master_wt;
ds18b20_onewire_master_o.dat <= wb_i.dat;
-- Assignments for submap fmc_spi_master
fmc_spi_master_tr <= fmc_spi_master_wt or fmc_spi_master_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_spi_master_rt <= '0';
else
fmc_spi_master_rt <= (fmc_spi_master_rt or fmc_spi_master_re) and not fmc_spi_master_rack;
end if;
end if;
end process;
fmc_spi_master_o.cyc <= fmc_spi_master_tr;
fmc_spi_master_o.stb <= fmc_spi_master_tr;
fmc_spi_master_wack <= fmc_spi_master_i.ack and fmc_spi_master_wt;
fmc_spi_master_rack <= fmc_spi_master_i.ack and fmc_spi_master_rt;
fmc_spi_master_o.adr <= ((26 downto 0 => '0') & wb_i.adr(4 downto 2)) & (1 downto 0 => '0');
fmc_spi_master_o.sel <= (others => '1');
fmc_spi_master_o.we <= fmc_spi_master_wt;
fmc_spi_master_o.dat <= wb_i.dat;
-- Assignments for submap timetag_core
timetag_core_tr <= timetag_core_wt or timetag_core_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
timetag_core_rt <= '0';
else
timetag_core_rt <= (timetag_core_rt or timetag_core_re) and not timetag_core_rack;
end if;
end if;
end process;
timetag_core_o.cyc <= timetag_core_tr;
timetag_core_o.stb <= timetag_core_tr;
timetag_core_wack <= timetag_core_i.ack and timetag_core_wt;
timetag_core_rack <= timetag_core_i.ack and timetag_core_rt;
timetag_core_o.adr <= ((24 downto 0 => '0') & wb_i.adr(6 downto 2)) & (1 downto 0 => '0');
timetag_core_o.sel <= (others => '1');
timetag_core_o.we <= timetag_core_wt;
timetag_core_o.dat <= wb_i.dat;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
fmc_adc_100m_csr_wt <= '0';
fmc_i2c_master_wt <= '0';
fmc_adc_eic_wt <= '0';
si570_i2c_master_wt <= '0';
ds18b20_onewire_master_wt <= '0';
fmc_spi_master_wt <= '0';
timetag_core_wt <= '0';
else
wr_ack_int <= '0';
fmc_adc_100m_csr_wt <= '0';
fmc_i2c_master_wt <= '0';
fmc_adc_eic_wt <= '0';
si570_i2c_master_wt <= '0';
ds18b20_onewire_master_wt <= '0';
fmc_spi_master_wt <= '0';
timetag_core_wt <= '0';
case wb_i.adr(12 downto 9) is
when "1000" =>
-- Submap fmc_adc_100m_csr
fmc_adc_100m_csr_wt <= (fmc_adc_100m_csr_wt or wr_int) and not fmc_adc_100m_csr_wack;
wr_ack_int <= fmc_adc_100m_csr_wack;
when "1010" =>
case wb_i.adr(8 downto 8) is
when "0" =>
-- Submap fmc_i2c_master
fmc_i2c_master_wt <= (fmc_i2c_master_wt or wr_int) and not fmc_i2c_master_wack;
wr_ack_int <= fmc_i2c_master_wack;
when "1" =>
-- Submap fmc_adc_eic
fmc_adc_eic_wt <= (fmc_adc_eic_wt or wr_int) and not fmc_adc_eic_wack;
wr_ack_int <= fmc_adc_eic_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "1011" =>
case wb_i.adr(8 downto 8) is
when "0" =>
-- Submap si570_i2c_master
si570_i2c_master_wt <= (si570_i2c_master_wt or wr_int) and not si570_i2c_master_wack;
wr_ack_int <= si570_i2c_master_wack;
when "1" =>
-- Submap ds18b20_onewire_master
ds18b20_onewire_master_wt <= (ds18b20_onewire_master_wt or wr_int) and not ds18b20_onewire_master_wack;
wr_ack_int <= ds18b20_onewire_master_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "1100" =>
case wb_i.adr(8 downto 7) is
when "00" =>
-- Submap fmc_spi_master
fmc_spi_master_wt <= (fmc_spi_master_wt or wr_int) and not fmc_spi_master_wack;
wr_ack_int <= fmc_spi_master_wack;
when "10" =>
-- Submap timetag_core
timetag_core_wt <= (timetag_core_wt or wr_int) and not timetag_core_wack;
wr_ack_int <= timetag_core_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(12 downto 9) is
when "1000" =>
when "1010" =>
case wb_i.adr(8 downto 8) is
when "0" =>
when "1" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "1011" =>
case wb_i.adr(8 downto 8) is
when "0" =>
when "1" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "1100" =>
case wb_i.adr(8 downto 7) is
when "00" =>
when "10" =>
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int, rd_int, fmc_adc_100m_csr_i.dat, fmc_adc_100m_csr_rack, fmc_adc_100m_csr_rt, rd_int, fmc_i2c_master_i.dat, fmc_i2c_master_rack, fmc_i2c_master_rt, rd_int, fmc_adc_eic_i.dat, fmc_adc_eic_rack, fmc_adc_eic_rt, rd_int, si570_i2c_master_i.dat, si570_i2c_master_rack, si570_i2c_master_rt, rd_int, ds18b20_onewire_master_i.dat, ds18b20_onewire_master_rack, ds18b20_onewire_master_rt, rd_int, fmc_spi_master_i.dat, fmc_spi_master_rack, fmc_spi_master_rt, rd_int, timetag_core_i.dat, timetag_core_rack, timetag_core_rt) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
fmc_adc_100m_csr_re <= '0';
fmc_i2c_master_re <= '0';
fmc_adc_eic_re <= '0';
si570_i2c_master_re <= '0';
ds18b20_onewire_master_re <= '0';
fmc_spi_master_re <= '0';
timetag_core_re <= '0';
case wb_i.adr(12 downto 9) is
when "1000" =>
-- Submap fmc_adc_100m_csr
fmc_adc_100m_csr_re <= rd_int;
wb_o.dat <= fmc_adc_100m_csr_i.dat;
rd_ack_int <= fmc_adc_100m_csr_rack;
when "1010" =>
case wb_i.adr(8 downto 8) is
when "0" =>
-- Submap fmc_i2c_master
fmc_i2c_master_re <= rd_int;
wb_o.dat <= fmc_i2c_master_i.dat;
rd_ack_int <= fmc_i2c_master_rack;
when "1" =>
-- Submap fmc_adc_eic
fmc_adc_eic_re <= rd_int;
wb_o.dat <= fmc_adc_eic_i.dat;
rd_ack_int <= fmc_adc_eic_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "1011" =>
case wb_i.adr(8 downto 8) is
when "0" =>
-- Submap si570_i2c_master
si570_i2c_master_re <= rd_int;
wb_o.dat <= si570_i2c_master_i.dat;
rd_ack_int <= si570_i2c_master_rack;
when "1" =>
-- Submap ds18b20_onewire_master
ds18b20_onewire_master_re <= rd_int;
wb_o.dat <= ds18b20_onewire_master_i.dat;
rd_ack_int <= ds18b20_onewire_master_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when "1100" =>
case wb_i.adr(8 downto 7) is
when "00" =>
-- Submap fmc_spi_master
fmc_spi_master_re <= rd_int;
wb_o.dat <= fmc_spi_master_i.dat;
rd_ack_int <= fmc_spi_master_rack;
when "10" =>
-- Submap timetag_core
timetag_core_re <= rd_int;
wb_o.dat <= timetag_core_i.dat;
rd_ack_int <= timetag_core_rack;
when others =>
rd_ack_int <= rd_int;
end case;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.cheby 0 → 100644
View file @ 920b7a16
memory-map:
name: spec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x6000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
address: 0x2000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
description: a ROM containing the application metadata
- submap:
name: fmc_adc_mezzanine
address: 0x4000
description: FMC ADC Mezzanine
filename: fmc_adc_mezzanine_mmap.cheby
hdl/top/spec_ref_design/spec_carrier_csr.vhd → hdl/cheby/spec_ref_fmc_adc_100Ms_mmap.vhd
View file @ 920b7a16
-- Do not edit; this file was generated by Cheby using these options:
-- -i spec_carrier_csr.cheby --gen-hdl=spec_carrier_csr.vhd
-- -i spec_ref_fmc_adc_100Ms_mmap.cheby --gen-hdl=spec_ref_fmc_adc_100Ms_mmap.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package spec_carrier_csr_pkg is
type t_carrier_csr_master_out is record
ctrl_led_green : std_logic;
ctrl_led_red : std_logic;
rst_fmc0 : std_logic;
end record t_carrier_csr_master_out;
subtype t_carrier_csr_slave_in is t_carrier_csr_master_out;
type t_carrier_csr_slave_out is record
carrier_pcb_rev : std_logic_vector(3 downto 0);
carrier_reserved : std_logic_vector(11 downto 0);
carrier_type : std_logic_vector(15 downto 0);
stat_fmc_pres : std_logic;
stat_p2l_pll_lck : std_logic;
stat_sys_pll_lck : std_logic;
stat_ddr3_cal_done : std_logic;
end record t_carrier_csr_slave_out;
subtype t_carrier_csr_master_in is t_carrier_csr_slave_out;
end spec_carrier_csr_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.spec_carrier_csr_pkg.all;
entity spec_carrier_csr is
entity spec_ref_fmc_adc_100m_mmap is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- Wires and registers
carrier_csr_i : in t_carrier_csr_master_in;
carrier_csr_o : out t_carrier_csr_master_out
-- a ROM containing the application metadata
metadata_i : in t_wishbone_master_in;
metadata_o : out t_wishbone_master_out;
-- FMC ADC Mezzanine
fmc_adc_mezzanine_i : in t_wishbone_master_in;
fmc_adc_mezzanine_o : out t_wishbone_master_out
);
end spec_carrier_csr;
end spec_ref_fmc_adc_100m_mmap;
architecture syn of spec_carrier_csr is
architecture syn of spec_ref_fmc_adc_100m_mmap is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
......@@ -54,9 +32,18 @@ architecture syn of spec_carrier_csr is
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal ctrl_led_green_reg : std_logic;
signal ctrl_led_red_reg : std_logic;
signal rst_fmc0_reg : std_logic;
signal metadata_re : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal fmc_adc_mezzanine_re : std_logic;
signal fmc_adc_mezzanine_wt : std_logic;
signal fmc_adc_mezzanine_rt : std_logic;
signal fmc_adc_mezzanine_tr : std_logic;
signal fmc_adc_mezzanine_wack : std_logic;
signal fmc_adc_mezzanine_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
......@@ -93,38 +80,67 @@ begin
wb_o.err <= '0';
-- Assign outputs
carrier_csr_o.ctrl_led_green <= ctrl_led_green_reg;
carrier_csr_o.ctrl_led_red <= ctrl_led_red_reg;
carrier_csr_o.rst_fmc0 <= rst_fmc0_reg;
-- Assignments for submap metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & wb_i.adr(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= (others => '1');
metadata_o.we <= metadata_wt;
metadata_o.dat <= wb_i.dat;
-- Assignments for submap fmc_adc_mezzanine
fmc_adc_mezzanine_tr <= fmc_adc_mezzanine_wt or fmc_adc_mezzanine_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_adc_mezzanine_rt <= '0';
else
fmc_adc_mezzanine_rt <= (fmc_adc_mezzanine_rt or fmc_adc_mezzanine_re) and not fmc_adc_mezzanine_rack;
end if;
end if;
end process;
fmc_adc_mezzanine_o.cyc <= fmc_adc_mezzanine_tr;
fmc_adc_mezzanine_o.stb <= fmc_adc_mezzanine_tr;
fmc_adc_mezzanine_wack <= fmc_adc_mezzanine_i.ack and fmc_adc_mezzanine_wt;
fmc_adc_mezzanine_rack <= fmc_adc_mezzanine_i.ack and fmc_adc_mezzanine_rt;
fmc_adc_mezzanine_o.adr <= ((18 downto 0 => '0') & wb_i.adr(12 downto 2)) & (1 downto 0 => '0');
fmc_adc_mezzanine_o.sel <= (others => '1');
fmc_adc_mezzanine_o.we <= fmc_adc_mezzanine_wt;
fmc_adc_mezzanine_o.dat <= wb_i.dat;
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
ctrl_led_green_reg <= '0';
ctrl_led_red_reg <= '0';
rst_fmc0_reg <= '0';
metadata_wt <= '0';
fmc_adc_mezzanine_wt <= '0';
else
wr_ack_int <= '0';
case wb_i.adr(3 downto 2) is
when "00" =>
-- Register carrier
metadata_wt <= '0';
fmc_adc_mezzanine_wt <= '0';
case wb_i.adr(14 downto 13) is
when "01" =>
-- Register stat
-- Submap metadata
metadata_wt <= (metadata_wt or wr_int) and not metadata_wack;
wr_ack_int <= metadata_wack;
when "10" =>
-- Register ctrl
if wr_int = '1' then
ctrl_led_green_reg <= wb_i.dat(0);
ctrl_led_red_reg <= wb_i.dat(1);
end if;
wr_ack_int <= wr_int;
when "11" =>
-- Register rst
if wr_int = '1' then
rst_fmc0_reg <= wb_i.dat(0);
end if;
wr_ack_int <= wr_int;
-- Submap fmc_adc_mezzanine
fmc_adc_mezzanine_wt <= (fmc_adc_mezzanine_wt or wr_int) and not fmc_adc_mezzanine_wack;
wr_ack_int <= fmc_adc_mezzanine_wack;
when others =>
wr_ack_int <= wr_int;
end case;
......@@ -139,28 +155,9 @@ begin
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- carrier
reg_rdat_int(3 downto 0) <= carrier_csr_i.carrier_pcb_rev;
reg_rdat_int(15 downto 4) <= carrier_csr_i.carrier_reserved;
reg_rdat_int(31 downto 16) <= carrier_csr_i.carrier_type;
rd_ack1_int <= rd_int;
case wb_i.adr(14 downto 13) is
when "01" =>
-- stat
reg_rdat_int(0) <= carrier_csr_i.stat_fmc_pres;
reg_rdat_int(1) <= carrier_csr_i.stat_p2l_pll_lck;
reg_rdat_int(2) <= carrier_csr_i.stat_sys_pll_lck;
reg_rdat_int(3) <= carrier_csr_i.stat_ddr3_cal_done;
rd_ack1_int <= rd_int;
when "10" =>
-- ctrl
reg_rdat_int(0) <= ctrl_led_green_reg;
reg_rdat_int(1) <= ctrl_led_red_reg;
rd_ack1_int <= rd_int;
when "11" =>
-- rst
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
......@@ -170,26 +167,22 @@ begin
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_i.dat, metadata_rack, metadata_rt, rd_int, fmc_adc_mezzanine_i.dat, fmc_adc_mezzanine_rack, fmc_adc_mezzanine_rt) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- carrier
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
metadata_re <= '0';
fmc_adc_mezzanine_re <= '0';
case wb_i.adr(14 downto 13) is
when "01" =>
-- stat
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
-- Submap metadata
metadata_re <= rd_int;
wb_o.dat <= metadata_i.dat;
rd_ack_int <= metadata_rack;
when "10" =>
-- ctrl
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- rst
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
-- Submap fmc_adc_mezzanine
fmc_adc_mezzanine_re <= rd_int;
wb_o.dat <= fmc_adc_mezzanine_i.dat;
rd_ack_int <= fmc_adc_mezzanine_rack;
when others =>
rd_ack_int <= rd_int;
end case;
......
hdl/rtl/timetag_core_regs.cheby → hdl/cheby/timetag_core_regs.cheby
View file @ 920b7a16
......@@ -2,6 +2,7 @@ memory-map:
bus: wb-32-be
name: timetag_core_regs
description: Time-tagging core registers
size: 0x80
comment: |
Wishbone slave for registers related to time-tagging core
x-hdl:
......
hdl/rtl/Manifest.py
View file @ 920b7a16
......@@ -3,11 +3,12 @@ files = [
"fmc_adc_mezzanine_pkg.vhd",
"fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"fmc_adc_aux_trigin.vhd",
"fmc_adc_aux_trigout.vhd",
"fmc_adc_eic.vhd",
"offset_gain_s.vhd",
"timetag_core_regs.vhd",
"timetag_core.vhd",
"../cheby/fmc_adc_mezzanine_mmap.vhd",
"../cheby/fmc_adc_100Ms_csr.vhd",
"../cheby/fmc_adc_aux_trigin.vhd",
"../cheby/fmc_adc_aux_trigout.vhd",
"../cheby/timetag_core_regs.vhd",
]
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 920b7a16
......@@ -130,18 +130,12 @@ end fmc_adc_mezzanine;
architecture rtl of fmc_adc_mezzanine is
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
-- Constants declaration
------------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 7;
-- Wishbone master(s)
constant c_WB_MASTER : integer := 0;
-- Wishbone slave(s)
constant c_WB_SLAVE_FMC_ADC : integer := 0; -- Mezzanine ADC core
constant c_WB_SLAVE_FMC_SYS_I2C : integer := 1; -- Mezzanine system I2C interface (EEPROM)
......@@ -151,78 +145,13 @@ architecture rtl of fmc_adc_mezzanine is
constant c_WB_SLAVE_FMC_SPI : integer := 5; -- Mezzanine SPI interface
constant c_WB_SLAVE_TIMETAG : integer := 6; -- Mezzanine timetag core
-- Devices sdb description
constant c_wb_adc_csr_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000001FF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000608",
version => x"00000002",
date => x"20190730",
name => "WB-FMC-ADC-Core ")));
constant c_wb_timetag_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000007F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000604",
version => x"00000001",
date => x"20121116",
name => "WB-Timetag-Core ")));
constant c_wb_fmc_adc_eic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"26ec6086", -- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-FMC-ADC.EIC ")));
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) :=
(
c_WB_SLAVE_FMC_ADC => f_sdb_embed_device(c_wb_adc_csr_sdb, x"00001000"),
c_WB_SLAVE_FMC_SYS_I2C => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001400"),
c_WB_SLAVE_FMC_EIC => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00001500"),
c_WB_SLAVE_FMC_I2C => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001600"),
c_WB_SLAVE_FMC_ONEWIRE => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001700"),
c_WB_SLAVE_FMC_SPI => f_sdb_embed_device(c_xwb_spi_sdb, x"00001800"),
c_WB_SLAVE_TIMETAG => f_sdb_embed_device(c_wb_timetag_sdb, x"00001900")
);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_out : t_wishbone_master_out;
signal cnx_master_in : t_wishbone_master_in;
-- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
......@@ -300,26 +229,29 @@ begin
clk_i => sys_clk_i,
slave_i => wb_csr_out,
slave_o => wb_csr_in,
master_i => cnx_master_in(c_WB_MASTER),
master_o => cnx_master_out(c_WB_MASTER));
master_i => cnx_master_in,
master_o => cnx_master_out);
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map (
g_VERBOSE => FALSE,
g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => TRUE,
g_wraparound => TRUE,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_wb_mode => PIPELINED,
g_sdb_addr => c_SDB_ADDRESS)
cmp_crossbar : entity work.fmc_adc_mezzanine_mmap
port map (
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_n_i,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
wb_i => cnx_master_out,
wb_o => cnx_master_in,
fmc_adc_100m_csr_i => cnx_slave_out(c_WB_SLAVE_FMC_ADC),
fmc_adc_100m_csr_o => cnx_slave_in(c_WB_SLAVE_FMC_ADC),
fmc_i2c_master_i => cnx_slave_out(c_WB_SLAVE_FMC_SYS_I2C),
fmc_i2c_master_o => cnx_slave_in(c_WB_SLAVE_FMC_SYS_I2C),
fmc_adc_eic_i => cnx_slave_out(c_WB_SLAVE_FMC_EIC),
fmc_adc_eic_o => cnx_slave_in(c_WB_SLAVE_FMC_EIC),
si570_i2c_master_i => cnx_slave_out(c_WB_SLAVE_FMC_I2C),
si570_i2c_master_o => cnx_slave_in(c_WB_SLAVE_FMC_I2C),
ds18b20_onewire_master_i => cnx_slave_out(c_WB_SLAVE_FMC_ONEWIRE),
ds18b20_onewire_master_o => cnx_slave_in(c_WB_SLAVE_FMC_ONEWIRE),
fmc_spi_master_i => cnx_slave_out(c_WB_SLAVE_FMC_SPI),
fmc_spi_master_o => cnx_slave_in(c_WB_SLAVE_FMC_SPI),
timetag_core_i => cnx_slave_out(c_WB_SLAVE_TIMETAG),
timetag_core_o => cnx_slave_in(c_WB_SLAVE_TIMETAG));
------------------------------------------------------------------------------
-- Mezzanine system managment I2C master
......
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ 920b7a16
`define FMC_ADC_100MS_CSR_SIZE 344
`define FMC_ADC_100MS_CSR_SIZE 512
`define ADDR_FMC_ADC_100MS_CSR_CTL 'h0
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD_OFFSET 0
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD 'h3
......
hdl/testbench/include/fmc_adc_mezzanine_mmap.v 0 → 100644
View file @ 920b7a16
`define FMC_ADC_MEZZANINE_MMAP_SIZE 8192
`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 'h1000
`define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_I2C_MASTER 'h1400
`define FMC_ADC_MEZZANINE_MMAP_FMC_I2C_MASTER_SIZE 256
`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 'h1500
`define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16
`define ADDR_FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 'h1600
`define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER_SIZE 256
`define ADDR_FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 'h1700
`define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 256
`define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 'h1800
`define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER_SIZE 32
`define ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 'h1900
`define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE_SIZE 128
hdl/testbench/include/spec_ref_fmc_adc_100Ms_mmap.v 0 → 100644
View file @ 920b7a16
`define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 24576
`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_METADATA 'h2000
`define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE 'h4000
`define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE_SIZE 8192
hdl/testbench/include/timetag_core_regs.v
View file @ 920b7a16
`define TIMETAG_CORE_REGS_SIZE 72
`define TIMETAG_CORE_REGS_SIZE 128
`define ADDR_TIMETAG_CORE_REGS_SECONDS_UPPER 'h0
`define TIMETAG_CORE_REGS_SECONDS_UPPER_OFFSET 0
`define TIMETAG_CORE_REGS_SECONDS_UPPER 'hff
......
hdl/top/spec_ref_design/Makefile deleted 100644 → 0
View file @ 8008de69
SIM =../../testbench/include
DOC =../../../doc/manual
SW =../../../software/include/hw
SOURCES = $(wildcard *.cheby)
TARGETS = $(SOURCES:.cheby=.vhd)
all: $(TARGETS)
.PHONY: $(TARGETS)
$(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< \
--gen-doc=$(DOC)/$(@:.vhd=.html) \
--gen-consts=$(SIM)/$(@:.vhd=.v) \
--gen-c=$(SW)/$(@:.vhd=.h)
hdl/top/spec_ref_design/Manifest.py
View file @ 920b7a16
files = [
"spec_ref_fmc_adc_100Ms.vhd",
"spec_carrier_csr.vhd",
"dma_eic.vhd",
"../../cheby/spec_ref_fmc_adc_100Ms_mmap.vhd",
]
fetchto = "../../ip_cores"
......
hdl/top/spec_ref_design/dma_eic.vhd deleted 100644 → 0
View file @ 8008de69
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for GN4124 DMA enhanced interrupt controller
---------------------------------------------------------------------------------------
-- File : ../rtl/dma_eic.vhd
-- Author : auto-generated by wbgen2 from dma_eic.wb
-- Created : Thu Jun 16 16:45:19 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity dma_eic is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_dma_done_i : in std_logic;
irq_dma_error_i : in std_logic
);
end dma_eic;
architecture syn of dma_eic is
signal eic_idr_int : std_logic_vector(1 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(1 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(1 downto 0);
signal eic_isr_clear_int : std_logic_vector(1 downto 0);
signal eic_isr_status_int : std_logic_vector(1 downto 0);
signal eic_irq_ack_int : std_logic_vector(1 downto 0);
signal eic_isr_write_int : std_logic ;
signal irq_inputs_vector_int : std_logic_vector(1 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= eic_imr_int(1 downto 0);
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(1 downto 0) <= eic_isr_status_int(1 downto 0);
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(1 downto 0) <= wrdata_reg(1 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(1 downto 0) <= wrdata_reg(1 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(1 downto 0) <= wrdata_reg(1 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 2,
g_irq00_mode => 0,
g_irq01_mode => 0,
g_irq02_mode => 0,
g_irq03_mode => 0,
g_irq04_mode => 0,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_dma_done_i;
irq_inputs_vector_int(1) <= irq_dma_error_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/top/spec_ref_design/spec_carrier_csr.cheby deleted 100644 → 0
View file @ 8008de69
memory-map:
bus: wb-32-be
name: spec_carrier_csr
description: Carrier control and status registers
comment: |
Wishbone slave for control and status registers related to the FMC carrier
x-hdl:
busgroup: True
iogroup: carrier_csr
children:
- reg:
name: carrier
address: 0x00000000
width: 32
access: ro
description: Carrier type and PCB version
children:
- field:
name: pcb_rev
range: 3-0
description: PCB revision
comment: |
Binary coded PCB layout revision.
- field:
name: reserved
range: 15-4
description: Reserved register
comment: |
Ignore on read, write with 0's.
- field:
name: type
range: 31-16
description: Carrier type
comment: |
Carrier type identifier
1 = SPEC
2 = SVEC
3 = VFC
4 = SPEXI
- reg:
name: stat
address: 0x00000004
width: 32
access: ro
description: Status
children:
- field:
name: fmc_pres
range: 0
description: FMC presence
comment: |
0: FMC slot is populated
1: FMC slot is not populated.
- field:
name: p2l_pll_lck
range: 1
description: GN4142 core P2L PLL status
comment: |
0: not locked
1: locked.
- field:
name: sys_pll_lck
range: 2
description: System clock PLL status
comment: |
0: not locked
1: locked.
- field:
name: ddr3_cal_done
range: 3
description: DDR3 calibration status
comment: |
0: not done
1: done.
- reg:
name: ctrl
address: 0x00000008
width: 32
access: rw
description: Control
children:
- field:
name: led_green
range: 0
description: Green LED
comment: |
Manual control of the front panel green LED (unused in the fmc-adc application)
- field:
name: led_red
range: 1
description: Red LED
comment: |
Manual control of the front panel red LED (unused in the fmc-adc application)
- reg:
name: rst
address: 0x0000000c
width: 32
access: wo
description: Reset Register
comment: |
Controls software reset of the mezzanine including the ddr interface and the time-tagging core.
children:
- field:
name: fmc0
range: 0
description: State of the reset line
comment: |
write 0: Normal FMC operation
write 1: FMC is held in reset
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @ 920b7a16
......@@ -38,7 +38,6 @@ library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_mezzanine_pkg.all;
use work.spec_carrier_csr_pkg.all;
use work.wr_board_pkg.all;
entity spec_ref_fmc_adc_100Ms is
......@@ -206,18 +205,12 @@ end spec_ref_fmc_adc_100Ms;
architecture arch of spec_ref_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
-- Constants declaration
------------------------------------------------------------------------------
-- Number of masters on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 2;
-- Wishbone master(s)
constant c_WB_MASTER_GENNUM : integer := 0;
-- Wishbone slave(s)
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FMC_ADC : integer := 1; -- FMC ADC mezzanine
......@@ -225,17 +218,6 @@ architecture arch of spec_ref_fmc_adc_100Ms is
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT_ADDR :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => c_METADATA_ADDR,
c_WB_SLAVE_FMC_ADC => x"0000_4000");
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes
c_WB_SLAVE_FMC_ADC => x"0003_e000"); -- 0x2000 bytes
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
......@@ -248,8 +230,8 @@ architecture arch of spec_ref_fmc_adc_100Ms is
signal rst_ref_125m_n : std_logic := '0';
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_out : t_wishbone_master_out;
signal cnx_master_in : t_wishbone_master_in;
-- Wishbone buse(s) from crossbar master port(s) to slave(s)
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
......@@ -279,25 +261,8 @@ architecture arch of spec_ref_fmc_adc_100Ms is
signal wrabbit_en : std_logic;
signal pps_led : std_logic;
-- IO for CSR registers
signal csr_regin : t_carrier_csr_master_in;
signal csr_regout : t_carrier_csr_master_out;
begin -- architecture arch
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"4144_4301", -- "ADC1"
g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
inst_spec_base : entity work.spec_base_wr
generic map (
g_WITH_VIC => TRUE,
......@@ -411,8 +376,8 @@ begin -- architecture arch
pps_p_o => open,
pps_led_o => pps_led,
link_ok_o => wrabbit_en,
app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM),
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM));
app_wb_o => cnx_master_out,
app_wb_i => cnx_master_in);
fmc_wb_ddr_in.err <= '0';
fmc_wb_ddr_in.rty <= '0';
......@@ -421,21 +386,33 @@ begin -- architecture arch
-- Primary wishbone crossbar
------------------------------------------------------------------------------
cmp_crossbar : xwb_crossbar
cmp_crossbar : entity work.spec_ref_fmc_adc_100m_mmap
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_i => cnx_master_out,
wb_o => cnx_master_in,
metadata_i => cnx_slave_out(c_WB_SLAVE_METADATA),
metadata_o => cnx_slave_in(c_WB_SLAVE_METADATA),
fmc_adc_mezzanine_i => cnx_slave_out(c_WB_SLAVE_FMC_ADC),
fmc_adc_mezzanine_o => cnx_slave_in(c_WB_SLAVE_FMC_ADC));
------------------------------------------------------------------------------
-- Application-specific metadata ROM
------------------------------------------------------------------------------
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_VERBOSE => FALSE,
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_ADDRESS => c_WB_LAYOUT_ADDR,
g_MASK => c_WB_LAYOUT_MASK)
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"4144_4301", -- "ADC1"
g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
------------------------------------------------------------------------------
-- FMC ADC mezzanines (wb bridge with cross-clocking)
......@@ -548,7 +525,7 @@ begin -- architecture arch
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_GENNUM).cyc,
pulse_i => cnx_master_out.cyc,
extended_o => gn4124_access);
aux_leds_o(0) <= not gn4124_access;
......
hdl/top/spec_ref_design/wb_gen/Makefile deleted 100644 → 0
View file @ 8008de69
WBGEN2=$(shell which wbgen2)
RTL=../
TEX=../../../../doc/manual/spec/
all: dma_eic
dma_eic:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
hdl/top/spec_ref_design/wb_gen/dma_eic.h deleted 100644 → 0
View file @ 8008de69
/*
Register definitions for slave core: GN4124 DMA enhanced interrupt controller
* File : dma_eic.h
* Author : auto-generated by wbgen2 from dma_eic.wb
* Created : Thu Jun 16 16:45:19 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_DMA_EIC_WB
#define __WBGEN2_REGDEFS_DMA_EIC_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: DMA done interrupt in reg: Interrupt disable register */
#define DMA_EIC_EIC_IDR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt disable register */
#define DMA_EIC_EIC_IDR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: DMA done interrupt in reg: Interrupt enable register */
#define DMA_EIC_EIC_IER_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt enable register */
#define DMA_EIC_EIC_IER_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: DMA done interrupt in reg: Interrupt mask register */
#define DMA_EIC_EIC_IMR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt mask register */
#define DMA_EIC_EIC_IMR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: DMA done interrupt in reg: Interrupt status register */
#define DMA_EIC_EIC_ISR_DMA_DONE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA error interrupt in reg: Interrupt status register */
#define DMA_EIC_EIC_ISR_DMA_ERROR WBGEN2_GEN_MASK(1, 1)
PACKED struct DMA_EIC_WB {
/* [0x0]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x4]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x8]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0xc]: REG Interrupt status register */
uint32_t EIC_ISR;
};
#endif
hdl/top/spec_ref_design/wb_gen/dma_eic.htm deleted 100644 → 0
View file @ 8008de69
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<HEAD>
<TITLE>dma_eic</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
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font-family: Arial,Helvetica; font-size:12; }
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.td_pblock_left { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: left; }
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-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">dma_eic</h1>
<h3>GN4124 DMA enhanced interrupt controller</h3>
<p>Enhanced interrrupt controller for GN4124 DMA.</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Interrupt disable register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Interrupt enable register</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Interrupt mask register</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Interrupt status register</a></span><br/>
<span style="margin-left: 0px; ">5. <A href="#sect_5_0">Interrupts</a></span><br/>
<span style="margin-left: 20px; ">5.1. <A href="#sect_5_1">DMA done interrupt</a></span><br/>
<span style="margin-left: 20px; ">5.2. <A href="#sect_5_2">DMA error interrupt</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#EIC_IDR">Interrupt disable register</a>
</td>
<td class="td_code">
dma_eic_eic_idr
</td>
<td class="td_code">
EIC_IDR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#EIC_IER">Interrupt enable register</a>
</td>
<td class="td_code">
dma_eic_eic_ier
</td>
<td class="td_code">
EIC_IER
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#EIC_IMR">Interrupt mask register</a>
</td>
<td class="td_code">
dma_eic_eic_imr
</td>
<td class="td_code">
EIC_IMR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#EIC_ISR">Interrupt status register</a>
</td>
<td class="td_code">
dma_eic_eic_isr
</td>
<td class="td_code">
EIC_ISR
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>DMA done interrupt:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_dma_done_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[1:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>DMA error interrupt:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_dma_error_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_int_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="EIC_IDR"></a>
<h3><a name="sect_3_1">3.1. Interrupt disable register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_eic_eic_idr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_IDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_ERROR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_DONE
</td>
</tr>
</table>
<ul>
<li><b>
DMA_DONE
</b>[<i>write-only</i>]: DMA done interrupt
<br>write 1: disable interrupt 'DMA done interrupt'<br>write 0: no effect
<li><b>
DMA_ERROR
</b>[<i>write-only</i>]: DMA error interrupt
<br>write 1: disable interrupt 'DMA error interrupt'<br>write 0: no effect
</ul>
<a name="EIC_IER"></a>
<h3><a name="sect_3_2">3.2. Interrupt enable register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_eic_eic_ier
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_IER
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_ERROR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_DONE
</td>
</tr>
</table>
<ul>
<li><b>
DMA_DONE
</b>[<i>write-only</i>]: DMA done interrupt
<br>write 1: enable interrupt 'DMA done interrupt'<br>write 0: no effect
<li><b>
DMA_ERROR
</b>[<i>write-only</i>]: DMA error interrupt
<br>write 1: enable interrupt 'DMA error interrupt'<br>write 0: no effect
</ul>
<a name="EIC_IMR"></a>
<h3><a name="sect_3_3">3.3. Interrupt mask register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_eic_eic_imr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_IMR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<p>
Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_ERROR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_DONE
</td>
</tr>
</table>
<ul>
<li><b>
DMA_DONE
</b>[<i>read-only</i>]: DMA done interrupt
<br>read 1: interrupt 'DMA done interrupt' is enabled<br>read 0: interrupt 'DMA done interrupt' is disabled
<li><b>
DMA_ERROR
</b>[<i>read-only</i>]: DMA error interrupt
<br>read 1: interrupt 'DMA error interrupt' is enabled<br>read 0: interrupt 'DMA error interrupt' is disabled
</ul>
<a name="EIC_ISR"></a>
<h3><a name="sect_3_4">3.4. Interrupt status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_eic_eic_isr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EIC_ISR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<p>
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_ERROR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DMA_DONE
</td>
</tr>
</table>
<ul>
<li><b>
DMA_DONE
</b>[<i>read/write</i>]: DMA done interrupt
<br>read 1: interrupt 'DMA done interrupt' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'DMA done interrupt'<br>write 0: no effect
<li><b>
DMA_ERROR
</b>[<i>read/write</i>]: DMA error interrupt
<br>read 1: interrupt 'DMA error interrupt' is pending<br>read 0: interrupt not pending<br>write 1: clear interrupt 'DMA error interrupt'<br>write 0: no effect
</ul>
<h3><a name="sect_5_0">5. Interrupts</a></h3>
<a name="DMA_DONE"></a>
<h3><a name="sect_5_1">5.1. DMA done interrupt</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td >
dma_eic_dma_done
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td >
DMA_DONE
</td>
</tr>
<tr>
<td >
<b>Trigger: </b>
</td>
<td >
rising edge
</td>
</tr>
</table>
<p>DMA done interrupt line (rising edge sensitive).</p>
<a name="DMA_ERROR"></a>
<h3><a name="sect_5_2">5.2. DMA error interrupt</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td >
dma_eic_dma_error
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td >
DMA_ERROR
</td>
</tr>
<tr>
<td >
<b>Trigger: </b>
</td>
<td >
rising edge
</td>
</tr>
</table>
<p>DMA error interrupt line (rising edge sensitive).</p>
</BODY>
</HTML>
hdl/top/spec_ref_design/wb_gen/dma_eic.wb deleted 100644 → 0
View file @ 8008de69
peripheral {
name = "GN4124 DMA enhanced interrupt controller";
description = "Enhanced interrrupt controller for GN4124 DMA.";
hdl_entity = "dma_eic";
prefix = "dma_eic";
irq {
name = "DMA done interrupt";
description = "DMA done interrupt line (rising edge sensitive).";
prefix = "dma_done";
trigger = EDGE_RISING;
};
irq {
name = "DMA error interrupt";
description = "DMA error interrupt line (rising edge sensitive).";
prefix = "dma_error";
trigger = EDGE_RISING;
};
};
software/include/hw/fmc_adc_100Ms_csr.h
View file @ 920b7a16
#ifndef __CHEBY__FMC_ADC_100MS_CSR__H__
#define __CHEBY__FMC_ADC_100MS_CSR__H__
#define FMC_ADC_100MS_CSR_SIZE 512
/* Control register */
#define FMC_ADC_100MS_CSR_CTL 0x0UL
......@@ -215,132 +216,135 @@
struct fmc_adc_100ms_csr {
/* [0x0]: REG (rw) Control register */
uint32_t ctl;
/* [0x4]: REG (ro) Status register */
uint32_t sta;
/* [0x8]: REG (ro) Trigger status */
uint32_t trig_stat;
/* [0xc]: REG (rw) Trigger enable */
uint32_t trig_en;
/* [0x10]: REG (rw) Trigger polarity */
uint32_t trig_pol;
/* [0x14]: REG (rw) External trigger delay */
uint32_t ext_trig_dly;
/* [0x18]: REG (wo) Software trigger */
uint32_t sw_trig;
/* [0x1c]: REG (rw) Number of shots */
uint32_t shots;
/* [0x20]: REG (ro) Multi-shot sample depth register */
uint32_t multi_depth;
/* [0x24]: REG (ro) Trigger address register */
uint32_t trig_pos;
/* [0x28]: REG (ro) Sampling clock frequency */
uint32_t fs_freq;
/* [0x2c]: REG (rw) Downsampling ratio */
uint32_t downsample;
/* [0x30]: REG (rw) Pre-trigger samples */
uint32_t pre_samples;
/* [0x34]: REG (rw) Post-trigger samples */
uint32_t post_samples;
/* [0x38]: REG (ro) Samples counter */
uint32_t samples_cnt;
/* padding to: 32 words */
uint32_t __padding_0[17];
/* [0x80]: REG (rw) Channel 1 control register */
uint32_t ch1_ctl;
/* [0x84]: REG (ro) Channel 1 status register */
uint32_t ch1_sta;
/* [0x88]: REG (rw) Channel 1 calibration register */
uint32_t ch1_calib;
/* [0x8c]: REG (rw) Channel 1 saturation register */
uint32_t ch1_sat;
/* [0x90]: REG (rw) Channel 1 trigger threshold configuration register */
uint32_t ch1_trig_thres;
/* [0x94]: REG (rw) Channel 1 trigger delay */
uint32_t ch1_trig_dly;
/* padding to: 48 words */
uint32_t __padding_1[10];
/* [0xc0]: REG (rw) Channel 2 control register */
uint32_t ch2_ctl;
/* [0xc4]: REG (ro) Channel 2 status register */
uint32_t ch2_sta;
/* [0xc8]: REG (rw) Channel 2 calibration register */
uint32_t ch2_calib;
/* [0xcc]: REG (rw) Channel 2 saturation register */
uint32_t ch2_sat;
/* [0xd0]: REG (rw) Channel 2 trigger threshold configuration register */
uint32_t ch2_trig_thres;
/* [0xd4]: REG (rw) Channel 2 trigger delay */
uint32_t ch2_trig_dly;
/* padding to: 64 words */
uint32_t __padding_2[10];
/* [0x100]: REG (rw) Channel 3 control register */
uint32_t ch3_ctl;
/* [0x104]: REG (ro) Channel 3 status register */
uint32_t ch3_sta;
/* [0x108]: REG (rw) Channel 3 calibration register */
uint32_t ch3_calib;
/* [0x10c]: REG (rw) Channel 3 saturation register */
uint32_t ch3_sat;
/* [0x110]: REG (rw) Channel 3 trigger threshold configuration register */
uint32_t ch3_trig_thres;
/* [0x114]: REG (rw) Channel 3 trigger delay */
uint32_t ch3_trig_dly;
/* padding to: 80 words */
uint32_t __padding_3[10];
/* [0x140]: REG (rw) Channel 4 control register */
uint32_t ch4_ctl;
/* [0x144]: REG (ro) Channel 4 status register */
uint32_t ch4_sta;
/* [0x148]: REG (rw) Channel 4 gain calibration register */
uint32_t ch4_calib;
/* [0x14c]: REG (rw) Channel 4 saturation register */
uint32_t ch4_sat;
/* [0x150]: REG (rw) Channel 4 trigger threshold configuration register */
uint32_t ch4_trig_thres;
/* [0x154]: REG (rw) Channel 4 trigger delay */
uint32_t ch4_trig_dly;
/* padding to: 85 words */
uint32_t __padding_4[42];
};
#endif /* __CHEBY__FMC_ADC_100MS_CSR__H__ */
software/include/hw/fmc_adc_aux_trigin.h
View file @ 920b7a16
#ifndef __CHEBY__AUX_TRIGIN__H__
#define __CHEBY__AUX_TRIGIN__H__
#define AUX_TRIGIN_SIZE 20
/* Core version */
#define AUX_TRIGIN_VERSION 0x0UL
......@@ -18,13 +19,13 @@
struct aux_trigin {
/* [0x0]: REG (ro) Core version */
uint32_t version;
/* [0x4]: REG (rw) Control register */
uint32_t ctrl;
/* [0x8]: REG (rw) Time (seconds) to trigger */
uint64_t seconds;
/* [0x10]: REG (rw) Time (cycles) to trigger */
uint32_t cycles;
};
......
software/include/hw/fmc_adc_aux_trigout.h
View file @ 920b7a16
#ifndef __CHEBY__AUX_TRIGOUT__H__
#define __CHEBY__AUX_TRIGOUT__H__
#define AUX_TRIGOUT_SIZE 20
/* Status register */
#define AUX_TRIGOUT_STATUS 0x0UL
......@@ -26,13 +27,13 @@
struct aux_trigout {
/* [0x0]: REG (ro) Status register */
uint32_t status;
/* padding to: 2 words */
uint32_t __padding_0[1];
/* [0x8]: REG (ro) Time (seconds) of the last event */
uint64_t ts_mask_sec;
/* [0x10]: REG (ro) Cycles part of timestamp fifo. */
uint32_t ts_cycles;
};
......
software/include/hw/fmc_adc_mezzanine_mmap.h 0 → 100644
View file @ 920b7a16
#ifndef __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
#define __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
#include "timetag_core_regs.h"
#include "fmc_adc_100ms_csr.h"
#define FMC_ADC_MEZZANINE_MMAP_SIZE 8192
/* FMC ADC 100M CSR */
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR 0x1000UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR_SIZE 512
/* Mezzanine system management I2C master */
#define FMC_ADC_MEZZANINE_MMAP_FMC_I2C_MASTER 0x1400UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_I2C_MASTER_SIZE 256
/* FMC ADC Embedded Interrupt Controller */
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC 0x1500UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC_SIZE 16
/* Si570 control I2C master */
#define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 0x1600UL
#define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER_SIZE 256
/* DS18B20 OneWire master */
#define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 0x1700UL
#define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 256
/* Mezzanine SPI master (ADC control + DAC offsets) */
#define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 0x1800UL
#define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER_SIZE 32
/* Timetag Core */
#define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 0x1900UL
#define FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE_SIZE 128
struct fmc_adc_mezzanine_mmap {
/* padding to: 1024 words */
uint32_t __padding_0[1024];
/* [0x1000]: SUBMAP FMC ADC 100M CSR */
struct fmc_adc_100ms_csr fmc_adc_100m_csr;
/* padding to: 1280 words */
uint32_t __padding_1[128];
/* [0x1400]: SUBMAP Mezzanine system management I2C master */
uint32_t fmc_i2c_master[64];
/* [0x1500]: SUBMAP FMC ADC Embedded Interrupt Controller */
uint32_t fmc_adc_eic[4];
/* padding to: 1408 words */
uint32_t __padding_2[60];
/* [0x1600]: SUBMAP Si570 control I2C master */
uint32_t si570_i2c_master[64];
/* [0x1700]: SUBMAP DS18B20 OneWire master */
uint32_t ds18b20_onewire_master[64];
/* [0x1800]: SUBMAP Mezzanine SPI master (ADC control + DAC offsets) */
uint32_t fmc_spi_master[8];
/* padding to: 1600 words */
uint32_t __padding_3[56];
/* [0x1900]: SUBMAP Timetag Core */
struct timetag_core_regs timetag_core;
/* padding to: 1600 words */
uint32_t __padding_4[416];
};
#endif /* __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__ */
software/include/hw/spec_carrier_csr.h deleted 100644 → 0
View file @ 8008de69
#ifndef __CHEBY__SPEC_CARRIER_CSR__H__
#define __CHEBY__SPEC_CARRIER_CSR__H__
#define SPEC_CARRIER_CSR_SIZE 16
/* Carrier type and PCB version */
#define SPEC_CARRIER_CSR_CARRIER 0x0UL
#define SPEC_CARRIER_CSR_CARRIER_PCB_REV_MASK 0xfUL
#define SPEC_CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define SPEC_CARRIER_CSR_CARRIER_RESERVED_MASK 0xfff0UL
#define SPEC_CARRIER_CSR_CARRIER_RESERVED_SHIFT 4
#define SPEC_CARRIER_CSR_CARRIER_TYPE_MASK 0xffff0000UL
#define SPEC_CARRIER_CSR_CARRIER_TYPE_SHIFT 16
/* Status */
#define SPEC_CARRIER_CSR_STAT 0x4UL
#define SPEC_CARRIER_CSR_STAT_FMC_PRES 0x1UL
#define SPEC_CARRIER_CSR_STAT_P2L_PLL_LCK 0x2UL
#define SPEC_CARRIER_CSR_STAT_SYS_PLL_LCK 0x4UL
#define SPEC_CARRIER_CSR_STAT_DDR3_CAL_DONE 0x8UL
/* Control */
#define SPEC_CARRIER_CSR_CTRL 0x8UL
#define SPEC_CARRIER_CSR_CTRL_LED_GREEN 0x1UL
#define SPEC_CARRIER_CSR_CTRL_LED_RED 0x2UL
/* Reset Register */
#define SPEC_CARRIER_CSR_RST 0xcUL
#define SPEC_CARRIER_CSR_RST_FMC0 0x1UL
struct spec_carrier_csr {
/* [0x0]: REG (ro) Carrier type and PCB version */
uint32_t carrier;
/* [0x4]: REG (ro) Status */
uint32_t stat;
/* [0x8]: REG (rw) Control */
uint32_t ctrl;
/* [0xc]: REG (wo) Reset Register */
uint32_t rst;
};
#endif /* __CHEBY__SPEC_CARRIER_CSR__H__ */
software/include/hw/spec_ref_fmc_adc_100Ms_mmap.h 0 → 100644
View file @ 920b7a16
#ifndef __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#define __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__
#include "fmc_adc_mezzanine_mmap.h"
#define SPEC_REF_FMC_ADC_100M_MMAP_SIZE 24576
/* a ROM containing the application metadata */
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA 0x2000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
/* FMC ADC Mezzanine */
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE 0x4000UL
#define SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE_SIZE 8192
struct spec_ref_fmc_adc_100m_mmap {
/* padding to: 2048 words */
uint32_t __padding_0[2048];
/* [0x2000]: SUBMAP a ROM containing the application metadata */
uint32_t metadata[16];
/* padding to: 4096 words */
uint32_t __padding_1[2032];
/* [0x4000]: SUBMAP FMC ADC Mezzanine */
struct fmc_adc_mezzanine_mmap fmc_adc_mezzanine;
};
#endif /* __CHEBY__SPEC_REF_FMC_ADC_100M_MMAP__H__ */
software/include/hw/timetag_core_regs.h
View file @ 920b7a16
#ifndef __CHEBY__TIMETAG_CORE_REGS__H__
#define __CHEBY__TIMETAG_CORE_REGS__H__
#define TIMETAG_CORE_REGS_SIZE 128
/* Timetag seconds register (upper) */
#define TIMETAG_CORE_REGS_SECONDS_UPPER 0x0UL
......@@ -82,57 +83,60 @@
struct timetag_core_regs {
/* [0x0]: REG (rw) Timetag seconds register (upper) */
uint32_t seconds_upper;
/* [0x4]: REG (rw) Timetag seconds register (lower) */
uint32_t seconds_lower;
/* [0x8]: REG (rw) Timetag coarse time register, system clock ticks (125MHz) */
uint32_t coarse;
/* [0xc]: REG (rw) Time trigger seconds register (upper) */
uint32_t time_trig_seconds_upper;
/* [0x10]: REG (rw) Time trigger seconds register (lower) */
uint32_t time_trig_seconds_lower;
/* [0x14]: REG (rw) Time trigger coarse time register, system clock ticks (125MHz) */
uint32_t time_trig_coarse;
/* [0x18]: REG (ro) Trigger time-tag seconds register (upper) */
uint32_t trig_tag_seconds_upper;
/* [0x1c]: REG (ro) Trigger time-tag seconds register (lower) */
uint32_t trig_tag_seconds_lower;
/* [0x20]: REG (ro) Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t trig_tag_coarse;
/* [0x24]: REG (ro) Acquisition start time-tag seconds register (upper) */
uint32_t acq_start_tag_seconds_upper;
/* [0x28]: REG (ro) Acquisition start time-tag seconds register (lower) */
uint32_t acq_start_tag_seconds_lower;
/* [0x2c]: REG (ro) Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t acq_start_tag_coarse;
/* [0x30]: REG (ro) Acquisition stop time-tag seconds register (upper) */
uint32_t acq_stop_tag_seconds_upper;
/* [0x34]: REG (ro) Acquisition stop time-tag seconds register (lower) */
uint32_t acq_stop_tag_seconds_lower;
/* [0x38]: REG (ro) Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t acq_stop_tag_coarse;
/* [0x3c]: REG (ro) Acquisition end time-tag seconds register (upper) */
uint32_t acq_end_tag_seconds_upper;
/* [0x40]: REG (ro) Acquisition end time-tag seconds register (lower) */
uint32_t acq_end_tag_seconds_lower;
/* [0x44]: REG (ro) Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t acq_end_tag_coarse;
/* padding to: 17 words */
uint32_t __padding_0[14];
};
#endif /* __CHEBY__TIMETAG_CORE_REGS__H__ */
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