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FMC ADC 100M 14b 4cha - Gateware
Commit 9e14427f authored by Tim Mottram's avatar Tim Mottram Committed by Dimitris Lampridis
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hdl: Preliminary support for logical OR of internal threshold triggers 

Signed-off-by: 's avatarDimitris Lampridis <Dimitris.Lampridis@cern.ch>
parent b98da95d
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doc/manual/fmc_adc_100Ms_csr.tex
View file @ 9e14427f
......@@ -75,65 +75,81 @@ REG @tab
Channel 1 saturation register
@item @code{0x48} @tab
REG @tab
@code{ch1_trig} @tab
Channel 1 trigger configuration register
@item @code{0x4c} @tab
REG @tab
@code{ch2_ctl} @tab
Channel 2 control register
@item @code{0x4c} @tab
@item @code{0x50} @tab
REG @tab
@code{ch2_sta} @tab
Channel 2 status register
@item @code{0x50} @tab
@item @code{0x54} @tab
REG @tab
@code{ch2_gain} @tab
Channel 2 gain calibration register
@item @code{0x54} @tab
@item @code{0x58} @tab
REG @tab
@code{ch2_offset} @tab
Channel 2 offset calibration register
@item @code{0x58} @tab
@item @code{0x5c} @tab
REG @tab
@code{ch2_sat} @tab
Channel 2 saturation register
@item @code{0x5c} @tab
@item @code{0x60} @tab
REG @tab
@code{ch2_trig} @tab
Channel 2 trigger configuration register
@item @code{0x64} @tab
REG @tab
@code{ch3_ctl} @tab
Channel 3 control register
@item @code{0x60} @tab
@item @code{0x68} @tab
REG @tab
@code{ch3_sta} @tab
Channel 3 status register
@item @code{0x64} @tab
@item @code{0x6c} @tab
REG @tab
@code{ch3_gain} @tab
Channel 3 gain calibration register
@item @code{0x68} @tab
@item @code{0x70} @tab
REG @tab
@code{ch3_offset} @tab
Channel 3 offset calibration register
@item @code{0x6c} @tab
@item @code{0x74} @tab
REG @tab
@code{ch3_sat} @tab
Channel 3 saturation register
@item @code{0x70} @tab
@item @code{0x78} @tab
REG @tab
@code{ch3_trig} @tab
Channel 3 trigger configuration register
@item @code{0x7c} @tab
REG @tab
@code{ch4_ctl} @tab
Channel 4 control register
@item @code{0x74} @tab
@item @code{0x80} @tab
REG @tab
@code{ch4_sta} @tab
Channel 4 status register
@item @code{0x78} @tab
@item @code{0x84} @tab
REG @tab
@code{ch4_gain} @tab
Channel 4 gain calibration register
@item @code{0x7c} @tab
@item @code{0x88} @tab
REG @tab
@code{ch4_offset} @tab
Channel 4 offset calibration register
@item @code{0x80} @tab
@item @code{0x8c} @tab
REG @tab
@code{ch4_sat} @tab
Channel 4 saturation register
@item @code{0x84} @tab
@item @code{0x90} @tab
REG @tab
@code{ch4_trig} @tab
Channel 4 trigger configuration register
@item @code{0x94} @tab
REG @tab
@code{multi_depth} @tab
Multi-shot sample depth register
......@@ -225,9 +241,9 @@ Acquisition configuration status
Hardware trigger selection
@item @code{2}
@tab R/W @tab
@code{HW_TRIG_POL}
@code{EX_HW_TRIG_POL}
@tab @code{0} @tab
Hardware trigger polarity
External Hardware trigger polarity
@item @code{3}
@tab R/W @tab
@code{HW_TRIG_EN}
......@@ -238,37 +254,19 @@ Hardware trigger enable
@code{SW_TRIG_EN}
@tab @code{0} @tab
Software trigger enable
@item @code{6...5}
@tab R/W @tab
@code{INT_TRIG_SEL}
@tab @code{0} @tab
Channel selection for internal trigger
@item @code{7}
@item @code{5}
@tab R/W @tab
@code{INT_TRIG_TEST_EN}
@tab @code{0} @tab
Enable internal trigger test mode
@item @code{15...8}
@tab R/W @tab
@code{INT_TRIG_THRES_FILT}
@tab @code{0} @tab
Internal trigger threshold glitch filter
@item @code{31...16}
@tab R/W @tab
@code{INT_TRIG_THRES}
@tab @code{0} @tab
Threshold for internal trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{hw_trig_sel} @tab 00: internal (data threshold)@*01: external (front panel trigger input)@*10: trigger from timetag core@*11: reserved (for WR message-based trigger)
@item @code{hw_trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ex_hw_trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{hw_trig_en} @tab 0: disable@*1: enable
@item @code{sw_trig_en} @tab 0: disable@*1: enable
@item @code{int_trig_sel} @tab 00: channel 1@*01: channel 2@*10: channel 3@*11: channel 4
@item @code{int_trig_test_en} @tab Test mode:@* ch1 = Channel 1 input(analogue)@* ch2 = Channel input over threshold (digital)@* ch3 = Channel input over threshold filtered (digital)@* ch4 = Trigger (digital)
@item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@end multitable
@regsection @code{trig_dly} - Trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -462,6 +460,42 @@ Saturation value for channel 1
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch1_trig} - Channel 1 trigger configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG_EN}
@tab @code{0} @tab
Trigger enable for channel 1
@item @code{1}
@tab R/W @tab
@code{TRIG_POL}
@tab @code{0} @tab
Trigger polarity
@item @code{7...2}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@item @code{15...8}
@tab R/W @tab
@code{INT_TRIG_THRES_FILT}
@tab @code{0} @tab
Internal trigger threshold glitch filter for Channel 1
@item @code{31...16}
@tab R/W @tab
@code{INT_TRIG_THRES}
@tab @code{0} @tab
Threshold for Channel 1 internal trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@end multitable
@regsection @code{ch2_ctl} - Channel 2 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -527,6 +561,42 @@ Saturation value for channel 2
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch2_trig} - Channel 2 trigger configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG_EN}
@tab @code{0} @tab
Trigger enable for channel 2
@item @code{1}
@tab R/W @tab
@code{TRIG_POL}
@tab @code{0} @tab
Trigger polarity
@item @code{7...2}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@item @code{15...8}
@tab R/W @tab
@code{INT_TRIG_THRES_FILT}
@tab @code{0} @tab
Internal trigger threshold glitch filter for Channel 2
@item @code{31...16}
@tab R/W @tab
@code{INT_TRIG_THRES}
@tab @code{0} @tab
Threshold for Channel 2 internal trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@end multitable
@regsection @code{ch3_ctl} - Channel 3 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -592,6 +662,42 @@ Saturation value for channel 3
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch3_trig} - Channel 3 trigger configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG_EN}
@tab @code{0} @tab
Trigger enable for channel 3
@item @code{1}
@tab R/W @tab
@code{TRIG_POL}
@tab @code{0} @tab
Trigger polarity
@item @code{7...2}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@item @code{15...8}
@tab R/W @tab
@code{INT_TRIG_THRES_FILT}
@tab @code{0} @tab
Internal trigger threshold glitch filter for Channel 3
@item @code{31...16}
@tab R/W @tab
@code{INT_TRIG_THRES}
@tab @code{0} @tab
Threshold for Channel 3 internal trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@end multitable
@regsection @code{ch4_ctl} - Channel 4 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -657,6 +763,42 @@ Saturation value for channel 4
@headitem Field @tab Description
@item @code{val} @tab Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
@end multitable
@regsection @code{ch4_trig} - Channel 4 trigger configuration register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{TRIG_EN}
@tab @code{0} @tab
Trigger enable for channel 4
@item @code{1}
@tab R/W @tab
@code{TRIG_POL}
@tab @code{0} @tab
trigger polarity
@item @code{7...2}
@tab R/W @tab
@code{RESERVED}
@tab @code{0} @tab
Reserved
@item @code{15...8}
@tab R/W @tab
@code{INT_TRIG_THRES_FILT}
@tab @code{0} @tab
Internal trigger threshold glitch filter for Channel 4
@item @code{31...16}
@tab R/W @tab
@code{INT_TRIG_THRES}
@tab @code{0} @tab
Threshold for Channel 4 internal trigger
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{reserved} @tab Ignore on read, write with 0's
@item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
@item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
@end multitable
@regsection @code{multi_depth} - Multi-shot sample depth register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ 9e14427f
......@@ -9,7 +9,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-24
-- Last update: 2016-06-23
-- Last update: 2018-01-22
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: FMC ADC 100Ms/s core.
......@@ -195,6 +195,8 @@ architecture rtl of fmc_adc_100Ms_core is
------------------------------------------------------------------------------
type t_acq_fsm_state is (IDLE, PRE_TRIG, WAIT_TRIG, POST_TRIG, TRIG_TAG, DECR_SHOT);
type t_data_pipe is array (natural range<>) of std_logic_vector(63 downto 0);
type t_fmc_adc_vec8_array is array (positive range<>) of std_logic_vector(7 downto 0);
type t_fmc_adc_vec16_array is array (positive range<>) of std_logic_vector(15 downto 0);
------------------------------------------------------------------------------
-- Signals declaration
......@@ -236,20 +238,22 @@ architecture rtl of fmc_adc_100Ms_core is
signal ext_trig_p, ext_trig_n : std_logic;
signal time_trig : std_logic;
signal int_trig : std_logic;
signal int_trig_over_thres : std_logic;
signal int_trig_over_thres_d : std_logic;
signal int_trig_over_thres_filt : std_logic;
signal int_trig_over_thres_filt_d : std_logic;
signal int_trig_sel : std_logic_vector(1 downto 0);
signal int_trig_data : std_logic_vector(15 downto 0);
signal int_trig_thres : std_logic_vector(15 downto 0);
signal int_ch_trig : std_logic_vector(1 to 4);
signal int_trig_over_thres : std_logic_vector(1 to 4);
signal int_trig_over_thres_d : std_logic_vector(1 to 4);
signal int_trig_over_thres_filt : std_logic_vector(1 to 4);
signal int_trig_over_thres_filt_d : std_logic_vector(1 to 4);
signal int_trig_data : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_thres : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_test_en : std_logic;
signal int_trig_thres_filt : std_logic_vector(7 downto 0);
signal int_trig_thres_filt : t_fmc_adc_vec8_array(1 to 4);
signal hw_trig_pol : std_logic;
signal int_trig_pol : std_logic_vector(1 to 4);
signal hw_trig : std_logic;
signal hw_trig_t : std_logic;
signal hw_trig_sel : std_logic_vector(1 downto 0);
signal hw_trig_en : std_logic;
signal int_trig_en : std_logic_vector(1 to 4);
signal sw_trig : std_logic;
signal sw_trig_t : std_logic;
signal sw_trig_en : std_logic;
......@@ -665,32 +669,45 @@ begin
csr_regin.ch4_sta_val_i <= serdes_out_data(63 downto 48);
csr_regin.multi_depth_i <= c_MULTISHOT_SAMPLE_DEPTH;
fsm_cmd <= csr_regout.ctl_fsm_cmd_o;
fsm_cmd_wr <= csr_regout.ctl_fsm_cmd_wr_o;
gpio_si570_oe_o <= csr_regout.ctl_fmc_clk_oe_o;
gpio_dac_clr_n_o <= csr_regout.ctl_offset_dac_clr_n_o;
serdes_man_bitslip <= csr_regout.ctl_man_bitslip_o;
test_data_en <= csr_regout.ctl_test_data_en_o;
trig_led_man <= csr_regout.ctl_trig_led_o;
acq_led_man <= csr_regout.ctl_acq_led_o;
hw_trig_sel <= csr_regout.trig_cfg_hw_trig_sel_o;
hw_trig_pol <= csr_regout.trig_cfg_hw_trig_pol_o;
hw_trig_en <= csr_regout.trig_cfg_hw_trig_en_o;
sw_trig_en <= csr_regout.trig_cfg_sw_trig_en_o;
int_trig_sel <= csr_regout.trig_cfg_int_trig_sel_o;
int_trig_test_en <= csr_regout.trig_cfg_int_trig_test_en_o;
int_trig_thres_filt <= csr_regout.trig_cfg_int_trig_thres_filt_o;
int_trig_thres <= csr_regout.trig_cfg_int_trig_thres_o;
trig_delay <= csr_regout.trig_dly_o;
sw_trig_t <= csr_regout.sw_trig_wr_o;
shots_value <= csr_regout.shots_nb_o;
undersample_factor <= csr_regout.sr_undersample_o;
pre_trig_value <= csr_regout.pre_samples_o;
post_trig_value <= csr_regout.post_samples_o;
gpio_ssr_ch1_o <= csr_regout.ch1_ctl_ssr_o;
gpio_ssr_ch2_o <= csr_regout.ch2_ctl_ssr_o;
gpio_ssr_ch3_o <= csr_regout.ch3_ctl_ssr_o;
gpio_ssr_ch4_o <= csr_regout.ch4_ctl_ssr_o;
fsm_cmd <= csr_regout.ctl_fsm_cmd_o;
fsm_cmd_wr <= csr_regout.ctl_fsm_cmd_wr_o;
gpio_si570_oe_o <= csr_regout.ctl_fmc_clk_oe_o;
gpio_dac_clr_n_o <= csr_regout.ctl_offset_dac_clr_n_o;
serdes_man_bitslip <= csr_regout.ctl_man_bitslip_o;
test_data_en <= csr_regout.ctl_test_data_en_o;
trig_led_man <= csr_regout.ctl_trig_led_o;
acq_led_man <= csr_regout.ctl_acq_led_o;
hw_trig_sel <= csr_regout.trig_cfg_hw_trig_sel_o;
hw_trig_pol <= csr_regout.trig_cfg_ex_hw_trig_pol_o;
int_trig_pol(1) <= csr_regout.ch1_trig_trig_pol_o;
int_trig_pol(2) <= csr_regout.ch2_trig_trig_pol_o;
int_trig_pol(3) <= csr_regout.ch3_trig_trig_pol_o;
int_trig_pol(4) <= csr_regout.ch4_trig_trig_pol_o;
hw_trig_en <= csr_regout.trig_cfg_hw_trig_en_o;
sw_trig_en <= csr_regout.trig_cfg_sw_trig_en_o;
int_trig_en(1) <= csr_regout.ch1_trig_trig_en_o;
int_trig_en(2) <= csr_regout.ch2_trig_trig_en_o;
int_trig_en(3) <= csr_regout.ch3_trig_trig_en_o;
int_trig_en(4) <= csr_regout.ch4_trig_trig_en_o;
int_trig_test_en <= csr_regout.trig_cfg_int_trig_test_en_o;
int_trig_thres_filt(1) <= csr_regout.ch1_trig_int_trig_thres_filt_o;
int_trig_thres_filt(2) <= csr_regout.ch2_trig_int_trig_thres_filt_o;
int_trig_thres_filt(3) <= csr_regout.ch3_trig_int_trig_thres_filt_o;
int_trig_thres_filt(4) <= csr_regout.ch4_trig_int_trig_thres_filt_o;
int_trig_thres(1) <= csr_regout.ch1_trig_int_trig_thres_o;
int_trig_thres(2) <= csr_regout.ch2_trig_int_trig_thres_o;
int_trig_thres(3) <= csr_regout.ch3_trig_int_trig_thres_o;
int_trig_thres(4) <= csr_regout.ch4_trig_int_trig_thres_o;
trig_delay <= csr_regout.trig_dly_o;
sw_trig_t <= csr_regout.sw_trig_wr_o;
shots_value <= csr_regout.shots_nb_o;
undersample_factor <= csr_regout.sr_undersample_o;
pre_trig_value <= csr_regout.pre_samples_o;
post_trig_value <= csr_regout.post_samples_o;
gpio_ssr_ch1_o <= csr_regout.ch1_ctl_ssr_o;
gpio_ssr_ch2_o <= csr_regout.ch2_ctl_ssr_o;
gpio_ssr_ch3_o <= csr_regout.ch3_ctl_ssr_o;
gpio_ssr_ch4_o <= csr_regout.ch4_ctl_ssr_o;
gain_calibr <= csr_regout.ch4_gain_val_o & csr_regout.ch3_gain_val_o &
csr_regout.ch2_gain_val_o & csr_regout.ch1_gain_val_o;
......@@ -759,51 +776,51 @@ begin
ppulse_o => time_trig);
-- Internal hardware trigger
int_trig_data <= data_calibr_out(15 downto 0) when int_trig_sel = "00" else -- CH1 selected
data_calibr_out(31 downto 16) when int_trig_sel = "01" else -- CH2 selected
data_calibr_out(47 downto 32) when int_trig_sel = "10" else -- CH3 selected
data_calibr_out(63 downto 48) when int_trig_sel = "11" else -- CH4 selected
(others => '0');
-- Detects input data going over the internal trigger threshold
p_int_trig : process (fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
int_trig_over_thres <= '0';
elsif rising_edge(fs_clk) then
if signed(int_trig_data) > signed(int_trig_thres) then
int_trig_over_thres <= '1';
else
int_trig_over_thres <= '0';
g_int_trig : for I in 1 to 4 generate
int_trig_data(I) <= data_calibr_out(16*I-1 downto 16*I-16);
-- Detects input data going over the internal trigger threshold
p_int_trig : process (fs_clk, fs_rst_n)
begin
if (fs_rst_n = '0' or int_trig_en(I) = '0') then
int_trig_over_thres(I) <= '0';
elsif rising_edge(fs_clk) then
if signed(int_trig_data(I)) > signed(int_trig_thres(I)) then
int_trig_over_thres(I) <= '1';
else
int_trig_over_thres(I) <= '0';
end if;
end if;
end if;
end process p_int_trig;
end process p_int_trig;
-- Filters out glitches from over threshold signal (rejects noise around the threshold -> hysteresis)
cmp_dyn_glitch_filt : gc_dyn_glitch_filt
generic map(
g_len_width => 8
)
port map(
clk_i => fs_clk,
rst_n_i => fs_rst_n,
len_i => int_trig_thres_filt(7 downto 0),
dat_i => int_trig_over_thres,
dat_o => int_trig_over_thres_filt
);
-- Filters out glitches from over threshold signal (rejects noise around the threshold -> hysteresis)
cmp_dyn_glitch_filt : gc_dyn_glitch_filt
generic map(
g_len_width => 8
)
port map(
clk_i => fs_clk,
rst_n_i => fs_rst_n,
len_i => int_trig_thres_filt(I),
dat_i => int_trig_over_thres(I),
dat_o => int_trig_over_thres_filt(I)
);
-- Detects whether it's a positive or negative slope
p_int_trig_slope : process (fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
int_trig_over_thres_filt_d <= '0';
elsif rising_edge(fs_clk) then
int_trig_over_thres_filt_d <= int_trig_over_thres_filt;
end if;
end process;
-- Detects whether it's a positive or negative slope
p_int_trig_slope : process (fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
int_trig_over_thres_filt_d(I) <= '0';
elsif rising_edge(fs_clk) then
int_trig_over_thres_filt_d(I) <= int_trig_over_thres_filt(I);
end if;
end process;
int_ch_trig(I) <= int_trig_over_thres_filt(I) and not(int_trig_over_thres_filt_d(I)) when int_trig_pol(I) = '0' else -- positive slope
not(int_trig_over_thres_filt(I)) and int_trig_over_thres_filt_d(I); -- negative slope
end generate g_int_trig;
int_trig <= int_trig_over_thres_filt and not(int_trig_over_thres_filt_d) when hw_trig_pol = '0' else -- positive slope
not(int_trig_over_thres_filt) and int_trig_over_thres_filt_d; -- negative slope
int_trig <= int_ch_trig(1) or int_ch_trig(2) or int_ch_trig(3) or int_ch_trig(4);
-- Hardware trigger selection
-- 00: internal = adc data threshold
......@@ -952,9 +969,9 @@ begin
end process;
-- Internal trigger test mode
int_trig_over_thres_tst <= X"1000" when int_trig_over_thres = '1' else X"0000";
int_trig_over_thres_filt_tst <= X"1000" when int_trig_over_thres_filt = '1' else X"0000";
trig_tst <= X"1000" when trig_align = '1' else X"0000";
int_trig_over_thres_tst <= X"1000" when int_trig_over_thres(1) = '1' else X"0000";
int_trig_over_thres_filt_tst <= X"1000" when int_trig_over_thres_filt(1) = '1' else X"0000";
trig_tst <= X"1000" when trig_align = '1' else X"0000";
-- Delay data to compoensate for internal trigger detection
p_data_delay : process (fs_clk, fs_rst_n)
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ 9e14427f
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Thu Jun 16 17:04:12 2016
-- Created : Mon Jan 22 15:24:47 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -54,36 +54,18 @@ signal fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_hw_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_sw_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_sw_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_sw_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_sel_int : std_logic_vector(1 downto 0);
signal fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_trig_dly_int : std_logic_vector(31 downto 0);
signal fmc_adc_100ms_csr_sw_trig_wr_int : std_logic ;
signal fmc_adc_100ms_csr_sw_trig_wr_int_delay : std_logic ;
......@@ -117,6 +99,25 @@ signal fmc_adc_100ms_csr_ch1_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch1_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_reserved_int : std_logic_vector(5 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch2_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch2_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_sta_val_lwb : std_logic ;
......@@ -128,6 +129,25 @@ signal fmc_adc_100ms_csr_ch2_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch2_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_reserved_int : std_logic_vector(5 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch3_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch3_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_sta_val_lwb : std_logic ;
......@@ -139,6 +159,25 @@ signal fmc_adc_100ms_csr_ch3_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch3_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_reserved_int : std_logic_vector(5 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch4_ctl_ssr_int : std_logic_vector(6 downto 0);
signal fmc_adc_100ms_csr_ch4_sta_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_sta_val_lwb : std_logic ;
......@@ -150,25 +189,34 @@ signal fmc_adc_100ms_csr_ch4_sta_val_lwb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch4_gain_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_offset_val_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_sat_val_int : std_logic_vector(14 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_trig_en_int : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_trig_en_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_trig_en_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_trig_pol_int : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_trig_pol_sync0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_trig_pol_sync1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_reserved_int : std_logic_vector(5 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_int : std_logic_vector(7 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s2 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_int : std_logic_vector(15 downto 0);
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_delay : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s0 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s1 : std_logic ;
signal fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s2 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(5 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -188,19 +236,10 @@ begin
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_int <= "00";
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_delay <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_int <= '0';
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_int <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_en_int <= '0';
fmc_adc_100ms_csr_trig_cfg_sw_trig_en_int <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_int <= "00";
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_delay <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_int <= "00000000";
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_int <= "0000000000000000";
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_trig_dly_int <= "00000000000000000000000000000000";
fmc_adc_100ms_csr_sw_trig_wr_int <= '0';
fmc_adc_100ms_csr_sw_trig_wr_int_delay <= '0';
......@@ -220,6 +259,15 @@ begin
fmc_adc_100ms_csr_ch1_gain_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch1_offset_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch1_sat_val_int <= "000000000000000";
fmc_adc_100ms_csr_ch1_trig_trig_en_int <= '0';
fmc_adc_100ms_csr_ch1_trig_trig_pol_int <= '0';
fmc_adc_100ms_csr_ch1_trig_reserved_int <= "000000";
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_int <= "00000000";
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_int <= "0000000000000000";
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_ctl_ssr_int <= "0000000";
fmc_adc_100ms_csr_ch2_sta_val_lwb <= '0';
fmc_adc_100ms_csr_ch2_sta_val_lwb_delay <= '0';
......@@ -227,6 +275,15 @@ begin
fmc_adc_100ms_csr_ch2_gain_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch2_offset_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch2_sat_val_int <= "000000000000000";
fmc_adc_100ms_csr_ch2_trig_trig_en_int <= '0';
fmc_adc_100ms_csr_ch2_trig_trig_pol_int <= '0';
fmc_adc_100ms_csr_ch2_trig_reserved_int <= "000000";
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_int <= "00000000";
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_int <= "0000000000000000";
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_ctl_ssr_int <= "0000000";
fmc_adc_100ms_csr_ch3_sta_val_lwb <= '0';
fmc_adc_100ms_csr_ch3_sta_val_lwb_delay <= '0';
......@@ -234,6 +291,15 @@ begin
fmc_adc_100ms_csr_ch3_gain_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch3_offset_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch3_sat_val_int <= "000000000000000";
fmc_adc_100ms_csr_ch3_trig_trig_en_int <= '0';
fmc_adc_100ms_csr_ch3_trig_trig_pol_int <= '0';
fmc_adc_100ms_csr_ch3_trig_reserved_int <= "000000";
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_int <= "00000000";
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_int <= "0000000000000000";
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_ctl_ssr_int <= "0000000";
fmc_adc_100ms_csr_ch4_sta_val_lwb <= '0';
fmc_adc_100ms_csr_ch4_sta_val_lwb_delay <= '0';
......@@ -241,6 +307,15 @@ begin
fmc_adc_100ms_csr_ch4_gain_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch4_offset_val_int <= "0000000000000000";
fmc_adc_100ms_csr_ch4_sat_val_int <= "000000000000000";
fmc_adc_100ms_csr_ch4_trig_trig_en_int <= '0';
fmc_adc_100ms_csr_ch4_trig_trig_pol_int <= '0';
fmc_adc_100ms_csr_ch4_trig_reserved_int <= "000000";
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_int <= "00000000";
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_int <= "0000000000000000";
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_delay <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -255,12 +330,6 @@ begin
fmc_adc_100ms_csr_ctl_man_bitslip_int_delay <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb <= fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_delay;
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_delay <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb <= fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_delay;
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_delay <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_delay;
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_delay;
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_sw_trig_wr_int <= fmc_adc_100ms_csr_sw_trig_wr_int_delay;
fmc_adc_100ms_csr_sw_trig_wr_int_delay <= '0';
fmc_adc_100ms_csr_fs_freq_lwb <= fmc_adc_100ms_csr_fs_freq_lwb_delay;
......@@ -277,24 +346,40 @@ begin
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch1_sta_val_int;
fmc_adc_100ms_csr_ch1_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_delay;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_delay;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_sta_val_lwb <= fmc_adc_100ms_csr_ch2_sta_val_lwb_delay;
fmc_adc_100ms_csr_ch2_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_ch2_sta_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch2_sta_val_int;
fmc_adc_100ms_csr_ch2_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_delay;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_delay;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_sta_val_lwb <= fmc_adc_100ms_csr_ch3_sta_val_lwb_delay;
fmc_adc_100ms_csr_ch3_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_ch3_sta_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch3_sta_val_int;
fmc_adc_100ms_csr_ch3_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_delay;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_delay;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_sta_val_lwb <= fmc_adc_100ms_csr_ch4_sta_val_lwb_delay;
fmc_adc_100ms_csr_ch4_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_100ms_csr_ch4_sta_val_lwb_in_progress = '1')) then
rddata_reg(15 downto 0) <= fmc_adc_100ms_csr_ch4_sta_val_int;
fmc_adc_100ms_csr_ch4_sta_val_lwb_in_progress <= '0';
end if;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_delay;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_delay <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_delay;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -384,28 +469,42 @@ begin
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_int <= wrdata_reg(1 downto 0);
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb <= '1';
fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_swb_delay <= '1';
fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_int <= wrdata_reg(2);
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_int <= wrdata_reg(2);
fmc_adc_100ms_csr_trig_cfg_hw_trig_en_int <= wrdata_reg(3);
fmc_adc_100ms_csr_trig_cfg_sw_trig_en_int <= wrdata_reg(4);
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_int <= wrdata_reg(6 downto 5);
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb <= '1';
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_delay <= '1';
fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int <= wrdata_reg(7);
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb <= '1';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_delay <= '1';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb <= '1';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_delay <= '1';
fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int <= wrdata_reg(5);
end if;
rddata_reg(1 downto 0) <= fmc_adc_100ms_csr_trig_cfg_hw_trig_sel_int;
rddata_reg(2) <= fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_int;
rddata_reg(2) <= fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_int;
rddata_reg(3) <= fmc_adc_100ms_csr_trig_cfg_hw_trig_en_int;
rddata_reg(4) <= fmc_adc_100ms_csr_trig_cfg_sw_trig_en_int;
rddata_reg(6 downto 5) <= fmc_adc_100ms_csr_trig_cfg_int_trig_sel_int;
rddata_reg(7) <= fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int;
rddata_reg(15 downto 8) <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_int;
rddata_reg(5) <= fmc_adc_100ms_csr_trig_cfg_int_trig_test_en_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "000011" =>
......@@ -673,6 +772,25 @@ begin
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch1_trig_trig_en_int <= wrdata_reg(0);
fmc_adc_100ms_csr_ch1_trig_trig_pol_int <= wrdata_reg(1);
fmc_adc_100ms_csr_ch1_trig_reserved_int <= wrdata_reg(7 downto 2);
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb <= '1';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_delay <= '1';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb <= '1';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_delay <= '1';
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_ch1_trig_trig_en_int;
rddata_reg(1) <= fmc_adc_100ms_csr_ch1_trig_trig_pol_int;
rddata_reg(7 downto 2) <= fmc_adc_100ms_csr_ch1_trig_reserved_int;
rddata_reg(15 downto 8) <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "010011" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_ctl_ssr_int <= wrdata_reg(6 downto 0);
end if;
......@@ -704,7 +822,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010011" =>
when "010100" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -730,7 +848,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "010100" =>
when "010101" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_gain_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -753,7 +871,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010101" =>
when "010110" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_offset_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -776,7 +894,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010110" =>
when "010111" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_sat_val_int <= wrdata_reg(14 downto 0);
end if;
......@@ -800,7 +918,26 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010111" =>
when "011000" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch2_trig_trig_en_int <= wrdata_reg(0);
fmc_adc_100ms_csr_ch2_trig_trig_pol_int <= wrdata_reg(1);
fmc_adc_100ms_csr_ch2_trig_reserved_int <= wrdata_reg(7 downto 2);
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb <= '1';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_delay <= '1';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb <= '1';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_delay <= '1';
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_ch2_trig_trig_en_int;
rddata_reg(1) <= fmc_adc_100ms_csr_ch2_trig_trig_pol_int;
rddata_reg(7 downto 2) <= fmc_adc_100ms_csr_ch2_trig_reserved_int;
rddata_reg(15 downto 8) <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "011001" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_ctl_ssr_int <= wrdata_reg(6 downto 0);
end if;
......@@ -832,7 +969,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
when "011010" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -858,7 +995,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "011001" =>
when "011011" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_gain_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -881,7 +1018,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
when "011100" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_offset_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -904,7 +1041,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011011" =>
when "011101" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_sat_val_int <= wrdata_reg(14 downto 0);
end if;
......@@ -928,7 +1065,26 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
when "011110" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch3_trig_trig_en_int <= wrdata_reg(0);
fmc_adc_100ms_csr_ch3_trig_trig_pol_int <= wrdata_reg(1);
fmc_adc_100ms_csr_ch3_trig_reserved_int <= wrdata_reg(7 downto 2);
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb <= '1';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_delay <= '1';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb <= '1';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_delay <= '1';
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_ch3_trig_trig_en_int;
rddata_reg(1) <= fmc_adc_100ms_csr_ch3_trig_trig_pol_int;
rddata_reg(7 downto 2) <= fmc_adc_100ms_csr_ch3_trig_reserved_int;
rddata_reg(15 downto 8) <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "011111" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_ctl_ssr_int <= wrdata_reg(6 downto 0);
end if;
......@@ -960,7 +1116,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011101" =>
when "100000" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
......@@ -986,7 +1142,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "011110" =>
when "100001" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_gain_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -1009,7 +1165,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011111" =>
when "100010" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_offset_val_int <= wrdata_reg(15 downto 0);
end if;
......@@ -1032,7 +1188,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
when "100011" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_sat_val_int <= wrdata_reg(14 downto 0);
end if;
......@@ -1056,7 +1212,26 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100001" =>
when "100100" =>
if (wb_we_i = '1') then
fmc_adc_100ms_csr_ch4_trig_trig_en_int <= wrdata_reg(0);
fmc_adc_100ms_csr_ch4_trig_trig_pol_int <= wrdata_reg(1);
fmc_adc_100ms_csr_ch4_trig_reserved_int <= wrdata_reg(7 downto 2);
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_int <= wrdata_reg(15 downto 8);
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb <= '1';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_delay <= '1';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_int <= wrdata_reg(31 downto 16);
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb <= '1';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_delay <= '1';
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_ch4_trig_trig_en_int;
rddata_reg(1) <= fmc_adc_100ms_csr_ch4_trig_trig_pol_int;
rddata_reg(7 downto 2) <= fmc_adc_100ms_csr_ch4_trig_reserved_int;
rddata_reg(15 downto 8) <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_int;
rddata_reg(31 downto 16) <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.multi_depth_i;
......@@ -1129,18 +1304,18 @@ begin
end process;
-- Hardware trigger polarity
-- synchronizer chain for field : Hardware trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
-- External Hardware trigger polarity
-- synchronizer chain for field : External Hardware trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.trig_cfg_hw_trig_pol_o <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_sync1 <= '0';
regs_o.trig_cfg_ex_hw_trig_pol_o <= '0';
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_sync0 <= fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_int;
fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_sync1 <= fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_sync0;
regs_o.trig_cfg_hw_trig_pol_o <= fmc_adc_100ms_csr_trig_cfg_hw_trig_pol_sync1;
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync0 <= fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_int;
fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync1 <= fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync0;
regs_o.trig_cfg_ex_hw_trig_pol_o <= fmc_adc_100ms_csr_trig_cfg_ex_hw_trig_pol_sync1;
end if;
end process;
......@@ -1177,26 +1352,6 @@ begin
end process;
-- Channel selection for internal trigger
-- asynchronous std_logic_vector register : Channel selection for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s0 <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s1 <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s2 <= '0';
regs_o.trig_cfg_int_trig_sel_o <= "00";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s0 <= fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb;
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s1 <= fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s0;
fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s2 <= fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s1;
if ((fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s2 = '0') and (fmc_adc_100ms_csr_trig_cfg_int_trig_sel_swb_s1 = '1')) then
regs_o.trig_cfg_int_trig_sel_o <= fmc_adc_100ms_csr_trig_cfg_int_trig_sel_int;
end if;
end if;
end process;
-- Enable internal trigger test mode
-- synchronizer chain for field : Enable internal trigger test mode (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
......@@ -1213,46 +1368,6 @@ begin
end process;
-- Internal trigger threshold glitch filter
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s0 <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s1 <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s2 <= '0';
regs_o.trig_cfg_int_trig_thres_filt_o <= "00000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s0 <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb;
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s1 <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s0;
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s2 <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s1;
if ((fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s2 = '0') and (fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_swb_s1 = '1')) then
regs_o.trig_cfg_int_trig_thres_filt_o <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_filt_int;
end if;
end if;
end process;
-- Threshold for internal trigger
-- asynchronous std_logic_vector register : Threshold for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s0 <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s1 <= '0';
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s2 <= '0';
regs_o.trig_cfg_int_trig_thres_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s0 <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb;
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s1 <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s0;
fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s2 <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s1;
if ((fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s2 = '0') and (fmc_adc_100ms_csr_trig_cfg_int_trig_thres_swb_s1 = '1')) then
regs_o.trig_cfg_int_trig_thres_o <= fmc_adc_100ms_csr_trig_cfg_int_trig_thres_int;
end if;
end if;
end process;
-- Trigger delay value
regs_o.trig_dly_o <= fmc_adc_100ms_csr_trig_dly_int;
-- Software trigger (ignore on read)
......@@ -1350,6 +1465,80 @@ begin
regs_o.ch1_offset_val_o <= fmc_adc_100ms_csr_ch1_offset_val_int;
-- Saturation value for channel 1
regs_o.ch1_sat_val_o <= fmc_adc_100ms_csr_ch1_sat_val_int;
-- Trigger enable for channel 1
-- synchronizer chain for field : Trigger enable for channel 1 (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch1_trig_trig_en_o <= '0';
fmc_adc_100ms_csr_ch1_trig_trig_en_sync0 <= '0';
fmc_adc_100ms_csr_ch1_trig_trig_en_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch1_trig_trig_en_sync0 <= fmc_adc_100ms_csr_ch1_trig_trig_en_int;
fmc_adc_100ms_csr_ch1_trig_trig_en_sync1 <= fmc_adc_100ms_csr_ch1_trig_trig_en_sync0;
regs_o.ch1_trig_trig_en_o <= fmc_adc_100ms_csr_ch1_trig_trig_en_sync1;
end if;
end process;
-- Trigger polarity
-- synchronizer chain for field : Trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch1_trig_trig_pol_o <= '0';
fmc_adc_100ms_csr_ch1_trig_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_ch1_trig_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch1_trig_trig_pol_sync0 <= fmc_adc_100ms_csr_ch1_trig_trig_pol_int;
fmc_adc_100ms_csr_ch1_trig_trig_pol_sync1 <= fmc_adc_100ms_csr_ch1_trig_trig_pol_sync0;
regs_o.ch1_trig_trig_pol_o <= fmc_adc_100ms_csr_ch1_trig_trig_pol_sync1;
end if;
end process;
-- Reserved
regs_o.ch1_trig_reserved_o <= fmc_adc_100ms_csr_ch1_trig_reserved_int;
-- Internal trigger threshold glitch filter for Channel 1
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter for Channel 1 (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s0 <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s1 <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s2 <= '0';
regs_o.ch1_trig_int_trig_thres_filt_o <= "00000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s0 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s1 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s0;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s2 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s1;
if ((fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s2 = '0') and (fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_swb_s1 = '1')) then
regs_o.ch1_trig_int_trig_thres_filt_o <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_filt_int;
end if;
end if;
end process;
-- Threshold for Channel 1 internal trigger
-- asynchronous std_logic_vector register : Threshold for Channel 1 internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s0 <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s1 <= '0';
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s2 <= '0';
regs_o.ch1_trig_int_trig_thres_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s0 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s1 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s0;
fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s2 <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s1;
if ((fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s2 = '0') and (fmc_adc_100ms_csr_ch1_trig_int_trig_thres_swb_s1 = '1')) then
regs_o.ch1_trig_int_trig_thres_o <= fmc_adc_100ms_csr_ch1_trig_int_trig_thres_int;
end if;
end if;
end process;
-- Solid state relays control for channel 2
regs_o.ch2_ctl_ssr_o <= fmc_adc_100ms_csr_ch2_ctl_ssr_int;
-- Channel 2 current ACD value
......@@ -1378,6 +1567,80 @@ begin
regs_o.ch2_offset_val_o <= fmc_adc_100ms_csr_ch2_offset_val_int;
-- Saturation value for channel 2
regs_o.ch2_sat_val_o <= fmc_adc_100ms_csr_ch2_sat_val_int;
-- Trigger enable for channel 2
-- synchronizer chain for field : Trigger enable for channel 2 (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch2_trig_trig_en_o <= '0';
fmc_adc_100ms_csr_ch2_trig_trig_en_sync0 <= '0';
fmc_adc_100ms_csr_ch2_trig_trig_en_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch2_trig_trig_en_sync0 <= fmc_adc_100ms_csr_ch2_trig_trig_en_int;
fmc_adc_100ms_csr_ch2_trig_trig_en_sync1 <= fmc_adc_100ms_csr_ch2_trig_trig_en_sync0;
regs_o.ch2_trig_trig_en_o <= fmc_adc_100ms_csr_ch2_trig_trig_en_sync1;
end if;
end process;
-- Trigger polarity
-- synchronizer chain for field : Trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch2_trig_trig_pol_o <= '0';
fmc_adc_100ms_csr_ch2_trig_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_ch2_trig_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch2_trig_trig_pol_sync0 <= fmc_adc_100ms_csr_ch2_trig_trig_pol_int;
fmc_adc_100ms_csr_ch2_trig_trig_pol_sync1 <= fmc_adc_100ms_csr_ch2_trig_trig_pol_sync0;
regs_o.ch2_trig_trig_pol_o <= fmc_adc_100ms_csr_ch2_trig_trig_pol_sync1;
end if;
end process;
-- Reserved
regs_o.ch2_trig_reserved_o <= fmc_adc_100ms_csr_ch2_trig_reserved_int;
-- Internal trigger threshold glitch filter for Channel 2
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter for Channel 2 (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s0 <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s1 <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s2 <= '0';
regs_o.ch2_trig_int_trig_thres_filt_o <= "00000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s0 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s1 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s0;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s2 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s1;
if ((fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s2 = '0') and (fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_swb_s1 = '1')) then
regs_o.ch2_trig_int_trig_thres_filt_o <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_filt_int;
end if;
end if;
end process;
-- Threshold for Channel 2 internal trigger
-- asynchronous std_logic_vector register : Threshold for Channel 2 internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s0 <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s1 <= '0';
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s2 <= '0';
regs_o.ch2_trig_int_trig_thres_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s0 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s1 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s0;
fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s2 <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s1;
if ((fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s2 = '0') and (fmc_adc_100ms_csr_ch2_trig_int_trig_thres_swb_s1 = '1')) then
regs_o.ch2_trig_int_trig_thres_o <= fmc_adc_100ms_csr_ch2_trig_int_trig_thres_int;
end if;
end if;
end process;
-- Solid state relays control for channel 3
regs_o.ch3_ctl_ssr_o <= fmc_adc_100ms_csr_ch3_ctl_ssr_int;
-- Channel 3 current ADC value
......@@ -1406,6 +1669,80 @@ begin
regs_o.ch3_offset_val_o <= fmc_adc_100ms_csr_ch3_offset_val_int;
-- Saturation value for channel 3
regs_o.ch3_sat_val_o <= fmc_adc_100ms_csr_ch3_sat_val_int;
-- Trigger enable for channel 3
-- synchronizer chain for field : Trigger enable for channel 3 (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch3_trig_trig_en_o <= '0';
fmc_adc_100ms_csr_ch3_trig_trig_en_sync0 <= '0';
fmc_adc_100ms_csr_ch3_trig_trig_en_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch3_trig_trig_en_sync0 <= fmc_adc_100ms_csr_ch3_trig_trig_en_int;
fmc_adc_100ms_csr_ch3_trig_trig_en_sync1 <= fmc_adc_100ms_csr_ch3_trig_trig_en_sync0;
regs_o.ch3_trig_trig_en_o <= fmc_adc_100ms_csr_ch3_trig_trig_en_sync1;
end if;
end process;
-- Trigger polarity
-- synchronizer chain for field : Trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch3_trig_trig_pol_o <= '0';
fmc_adc_100ms_csr_ch3_trig_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_ch3_trig_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch3_trig_trig_pol_sync0 <= fmc_adc_100ms_csr_ch3_trig_trig_pol_int;
fmc_adc_100ms_csr_ch3_trig_trig_pol_sync1 <= fmc_adc_100ms_csr_ch3_trig_trig_pol_sync0;
regs_o.ch3_trig_trig_pol_o <= fmc_adc_100ms_csr_ch3_trig_trig_pol_sync1;
end if;
end process;
-- Reserved
regs_o.ch3_trig_reserved_o <= fmc_adc_100ms_csr_ch3_trig_reserved_int;
-- Internal trigger threshold glitch filter for Channel 3
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter for Channel 3 (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s0 <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s1 <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s2 <= '0';
regs_o.ch3_trig_int_trig_thres_filt_o <= "00000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s0 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s1 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s0;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s2 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s1;
if ((fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s2 = '0') and (fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_swb_s1 = '1')) then
regs_o.ch3_trig_int_trig_thres_filt_o <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_filt_int;
end if;
end if;
end process;
-- Threshold for Channel 3 internal trigger
-- asynchronous std_logic_vector register : Threshold for Channel 3 internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s0 <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s1 <= '0';
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s2 <= '0';
regs_o.ch3_trig_int_trig_thres_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s0 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s1 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s0;
fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s2 <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s1;
if ((fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s2 = '0') and (fmc_adc_100ms_csr_ch3_trig_int_trig_thres_swb_s1 = '1')) then
regs_o.ch3_trig_int_trig_thres_o <= fmc_adc_100ms_csr_ch3_trig_int_trig_thres_int;
end if;
end if;
end process;
-- Solid state relays control for channel 4
regs_o.ch4_ctl_ssr_o <= fmc_adc_100ms_csr_ch4_ctl_ssr_int;
-- Channel 4 current ADC value
......@@ -1434,6 +1771,80 @@ begin
regs_o.ch4_offset_val_o <= fmc_adc_100ms_csr_ch4_offset_val_int;
-- Saturation value for channel 4
regs_o.ch4_sat_val_o <= fmc_adc_100ms_csr_ch4_sat_val_int;
-- Trigger enable for channel 4
-- synchronizer chain for field : Trigger enable for channel 4 (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch4_trig_trig_en_o <= '0';
fmc_adc_100ms_csr_ch4_trig_trig_en_sync0 <= '0';
fmc_adc_100ms_csr_ch4_trig_trig_en_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch4_trig_trig_en_sync0 <= fmc_adc_100ms_csr_ch4_trig_trig_en_int;
fmc_adc_100ms_csr_ch4_trig_trig_en_sync1 <= fmc_adc_100ms_csr_ch4_trig_trig_en_sync0;
regs_o.ch4_trig_trig_en_o <= fmc_adc_100ms_csr_ch4_trig_trig_en_sync1;
end if;
end process;
-- trigger polarity
-- synchronizer chain for field : trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ch4_trig_trig_pol_o <= '0';
fmc_adc_100ms_csr_ch4_trig_trig_pol_sync0 <= '0';
fmc_adc_100ms_csr_ch4_trig_trig_pol_sync1 <= '0';
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch4_trig_trig_pol_sync0 <= fmc_adc_100ms_csr_ch4_trig_trig_pol_int;
fmc_adc_100ms_csr_ch4_trig_trig_pol_sync1 <= fmc_adc_100ms_csr_ch4_trig_trig_pol_sync0;
regs_o.ch4_trig_trig_pol_o <= fmc_adc_100ms_csr_ch4_trig_trig_pol_sync1;
end if;
end process;
-- Reserved
regs_o.ch4_trig_reserved_o <= fmc_adc_100ms_csr_ch4_trig_reserved_int;
-- Internal trigger threshold glitch filter for Channel 4
-- asynchronous std_logic_vector register : Internal trigger threshold glitch filter for Channel 4 (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s0 <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s1 <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s2 <= '0';
regs_o.ch4_trig_int_trig_thres_filt_o <= "00000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s0 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s1 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s0;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s2 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s1;
if ((fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s2 = '0') and (fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_swb_s1 = '1')) then
regs_o.ch4_trig_int_trig_thres_filt_o <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_filt_int;
end if;
end if;
end process;
-- Threshold for Channel 4 internal trigger
-- asynchronous std_logic_vector register : Threshold for Channel 4 internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s0 <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s1 <= '0';
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s2 <= '0';
regs_o.ch4_trig_int_trig_thres_o <= "0000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s0 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s1 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s0;
fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s2 <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s1;
if ((fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s2 = '0') and (fmc_adc_100ms_csr_ch4_trig_int_trig_thres_swb_s1 = '1')) then
regs_o.ch4_trig_int_trig_thres_o <= fmc_adc_100ms_csr_ch4_trig_int_trig_thres_int;
end if;
end if;
end process;
-- Multi-shot sample depth
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
......
hdl/adc/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
View file @ 9e14427f
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Thu Jun 16 17:04:12 2016
-- Created : Mon Jan 22 15:24:47 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -63,13 +63,10 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ctl_trig_led_o : std_logic;
ctl_acq_led_o : std_logic;
trig_cfg_hw_trig_sel_o : std_logic_vector(1 downto 0);
trig_cfg_hw_trig_pol_o : std_logic;
trig_cfg_ex_hw_trig_pol_o : std_logic;
trig_cfg_hw_trig_en_o : std_logic;
trig_cfg_sw_trig_en_o : std_logic;
trig_cfg_int_trig_sel_o : std_logic_vector(1 downto 0);
trig_cfg_int_trig_test_en_o : std_logic;
trig_cfg_int_trig_thres_filt_o : std_logic_vector(7 downto 0);
trig_cfg_int_trig_thres_o : std_logic_vector(15 downto 0);
trig_dly_o : std_logic_vector(31 downto 0);
sw_trig_o : std_logic_vector(31 downto 0);
sw_trig_wr_o : std_logic;
......@@ -81,18 +78,38 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ch1_gain_val_o : std_logic_vector(15 downto 0);
ch1_offset_val_o : std_logic_vector(15 downto 0);
ch1_sat_val_o : std_logic_vector(14 downto 0);
ch1_trig_trig_en_o : std_logic;
ch1_trig_trig_pol_o : std_logic;
ch1_trig_reserved_o : std_logic_vector(5 downto 0);
ch1_trig_int_trig_thres_filt_o : std_logic_vector(7 downto 0);
ch1_trig_int_trig_thres_o : std_logic_vector(15 downto 0);
ch2_ctl_ssr_o : std_logic_vector(6 downto 0);
ch2_gain_val_o : std_logic_vector(15 downto 0);
ch2_offset_val_o : std_logic_vector(15 downto 0);
ch2_sat_val_o : std_logic_vector(14 downto 0);
ch2_trig_trig_en_o : std_logic;
ch2_trig_trig_pol_o : std_logic;
ch2_trig_reserved_o : std_logic_vector(5 downto 0);
ch2_trig_int_trig_thres_filt_o : std_logic_vector(7 downto 0);
ch2_trig_int_trig_thres_o : std_logic_vector(15 downto 0);
ch3_ctl_ssr_o : std_logic_vector(6 downto 0);
ch3_gain_val_o : std_logic_vector(15 downto 0);
ch3_offset_val_o : std_logic_vector(15 downto 0);
ch3_sat_val_o : std_logic_vector(14 downto 0);
ch3_trig_trig_en_o : std_logic;
ch3_trig_trig_pol_o : std_logic;
ch3_trig_reserved_o : std_logic_vector(5 downto 0);
ch3_trig_int_trig_thres_filt_o : std_logic_vector(7 downto 0);
ch3_trig_int_trig_thres_o : std_logic_vector(15 downto 0);
ch4_ctl_ssr_o : std_logic_vector(6 downto 0);
ch4_gain_val_o : std_logic_vector(15 downto 0);
ch4_offset_val_o : std_logic_vector(15 downto 0);
ch4_sat_val_o : std_logic_vector(14 downto 0);
ch4_trig_trig_en_o : std_logic;
ch4_trig_trig_pol_o : std_logic;
ch4_trig_reserved_o : std_logic_vector(5 downto 0);
ch4_trig_int_trig_thres_filt_o : std_logic_vector(7 downto 0);
ch4_trig_int_trig_thres_o : std_logic_vector(15 downto 0);
end record;
constant c_fmc_adc_100ms_csr_out_registers_init_value: t_fmc_adc_100ms_csr_out_registers := (
......@@ -105,13 +122,10 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ctl_trig_led_o => '0',
ctl_acq_led_o => '0',
trig_cfg_hw_trig_sel_o => (others => '0'),
trig_cfg_hw_trig_pol_o => '0',
trig_cfg_ex_hw_trig_pol_o => '0',
trig_cfg_hw_trig_en_o => '0',
trig_cfg_sw_trig_en_o => '0',
trig_cfg_int_trig_sel_o => (others => '0'),
trig_cfg_int_trig_test_en_o => '0',
trig_cfg_int_trig_thres_filt_o => (others => '0'),
trig_cfg_int_trig_thres_o => (others => '0'),
trig_dly_o => (others => '0'),
sw_trig_o => (others => '0'),
sw_trig_wr_o => '0',
......@@ -123,18 +137,38 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ch1_gain_val_o => (others => '0'),
ch1_offset_val_o => (others => '0'),
ch1_sat_val_o => (others => '0'),
ch1_trig_trig_en_o => '0',
ch1_trig_trig_pol_o => '0',
ch1_trig_reserved_o => (others => '0'),
ch1_trig_int_trig_thres_filt_o => (others => '0'),
ch1_trig_int_trig_thres_o => (others => '0'),
ch2_ctl_ssr_o => (others => '0'),
ch2_gain_val_o => (others => '0'),
ch2_offset_val_o => (others => '0'),
ch2_sat_val_o => (others => '0'),
ch2_trig_trig_en_o => '0',
ch2_trig_trig_pol_o => '0',
ch2_trig_reserved_o => (others => '0'),
ch2_trig_int_trig_thres_filt_o => (others => '0'),
ch2_trig_int_trig_thres_o => (others => '0'),
ch3_ctl_ssr_o => (others => '0'),
ch3_gain_val_o => (others => '0'),
ch3_offset_val_o => (others => '0'),
ch3_sat_val_o => (others => '0'),
ch3_trig_trig_en_o => '0',
ch3_trig_trig_pol_o => '0',
ch3_trig_reserved_o => (others => '0'),
ch3_trig_int_trig_thres_filt_o => (others => '0'),
ch3_trig_int_trig_thres_o => (others => '0'),
ch4_ctl_ssr_o => (others => '0'),
ch4_gain_val_o => (others => '0'),
ch4_offset_val_o => (others => '0'),
ch4_sat_val_o => (others => '0')
ch4_sat_val_o => (others => '0'),
ch4_trig_trig_en_o => '0',
ch4_trig_trig_pol_o => '0',
ch4_trig_reserved_o => (others => '0'),
ch4_trig_int_trig_thres_filt_o => (others => '0'),
ch4_trig_int_trig_thres_o => (others => '0')
);
function "or" (left, right: t_fmc_adc_100ms_csr_in_registers) return t_fmc_adc_100ms_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -154,10 +188,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
if x(i) = '1' then
tmp(i):= '1';
else
tmp(i):=x(i);
tmp(i):= '0';
end if;
end loop;
return tmp;
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ 9e14427f
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Thu Jun 16 17:04:12 2016
* Created : Mon Jan 22 15:24:47 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -86,8 +86,8 @@
#define FMC_ADC_100MS_CSR_TRIG_CFG_HW_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC_ADC_100MS_CSR_TRIG_CFG_HW_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Hardware trigger polarity in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_HW_TRIG_POL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: External Hardware trigger polarity in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_EX_HW_TRIG_POL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Hardware trigger enable in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_HW_TRIG_EN WBGEN2_GEN_MASK(3, 1)
......@@ -95,26 +95,8 @@
/* definitions for field: Software trigger enable in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_SW_TRIG_EN WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Channel selection for internal trigger in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_SEL_MASK WBGEN2_GEN_MASK(5, 2)
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_SEL_SHIFT 5
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 5, 2)
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 5, 2)
/* definitions for field: Enable internal trigger test mode in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_TEST_EN WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Internal trigger threshold glitch filter in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_THRES_FILT_SHIFT 8
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Threshold for internal trigger in reg: Trigger configuration */
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_THRES_SHIFT 16
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
#define FMC_ADC_100MS_CSR_TRIG_CFG_INT_TRIG_TEST_EN WBGEN2_GEN_MASK(5, 1)
/* definitions for register: Trigger delay */
......@@ -194,6 +176,32 @@
#define FMC_ADC_100MS_CSR_CH1_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH1_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 1 trigger configuration register */
/* definitions for field: Trigger enable for channel 1 in reg: Channel 1 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_TRIG_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Trigger polarity in reg: Channel 1 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reserved in reg: Channel 1 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_RESERVED_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC_ADC_100MS_CSR_CH1_TRIG_RESERVED_SHIFT 2
#define FMC_ADC_100MS_CSR_CH1_TRIG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC_ADC_100MS_CSR_CH1_TRIG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Internal trigger threshold glitch filter for Channel 1 in reg: Channel 1 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_FILT_SHIFT 8
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Threshold for Channel 1 internal trigger in reg: Channel 1 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_SHIFT 16
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 control register */
/* definitions for field: Solid state relays control for channel 2 in reg: Channel 2 control register */
......@@ -234,6 +242,32 @@
#define FMC_ADC_100MS_CSR_CH2_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH2_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 2 trigger configuration register */
/* definitions for field: Trigger enable for channel 2 in reg: Channel 2 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_TRIG_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Trigger polarity in reg: Channel 2 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reserved in reg: Channel 2 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_RESERVED_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC_ADC_100MS_CSR_CH2_TRIG_RESERVED_SHIFT 2
#define FMC_ADC_100MS_CSR_CH2_TRIG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC_ADC_100MS_CSR_CH2_TRIG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Internal trigger threshold glitch filter for Channel 2 in reg: Channel 2 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_FILT_SHIFT 8
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Threshold for Channel 2 internal trigger in reg: Channel 2 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_SHIFT 16
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 control register */
/* definitions for field: Solid state relays control for channel 3 in reg: Channel 3 control register */
......@@ -274,6 +308,32 @@
#define FMC_ADC_100MS_CSR_CH3_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH3_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 3 trigger configuration register */
/* definitions for field: Trigger enable for channel 3 in reg: Channel 3 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_TRIG_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Trigger polarity in reg: Channel 3 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reserved in reg: Channel 3 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_RESERVED_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC_ADC_100MS_CSR_CH3_TRIG_RESERVED_SHIFT 2
#define FMC_ADC_100MS_CSR_CH3_TRIG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC_ADC_100MS_CSR_CH3_TRIG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Internal trigger threshold glitch filter for Channel 3 in reg: Channel 3 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_FILT_SHIFT 8
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Threshold for Channel 3 internal trigger in reg: Channel 3 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_SHIFT 16
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 control register */
/* definitions for field: Solid state relays control for channel 4 in reg: Channel 4 control register */
......@@ -314,6 +374,32 @@
#define FMC_ADC_100MS_CSR_CH4_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH4_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 4 trigger configuration register */
/* definitions for field: Trigger enable for channel 4 in reg: Channel 4 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_TRIG_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: trigger polarity in reg: Channel 4 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_TRIG_POL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reserved in reg: Channel 4 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_RESERVED_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC_ADC_100MS_CSR_CH4_TRIG_RESERVED_SHIFT 2
#define FMC_ADC_100MS_CSR_CH4_TRIG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC_ADC_100MS_CSR_CH4_TRIG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Internal trigger threshold glitch filter for Channel 4 in reg: Channel 4 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_FILT_SHIFT 8
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_FILT_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_FILT_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Threshold for Channel 4 internal trigger in reg: Channel 4 trigger configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_SHIFT 16
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Multi-shot sample depth register */
PACKED struct FMC_ADC_100MS_CSR_WB {
......@@ -353,37 +439,45 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t CH1_OFFSET;
/* [0x44]: REG Channel 1 saturation register */
uint32_t CH1_SAT;
/* [0x48]: REG Channel 2 control register */
/* [0x48]: REG Channel 1 trigger configuration register */
uint32_t CH1_TRIG;
/* [0x4c]: REG Channel 2 control register */
uint32_t CH2_CTL;
/* [0x4c]: REG Channel 2 status register */
/* [0x50]: REG Channel 2 status register */
uint32_t CH2_STA;
/* [0x50]: REG Channel 2 gain calibration register */
/* [0x54]: REG Channel 2 gain calibration register */
uint32_t CH2_GAIN;
/* [0x54]: REG Channel 2 offset calibration register */
/* [0x58]: REG Channel 2 offset calibration register */
uint32_t CH2_OFFSET;
/* [0x58]: REG Channel 2 saturation register */
/* [0x5c]: REG Channel 2 saturation register */
uint32_t CH2_SAT;
/* [0x5c]: REG Channel 3 control register */
/* [0x60]: REG Channel 2 trigger configuration register */
uint32_t CH2_TRIG;
/* [0x64]: REG Channel 3 control register */
uint32_t CH3_CTL;
/* [0x60]: REG Channel 3 status register */
/* [0x68]: REG Channel 3 status register */
uint32_t CH3_STA;
/* [0x64]: REG Channel 3 gain calibration register */
/* [0x6c]: REG Channel 3 gain calibration register */
uint32_t CH3_GAIN;
/* [0x68]: REG Channel 3 offset calibration register */
/* [0x70]: REG Channel 3 offset calibration register */
uint32_t CH3_OFFSET;
/* [0x6c]: REG Channel 3 saturation register */
/* [0x74]: REG Channel 3 saturation register */
uint32_t CH3_SAT;
/* [0x70]: REG Channel 4 control register */
/* [0x78]: REG Channel 3 trigger configuration register */
uint32_t CH3_TRIG;
/* [0x7c]: REG Channel 4 control register */
uint32_t CH4_CTL;
/* [0x74]: REG Channel 4 status register */
/* [0x80]: REG Channel 4 status register */
uint32_t CH4_STA;
/* [0x78]: REG Channel 4 gain calibration register */
/* [0x84]: REG Channel 4 gain calibration register */
uint32_t CH4_GAIN;
/* [0x7c]: REG Channel 4 offset calibration register */
/* [0x88]: REG Channel 4 offset calibration register */
uint32_t CH4_OFFSET;
/* [0x80]: REG Channel 4 saturation register */
/* [0x8c]: REG Channel 4 saturation register */
uint32_t CH4_SAT;
/* [0x84]: REG Multi-shot sample depth register */
/* [0x90]: REG Channel 4 trigger configuration register */
uint32_t CH4_TRIG;
/* [0x94]: REG Multi-shot sample depth register */
uint32_t MULTI_DEPTH;
};
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ 9e14427f
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hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ 9e14427f
......@@ -151,9 +151,9 @@ peripheral {
};
field {
name = "Hardware trigger polarity";
name = "External Hardware trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "hw_trig_pol";
prefix = "ex_hw_trig_pol";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -180,17 +180,6 @@ peripheral {
clock = "fs_clk_i";
};
field {
name = "Channel selection for internal trigger";
description = "00: channel 1\n01: channel 2\n10: channel 3\n11: channel 4";
prefix = "int_trig_sel";
type = SLV;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Enable internal trigger test mode";
description = "Test mode:\n ch1 = Channel 1 input(analogue)\n ch2 = Channel input over threshold (digital)\n ch3 = Channel input over threshold filtered (digital)\n ch4 = Trigger (digital)";
......@@ -201,27 +190,18 @@ peripheral {
clock = "fs_clk_i";
};
--[[
field {
name = "Internal trigger threshold glitch filter";
description = "Configures the internal trigger threshold glitch filter length.";
prefix = "int_trig_thres_filt";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres";
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
size = 26;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
]]
};
reg {
......@@ -521,6 +501,59 @@ peripheral {
]]
};
reg {
name = "Channel 1 trigger configuration register";
prefix = "ch1_trig";
field {
name = "Trigger enable for channel 1";
discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
prefix = "trig_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "trig_pol";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal trigger threshold glitch filter for Channel 1";
description = "Configures the internal trigger threshold glitch filter length.";
prefix = "int_trig_thres_filt";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Threshold for Channel 1 internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 2 control register";
prefix = "ch2_ctl";
......@@ -652,6 +685,59 @@ peripheral {
]]
};
reg {
name = "Channel 2 trigger configuration register";
prefix = "ch2_trig";
field {
name = "Trigger enable for channel 2";
discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
prefix = "trig_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "trig_pol";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal trigger threshold glitch filter for Channel 2";
description = "Configures the internal trigger threshold glitch filter length.";
prefix = "int_trig_thres_filt";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Threshold for Channel 2 internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 3 control register";
prefix = "ch3_ctl";
......@@ -783,6 +869,59 @@ peripheral {
]]
};
reg {
name = "Channel 3 trigger configuration register";
prefix = "ch3_trig";
field {
name = "Trigger enable for channel 3";
discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
prefix = "trig_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "trig_pol";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal trigger threshold glitch filter for Channel 3";
description = "Configures the internal trigger threshold glitch filter length.";
prefix = "int_trig_thres_filt";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Threshold for Channel 3 internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 4 control register";
prefix = "ch4_ctl";
......@@ -914,6 +1053,60 @@ peripheral {
]]
};
reg {
name = "Channel 4 trigger configuration register";
prefix = "ch4_trig";
field {
name = "Trigger enable for channel 4";
discription = "0: disable\n1: enable, Active only if internal trigger in Trigger Configuration is enabled";
prefix = "trig_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "trigger polarity";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "trig_pol";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal trigger threshold glitch filter for Channel 4";
description = "Configures the internal trigger threshold glitch filter length.";
prefix = "int_trig_thres_filt";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Threshold for Channel 4 internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "int_trig_thres";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Multi-shot sample depth register";
prefix = "multi_depth";
......
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