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FMC ADC 100M 14b 4cha - Gateware
Commit ad1db4c2 authored by Matthieu Cattin's avatar Matthieu Cattin
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syn: spec-fmc-adc gateware release 4.0

parent 5caab66f
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hdl/spec/rtl/sdb_meta_pkg.vhd
View file @ ad1db4c2
......@@ -54,13 +54,13 @@ package sdb_meta_pkg is
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "697546304b7a1890aba8d6effd935a0f",
syn_commit_id => "26749f0a1873c215abb33942a8a335db",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date => x"20140116",
syn_date => x"20140425",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
......@@ -69,8 +69,8 @@ package sdb_meta_pkg is
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00030000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20140116", -- yyyymmdd
version => x"00040000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20140425", -- yyyymmdd
name => "spec_fmcadc100m14b "));
......
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ ad1db4c2
......@@ -473,366 +473,372 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
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</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
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</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
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</file>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
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</file>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
</files>
<bindings/>
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
View file @ ad1db4c2
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Thu Jan 16 18:02:06 2014
pcbe15575:: Fri Apr 25 16:32:51 2014
par -w -intstyle ise -ol high -mt off spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
......@@ -10,6 +10,12 @@ spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
Constraints file: spec_top_fmc_adc_100Ms.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment /opt/Xilinx/13.3/ISE_DS/ISE/.
"spec_top_fmc_adc_100Ms" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:42 - Your license support version '2014.04' for ISE expires in 4 days after which you will not qualify
for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
......@@ -22,36 +28,36 @@ Device speed data version: "PRODUCTION 1.20 2011-10-03".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 6,698 out of 54,576 12%
Number used as Flip Flops: 6,698
Number of Slice Registers: 6,815 out of 54,576 12%
Number used as Flip Flops: 6,786
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,758 out of 27,288 21%
Number used as logic: 5,404 out of 27,288 19%
Number using O6 output only: 3,644
Number using O5 output only: 368
Number using O5 and O6: 1,392
Number used as AND/OR logics: 29
Number of Slice LUTs: 6,024 out of 27,288 22%
Number used as logic: 5,626 out of 27,288 20%
Number using O6 output only: 3,598
Number using O5 output only: 363
Number using O5 and O6: 1,665
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Memory: 34 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 2
Number used as Shift Register: 34
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 352
Number with same-slice register load: 328
Number using O5 and O6: 32
Number used exclusively as route-thrus: 364
Number with same-slice register load: 340
Number with same-slice carry load: 24
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,468 out of 6,822 36%
Nummber of MUXCYs used: 1,440 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,910
Number with an unused Flip Flop: 1,939 out of 7,910 24%
Number with an unused LUT: 2,152 out of 7,910 27%
Number of fully used LUT-FF pairs: 3,819 out of 7,910 48%
Number of occupied Slices: 2,500 out of 6,822 36%
Nummber of MUXCYs used: 1,660 out of 13,644 12%
Number of LUT Flip Flop pairs used: 8,097
Number with an unused Flip Flop: 2,095 out of 8,097 25%
Number with an unused LUT: 2,073 out of 8,097 25%
Number of fully used LUT-FF pairs: 3,929 out of 8,097 48%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -62,12 +68,12 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 188 out of 296 63%
Number of LOCed IOBs: 188 out of 188 100%
Number of bonded IOBs: 192 out of 296 64%
Number of LOCed IOBs: 192 out of 192 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 26 out of 116 22%
Number of RAMB8BWERs: 4 out of 232 1%
Number of RAMB16BWERs: 23 out of 116 19%
Number of RAMB8BWERs: 7 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
......@@ -110,40 +116,40 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 24 secs
Finished initial Timing Analysis. REAL time: 24 secs
Finished initial Timing Analysis. REAL time: 25 secs
WARNING:Par:288 - The signal aux_buttons_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal aux_buttons_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal aux_buttons_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal aux_buttons_i<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 40071 unrouted; REAL time: 26 secs
Phase 1 : 40605 unrouted; REAL time: 26 secs
Phase 2 : 34430 unrouted; REAL time: 30 secs
Phase 2 : 34579 unrouted; REAL time: 30 secs
Phase 3 : 13949 unrouted; REAL time: 54 secs
Phase 3 : 13915 unrouted; REAL time: 55 secs
Phase 4 : 13983 unrouted; (Setup:0, Hold:7686, Component Switching Limit:0) REAL time: 1 mins
Phase 4 : 13928 unrouted; (Setup:0, Hold:1824, Component Switching Limit:0) REAL time: 58 secs
Updating file: spec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:7456, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:1501, Component Switching Limit:0) REAL time: 1 mins 26 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:7456, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1501, Component Switching Limit:0) REAL time: 1 mins 26 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7456, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1501, Component Switching Limit:0) REAL time: 1 mins 26 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7456, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1501, Component Switching Limit:0) REAL time: 1 mins 26 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 27 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 32 secs
Total REAL time to Router completion: 1 mins 32 secs
Total CPU time to Router completion: 1 mins 25 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 30 secs
Total REAL time to Router completion: 1 mins 30 secs
Total CPU time to Router completion: 1 mins 23 secs
Partition Implementation Status
-------------------------------
......@@ -161,20 +167,20 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X3Y13| No | 1208 | 0.069 | 1.280 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y2| No | 162 | 0.238 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y12| No | 641 | 0.187 | 1.398 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X3Y13| No | 1251 | 0.069 | 1.280 |
| s_core/fs_clk | BUFGMUX_X2Y2| No | 226 | 0.257 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_mcb_d | | | | | |
| rp_clk | BUFGMUX_X2Y3| No | 82 | 0.072 | 1.285 |
| rp_clk | BUFGMUX_X2Y3| No | 79 | 0.052 | 1.285 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y12| No | 635 | 0.187 | 1.398 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
......@@ -290,21 +296,21 @@ Asterisk (*) preceding a constraint indicates it was not met.
_ddr3_ctrl_memc3_infrastructure_inst_clk_ | | | | |
2x_0" TS_SYS_CLK5 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.027ns| 4.973ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.136ns| | 0| 0
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.035ns| 4.965ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.042ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.073ns| 7.927ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.275ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
0Ms_core_dco_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100 | | | | |
Ms_core_dco_clk" TS_adc_dco_n_i H | | | | |
IGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.099ns| 7.901ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.287ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_SYS_CLK5 = PERIOD TIMEGRP "SYS_CLK5" 3 | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
ns HIGH 50% | | | | |
......@@ -313,8 +319,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
buf" TS_clk20_vcxo_i / 16.6666667 | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | SETUP | 0.806ns| 7.194ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.393ns| | 0| 0
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | SETUP | 0.946ns| 7.054ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.399ns| | 0| 0
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_ | | | | |
100Ms_core_fs_clk_buf" TS_cmp_fmc | | | | |
_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_d | | | | |
......@@ -348,8 +354,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 4.451ns| 7.548ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.393ns| | 0| 0
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 4.268ns| 7.731ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.270ns| | 0| 0
nfrastructure_inst_mcb_drp_clk_bufg_in_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr | | | | |
_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank | | | | |
......@@ -412,12 +418,12 @@ Derived Constraints for TS_p2l_clkn
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.973ns| 0| 0| 0| 30234|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.973ns| 0| 0| 0| 30234|
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.965ns| 0| 0| 0| 29557|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.965ns| 0| 0| 0| 29557|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.973ns| N/A| 0| 0| 30234| 0|
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.965ns| N/A| 0| 0| 29557| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -427,10 +433,10 @@ Derived Constraints for TS_clk20_vcxo_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 410728|
| TS_sys_clk_125_buf | 8.000ns| 7.927ns| N/A| 0| 0| 400328| 0|
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 398349|
| TS_sys_clk_125_buf | 8.000ns| 7.901ns| N/A| 0| 0| 387949| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 10400|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 7.548ns| N/A| 0| 0| 10400| 0|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 7.731ns| N/A| 0| 0| 10400| 0|
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_mcb_drp_clk_buf| | | | | | | |
......@@ -472,10 +478,10 @@ Derived Constraints for TS_adc_dco_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc_dco_n_i | 2.000ns| 0.925ns| 1.798ns| 0| 0| 0| 47928|
| TS_cmp_fmc_adc_mezzanine_0_cmp| 2.000ns| 1.636ns| 1.798ns| 0| 0| 0| 47928|
|TS_adc_dco_n_i | 2.000ns| 0.925ns| 1.764ns| 0| 0| 0| 53971|
| TS_cmp_fmc_adc_mezzanine_0_cmp| 2.000ns| 1.636ns| 1.764ns| 0| 0| 0| 53971|
| _fmc_adc_100Ms_core_dco_clk | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 8.000ns| 7.194ns| N/A| 0| 0| 47928| 0|
| TS_cmp_fmc_adc_mezzanine_0_cm| 8.000ns| 7.054ns| N/A| 0| 0| 53971| 0|
| p_fmc_adc_100Ms_core_fs_clk_b| | | | | | | |
| uf | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 1.000ns| N/A| N/A| 0| 0| 0| 0|
......@@ -497,10 +503,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 35 secs
Total CPU time to PAR completion: 1 mins 28 secs
Total REAL time to PAR completion: 1 mins 33 secs
Total CPU time to PAR completion: 1 mins 26 secs
Peak Memory Usage: 335 MB
Peak Memory Usage: 337 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
View file @ ad1db4c2
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
View file @ ad1db4c2
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
View file @ ad1db4c2
......@@ -11,46 +11,46 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Jan 16 17:57:07 2014
Mapped Date : Fri Apr 25 16:27:42 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,698 out of 54,576 12%
Number used as Flip Flops: 6,698
Number of Slice Registers: 6,815 out of 54,576 12%
Number used as Flip Flops: 6,786
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,758 out of 27,288 21%
Number used as logic: 5,404 out of 27,288 19%
Number using O6 output only: 3,644
Number using O5 output only: 368
Number using O5 and O6: 1,392
Number used as AND/OR logics: 29
Number of Slice LUTs: 6,024 out of 27,288 22%
Number used as logic: 5,626 out of 27,288 20%
Number using O6 output only: 3,598
Number using O5 output only: 363
Number using O5 and O6: 1,665
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Memory: 34 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 2
Number used as Shift Register: 34
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 352
Number with same-slice register load: 328
Number using O5 and O6: 32
Number used exclusively as route-thrus: 364
Number with same-slice register load: 340
Number with same-slice carry load: 24
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,468 out of 6,822 36%
Nummber of MUXCYs used: 1,440 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,910
Number with an unused Flip Flop: 1,939 out of 7,910 24%
Number with an unused LUT: 2,152 out of 7,910 27%
Number of fully used LUT-FF pairs: 3,819 out of 7,910 48%
Number of unique control sets: 237
Number of occupied Slices: 2,500 out of 6,822 36%
Nummber of MUXCYs used: 1,660 out of 13,644 12%
Number of LUT Flip Flop pairs used: 8,097
Number with an unused Flip Flop: 2,095 out of 8,097 25%
Number with an unused LUT: 2,073 out of 8,097 25%
Number of fully used LUT-FF pairs: 3,929 out of 8,097 48%
Number of unique control sets: 251
Number of slice register sites lost
to control set restrictions: 548 out of 54,576 1%
to control set restrictions: 532 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -59,12 +59,12 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 188 out of 296 63%
Number of LOCed IOBs: 188 out of 188 100%
Number of bonded IOBs: 192 out of 296 64%
Number of LOCed IOBs: 192 out of 192 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 26 out of 116 22%
Number of RAMB8BWERs: 4 out of 232 1%
Number of RAMB16BWERs: 23 out of 116 19%
Number of RAMB8BWERs: 7 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.80
Average Fanout of Non-Clock Nets: 3.73
Peak Memory Usage: 409 MB
Total REAL time to MAP completion: 4 mins 52 secs
Total CPU time to MAP completion (all processors): 4 mins 43 secs
Peak Memory Usage: 415 MB
Total REAL time to MAP completion: 5 mins 2 secs
Total CPU time to MAP completion (all processors): 4 mins 55 secs
Table of Contents
-----------------
......@@ -127,6 +127,9 @@ Section 1 - Errors
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your license support version '2014.04' for ISE expires in
4 days after which you will not qualify for Xilinx software updates or new
releases.
WARNING:MapLib:701 - Signal L_CLKp connected to top level port L_CLKp has been
removed.
WARNING:MapLib:701 - Signal L_CLKn connected to top level port L_CLKn has been
......@@ -159,13 +162,14 @@ Section 3 - Informational
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run.
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
INFO:LIT:243 - Logical network
cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown):
N798,
N800,
N776,
N778,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......@@ -186,7 +190,7 @@ INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
93 block(s) removed
94 block(s) removed
2 block(s) optimized away
74 signal(s) removed
......@@ -378,6 +382,9 @@ nfrastructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
Loadless block "cmp_clk_250_buf" (CKBUF) removed.
The signal "sys_clk_250_buf" is loadless and has been removed.
Loadless block
"cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Madd_pre_trig_value[31]_GND_383_
o_add_67_OUT31" (ROM) removed.
Loadless block
"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[0].loop3.iodelay_m" (IODELAY2)
removed.
The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" is loadless
......@@ -803,6 +810,10 @@ Section 6 - IOB Properties
| pcb_ver_i<1> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<2> | IOB | INPUT | LVCMOS15 | | | | | | |
| pcb_ver_i<3> | IOB | INPUT | LVCMOS15 | | | | | | |
| pll20dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| pll25dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| plldac_din_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| plldac_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
......
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