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FMC ADC 100M 14b 4cha - Gateware
Commit b48832a9 authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Insert trigger time-tag in data, after post-trigger samples.

parent 94774b66
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hdl/adc/rtl/fmc_adc_100Ms_core.vhd
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......@@ -39,6 +39,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
library UNISIM;
......@@ -85,6 +86,9 @@ entity fmc_adc_100Ms_core is
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
......@@ -276,7 +280,7 @@ architecture rtl of fmc_adc_100Ms_core is
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
type t_acq_fsm_state is (IDLE, PRE_TRIG, WAIT_TRIG, POST_TRIG, DECR_SHOT);
type t_acq_fsm_state is (IDLE, PRE_TRIG, WAIT_TRIG, POST_TRIG, TRIG_TAG, DECR_SHOT);
------------------------------------------------------------------------------
-- Signals declaration
......@@ -346,7 +350,6 @@ architecture rtl of fmc_adc_100Ms_core is
signal sync_fifo_wr : std_logic;
signal sync_fifo_rd : std_logic;
signal sync_fifo_valid : std_logic;
signal sync_fifo_dreq : std_logic;
-- Gain/offset calibration
signal gain_calibr : std_logic_vector(63 downto 0);
......@@ -355,7 +358,6 @@ architecture rtl of fmc_adc_100Ms_core is
signal data_calibr_out : std_logic_vector(63 downto 0);
signal data_calibr_out_d : std_logic_vector(63 downto 0);
-- Acquisition FSM
signal acq_fsm_current_state : t_acq_fsm_state;
signal acq_fsm_state : std_logic_vector(2 downto 0);
......@@ -369,8 +371,14 @@ architecture rtl of fmc_adc_100Ms_core is
signal acq_in_pre_trig : std_logic;
signal acq_in_wait_trig : std_logic;
signal acq_in_post_trig : std_logic;
signal acq_in_trig_tag : std_logic;
signal samples_wr_en : std_logic;
-- Trigger tag insertion in data
signal trig_tag_done : std_logic;
signal trig_tag_data : std_logic_vector(63 downto 0);
signal trig_tag_progress : std_logic_vector(1 downto 0);
-- pre/post trigger and shots counters
signal pre_trig_value : std_logic_vector(31 downto 0);
signal pre_trig_cnt : unsigned(31 downto 0);
......@@ -970,7 +978,7 @@ begin
-- "00000000" & serdes_out_fr;
sync_fifo_wr <= decim_en and serdes_synced and not(sync_fifo_full);
sync_fifo_rd <= sync_fifo_dreq and not(sync_fifo_empty);
sync_fifo_rd <= not(sync_fifo_empty); -- read sync fifo as soon as data are available
--============================================================================
......@@ -1162,6 +1170,13 @@ begin
if acq_stop = '1' then
acq_fsm_current_state <= IDLE;
elsif post_trig_done = '1' then
acq_fsm_current_state <= TRIG_TAG;
end if;
when TRIG_TAG =>
if acq_stop = '1' then
acq_fsm_current_state <= IDLE;
elsif trig_tag_done = '1' then
if single_shot = '1' then
acq_fsm_current_state <= IDLE;
else
......@@ -1195,55 +1210,64 @@ begin
when IDLE =>
shots_decr <= '0';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '0';
acq_in_wait_trig <= '0';
acq_in_post_trig <= '0';
acq_in_trig_tag <= '0';
samples_wr_en <= '0';
acq_fsm_state <= "001";
when PRE_TRIG =>
shots_decr <= '0';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '1';
acq_in_wait_trig <= '0';
acq_in_post_trig <= '0';
acq_in_trig_tag <= '0';
samples_wr_en <= '1';
acq_fsm_state <= "010";
when WAIT_TRIG =>
shots_decr <= '0';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '0';
acq_in_wait_trig <= '1';
acq_in_post_trig <= '0';
acq_in_trig_tag <= '0';
samples_wr_en <= '1';
acq_fsm_state <= "011";
when POST_TRIG =>
shots_decr <= '0';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '0';
acq_in_wait_trig <= '0';
acq_in_post_trig <= '1';
acq_in_trig_tag <= '0';
samples_wr_en <= '1';
acq_fsm_state <= "100";
when TRIG_TAG =>
shots_decr <= '0';
acq_in_pre_trig <= '0';
acq_in_wait_trig <= '0';
acq_in_post_trig <= '0';
acq_in_trig_tag <= '1';
samples_wr_en <= '0';
acq_fsm_state <= "101";
when DECR_SHOT =>
shots_decr <= '1';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '0';
acq_in_wait_trig <= '0';
acq_in_post_trig <= '0';
acq_in_trig_tag <= '0';
samples_wr_en <= '0';
acq_fsm_state <= "101";
acq_fsm_state <= "110";
when others =>
shots_decr <= '0';
sync_fifo_dreq <= '1';
acq_in_pre_trig <= '0';
acq_in_wait_trig <= '0';
acq_in_post_trig <= '0';
acq_in_trig_tag <= '0';
samples_wr_en <= '0';
acq_fsm_state <= "111";
......@@ -1251,256 +1275,281 @@ begin
end process p_acq_fsm_outputs;
------------------------------------------------------------------------------
-- Dual DPRAM buffers for multi-shots acquisition
-----------------------------------------------------------------------------
-- DPRAM input address counter
p_dpram_addra_cnt : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
dpram_addra_cnt <= (others => '0');
dpram_addra_trig <= (others => '0');
dpram_addra_post_done <= (others => '0');
elsif rising_edge(sys_clk_i) then
if shots_decr = '1' then
dpram_addra_cnt <= to_unsigned(0, dpram_addra_cnt'length);
elsif (samples_wr_en = '1' and sync_fifo_valid = '1') then
dpram_addra_cnt <= dpram_addra_cnt + 1;
end if;
if acq_trig = '1' then
dpram_addra_trig <= dpram_addra_cnt;
end if;
if post_trig_done = '1' then
if unsigned(post_trig_value) = to_unsigned(0, post_trig_value'length) then
dpram_addra_post_done <= dpram_addra_cnt - 1;
else
dpram_addra_post_done <= dpram_addra_cnt;
-- Inserting trigger time-tag after post_trigger samples
------------------------------------------------------------------------------
-- ###
p_insert_trig_tag : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
trig_tag_data <= (others => '0');
trig_tag_progress <= (others => '0');
elsif rising_edge(sys_clk_i) then
trig_tag_done <= acq_in_trig_tag;
if trig_tag_done = '0' then
trig_tag_data <= trigger_tag_i.seconds & trigger_tag_i.meta;
elsif trig_tag_done = '1' then
trig_tag_data <= trigger_tag_i.fine & trigger_tag_i.coarse;
end if;
end if;
end if;
end process p_dpram_addra_cnt;
-- DPRAM inputs
dpram0_addra <= std_logic_vector(dpram_addra_cnt);
dpram1_addra <= std_logic_vector(dpram_addra_cnt);
dpram0_dina <= sync_fifo_dout(63 downto 0);
dpram1_dina <= sync_fifo_dout(63 downto 0);
dpram0_wea <= (samples_wr_en and sync_fifo_valid) when multishot_buffer_sel = '0' else '0';
dpram1_wea <= (samples_wr_en and sync_fifo_valid) when multishot_buffer_sel = '1' else '0';
-- DPRAMs
cmp_multishot_dpram0 : generic_dpram
generic map
(
g_data_width => 64,
g_size => g_multishot_ram_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_dual_clock => true
-- default values for the rest of the generics are okay
)
port map
(
rst_n_i => sys_rst_n_i,
clka_i => sys_clk_i,
bwea_i => open,
wea_i => dpram0_wea,
aa_i => dpram0_addra,
da_i => dpram0_dina,
qa_o => open,
clkb_i => sys_clk_i,
bweb_i => open,
ab_i => dpram0_addrb,
-- db_i => (others => '0'),
qb_o => dpram0_doutb
);
end process p_insert_trig_tag;
-- ###
cmp_multishot_dpram1 : generic_dpram
generic map
(
g_data_width => 64,
g_size => g_multishot_ram_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_dual_clock => false
-- default values for the rest of the generics are okay
)
port map
(
rst_n_i => sys_rst_n_i,
clka_i => sys_clk_i,
bwea_i => open,
wea_i => dpram1_wea,
aa_i => dpram1_addra,
da_i => dpram1_dina,
qa_o => open,
clkb_i => sys_clk_i,
bweb_i => open,
ab_i => dpram1_addrb,
-- db_i => (others => '0'),
qb_o => dpram1_doutb
);
------------------------------------------------------------------------------
-- Dual DPRAM buffers for multi-shots acquisition
------------------------------------------------------------------------------
-- DPRAM output address counter
p_dpram_addrb_cnt : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
dpram_addrb_cnt <= (others => '0');
dpram_valid_t <= '0';
dpram_valid <= '0';
elsif rising_edge(sys_clk_i) then
if post_trig_done = '1' then
dpram_addrb_cnt <= dpram_addra_trig - unsigned(pre_trig_value(c_dpram_depth-1 downto 0));
dpram_valid_t <= '1';
elsif (dpram_addrb_cnt = dpram_addra_post_done) then
dpram_valid_t <= '0';
else
dpram_addrb_cnt <= dpram_addrb_cnt + 1;
-- DPRAM input address counter
p_dpram_addra_cnt : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
dpram_addra_cnt <= (others => '0');
dpram_addra_trig <= (others => '0');
dpram_addra_post_done <= (others => '0');
elsif rising_edge(sys_clk_i) then
if shots_decr = '1' then
dpram_addra_cnt <= to_unsigned(0, dpram_addra_cnt'length);
elsif (samples_wr_en = '1' and sync_fifo_valid = '1') then
dpram_addra_cnt <= dpram_addra_cnt + 1;
end if;
if acq_trig = '1' then
dpram_addra_trig <= dpram_addra_cnt;
end if;
if post_trig_done = '1' then
if unsigned(post_trig_value) = to_unsigned(0, post_trig_value'length) then
dpram_addra_post_done <= dpram_addra_cnt - 1;
else
dpram_addra_post_done <= dpram_addra_cnt;
end if;
end if;
end if;
dpram_valid <= dpram_valid_t;
end if;
end process p_dpram_addrb_cnt;
-- DPRAM output mux
dpram_dout <= dpram0_doutb when multishot_buffer_sel = '1' else dpram1_doutb;
dpram0_addrb <= std_logic_vector(dpram_addrb_cnt);
dpram1_addrb <= std_logic_vector(dpram_addrb_cnt);
end process p_dpram_addra_cnt;
-- DPRAM inputs
dpram0_addra <= std_logic_vector(dpram_addra_cnt);
dpram1_addra <= std_logic_vector(dpram_addra_cnt);
dpram0_dina <= sync_fifo_dout(63 downto 0) when acq_in_trig_tag = '0' else trig_tag_data; -- ###
dpram1_dina <= sync_fifo_dout(63 downto 0) when acq_in_trig_tag = '0' else trig_tag_data; -- ###;
dpram0_wea <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '0' else '0'; -- ###
dpram1_wea <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '1' else '0'; -- ###
-- DPRAMs
cmp_multishot_dpram0 : generic_dpram
generic map
(
g_data_width => 64,
g_size => g_multishot_ram_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_dual_clock => true
-- default values for the rest of the generics are okay
)
port map
(
rst_n_i => sys_rst_n_i,
clka_i => sys_clk_i,
bwea_i => open,
wea_i => dpram0_wea,
aa_i => dpram0_addra,
da_i => dpram0_dina,
qa_o => open,
clkb_i => sys_clk_i,
bweb_i => open,
ab_i => dpram0_addrb,
-- db_i => (others => '0'),
qb_o => dpram0_doutb
);
------------------------------------------------------------------------------
-- Flow control FIFO for data to DDR
------------------------------------------------------------------------------
cmp_wb_ddr_fifo : generic_sync_fifo
generic map (
g_data_width => 65,
g_size => 64,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => false,
g_with_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0
)
port map(
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
d_i => wb_ddr_fifo_din,
we_i => wb_ddr_fifo_wr,
q_o => wb_ddr_fifo_dout,
rd_i => wb_ddr_fifo_rd,
empty_o => wb_ddr_fifo_empty,
full_o => wb_ddr_fifo_full,
almost_empty_o => open,
almost_full_o => open,
count_o => open
);
cmp_multishot_dpram1 : generic_dpram
generic map
(
g_data_width => 64,
g_size => g_multishot_ram_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_dual_clock => false
-- default values for the rest of the generics are okay
)
port map
(
rst_n_i => sys_rst_n_i,
clka_i => sys_clk_i,
bwea_i => open,
wea_i => dpram1_wea,
aa_i => dpram1_addra,
da_i => dpram1_dina,
qa_o => open,
clkb_i => sys_clk_i,
bweb_i => open,
ab_i => dpram1_addrb,
-- db_i => (others => '0'),
qb_o => dpram1_doutb
);
-- One clock cycle delay for the FIFO's VALID signal. Since the General Cores
-- package does not offer the possibility to use the FWFT feature of the FIFOs,
-- we simulate the valid flag here according to Figure 4-7 in ref. [1].
p_wb_ddr_fifo_valid : process (sys_clk_i) is
begin
if rising_edge(sys_clk_i) then
wb_ddr_fifo_valid <= wb_ddr_fifo_rd;
if (wb_ddr_fifo_empty = '1') then
wb_ddr_fifo_valid <= '0';
-- DPRAM output address counter
p_dpram_addrb_cnt : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
dpram_addrb_cnt <= (others => '0');
dpram_valid_t <= '0';
dpram_valid <= '0';
elsif rising_edge(sys_clk_i) then
if post_trig_done = '1' then
dpram_addrb_cnt <= dpram_addra_trig - unsigned(pre_trig_value(c_dpram_depth-1 downto 0));
dpram_valid_t <= '1';
elsif (dpram_addrb_cnt = dpram_addra_post_done) then
dpram_valid_t <= '0';
else
dpram_addrb_cnt <= dpram_addrb_cnt + 1;
end if;
dpram_valid <= dpram_valid_t;
end if;
end if;
end process;
end process p_dpram_addrb_cnt;
-- DPRAM output mux
dpram_dout <= dpram0_doutb when multishot_buffer_sel = '1' else dpram1_doutb;
dpram0_addrb <= std_logic_vector(dpram_addrb_cnt);
dpram1_addrb <= std_logic_vector(dpram_addrb_cnt);
------------------------------------------------------------------------------
-- Flow control FIFO for data to DDR
------------------------------------------------------------------------------
cmp_wb_ddr_fifo : generic_sync_fifo
generic map (
g_data_width => 65,
g_size => 64,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => false,
g_with_count => false,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0
)
port map(
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
d_i => wb_ddr_fifo_din,
we_i => wb_ddr_fifo_wr,
q_o => wb_ddr_fifo_dout,
rd_i => wb_ddr_fifo_rd,
empty_o => wb_ddr_fifo_empty,
full_o => wb_ddr_fifo_full,
almost_empty_o => open,
almost_full_o => open,
count_o => open
);
p_wb_ddr_fifo_input : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
wb_ddr_fifo_din <= (others => '0');
wb_ddr_fifo_wr_en <= '0';
elsif rising_edge(sys_clk_i) then
if single_shot = '1' then
wb_ddr_fifo_din <= acq_trig & sync_fifo_dout(63 downto 0); -- trigger + data
wb_ddr_fifo_wr_en <= samples_wr_en and sync_fifo_valid;
else
wb_ddr_fifo_din <= '0' & dpram_dout;
wb_ddr_fifo_wr_en <= dpram_valid;
-- One clock cycle delay for the FIFO's VALID signal. Since the General Cores
-- package does not offer the possibility to use the FWFT feature of the FIFOs,
-- we simulate the valid flag here according to Figure 4-7 in ref. [1].
p_wb_ddr_fifo_valid : process (sys_clk_i) is
begin
if rising_edge(sys_clk_i) then
wb_ddr_fifo_valid <= wb_ddr_fifo_rd;
if (wb_ddr_fifo_empty = '1') then
wb_ddr_fifo_valid <= '0';
end if;
end if;
end if;
end process p_wb_ddr_fifo_input;
--wb_ddr_fifo_din <= sync_fifo_dout(63 downto 0) when single_shot = '1' else dpram_dout;
--wb_ddr_fifo_wr_en <= samples_wr_en when single_shot = '1' else dpram_valid;
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and not(wb_ddr_fifo_full);
wb_ddr_fifo_rd <= wb_ddr_fifo_dreq and not(wb_ddr_fifo_empty) and not(wb_ddr_stall_t);
wb_ddr_fifo_dreq <= '1';
end process;
------------------------------------------------------------------------------
-- RAM address counter (32-bit word address)
------------------------------------------------------------------------------
p_ram_addr_cnt : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
ram_addr_cnt <= (others => '0');
elsif rising_edge(wb_ddr_clk_i) then
if acq_start = '1' then
p_wb_ddr_fifo_input : process (sys_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
wb_ddr_fifo_din <= (others => '0');
wb_ddr_fifo_wr_en <= '0';
elsif rising_edge(sys_clk_i) then
if single_shot = '1' then
if acq_in_trig_tag = '1' then
wb_ddr_fifo_din <= trig_tag_data; -- ###
wb_ddr_fifo_wr_en <= acq_in_trig_tag; -- ###
else
wb_ddr_fifo_din <= acq_trig & sync_fifo_dout(63 downto 0); -- trigger + data
wb_ddr_fifo_wr_en <= samples_wr_en and sync_fifo_valid;
end if;
else
wb_ddr_fifo_din <= '0' & dpram_dout;
wb_ddr_fifo_wr_en <= dpram_valid;
end if;
end if;
end process p_wb_ddr_fifo_input;
--wb_ddr_fifo_din <= sync_fifo_dout(63 downto 0) when single_shot = '1' else dpram_dout;
--wb_ddr_fifo_wr_en <= samples_wr_en when single_shot = '1' else dpram_valid;
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and not(wb_ddr_fifo_full);
wb_ddr_fifo_rd <= wb_ddr_fifo_dreq and not(wb_ddr_fifo_empty) and not(wb_ddr_stall_t);
wb_ddr_fifo_dreq <= '1';
------------------------------------------------------------------------------
-- RAM address counter (32-bit word address)
------------------------------------------------------------------------------
p_ram_addr_cnt : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
ram_addr_cnt <= (others => '0');
elsif wb_ddr_fifo_valid = '1' then
ram_addr_cnt <= ram_addr_cnt + 1;
elsif rising_edge(wb_ddr_clk_i) then
if acq_start = '1' then
ram_addr_cnt <= (others => '0');
elsif wb_ddr_fifo_valid = '1' then
ram_addr_cnt <= ram_addr_cnt + 1;
end if;
end if;
end if;
end process p_ram_addr_cnt;
end process p_ram_addr_cnt;
------------------------------------------------------------------------------
-- Store trigger DDR address
------------------------------------------------------------------------------
p_trig_addr : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
trig_addr <= (others => '0');
elsif rising_edge(wb_ddr_clk_i) then
if wb_ddr_fifo_dout(64) = '1' and wb_ddr_fifo_valid = '1' then
trig_addr <= "0000000" & std_logic_vector(ram_addr_cnt);
------------------------------------------------------------------------------
-- Store trigger DDR address
------------------------------------------------------------------------------
p_trig_addr : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
trig_addr <= (others => '0');
elsif rising_edge(wb_ddr_clk_i) then
if wb_ddr_fifo_dout(64) = '1' and wb_ddr_fifo_valid = '1' then
trig_addr <= "0000000" & std_logic_vector(ram_addr_cnt);
end if;
end if;
end if;
end process p_trig_addr;
end process p_trig_addr;
------------------------------------------------------------------------------
-- Wishbone master (to DDR)
------------------------------------------------------------------------------
p_wb_master : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
wb_ddr_stb_o <= '0';
wb_ddr_adr_o <= (others => '0');
wb_ddr_dat_o <= (others => '0');
wb_ddr_stall_t <= '0';
elsif rising_edge(wb_ddr_clk_i) then
if wb_ddr_fifo_valid = '1' then --if (wb_ddr_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
wb_ddr_stb_o <= '1';
wb_ddr_adr_o <= "0000000" & std_logic_vector(ram_addr_cnt);
if test_data_en = '1' then
wb_ddr_dat_o <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
------------------------------------------------------------------------------
-- Wishbone master (to DDR)
------------------------------------------------------------------------------
p_wb_master : process (wb_ddr_clk_i, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
wb_ddr_stb_o <= '0';
wb_ddr_adr_o <= (others => '0');
wb_ddr_dat_o <= (others => '0');
wb_ddr_stall_t <= '0';
elsif rising_edge(wb_ddr_clk_i) then
if wb_ddr_fifo_valid = '1' then --if (wb_ddr_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
wb_ddr_stb_o <= '1';
wb_ddr_adr_o <= "0000000" & std_logic_vector(ram_addr_cnt);
if test_data_en = '1' then
wb_ddr_dat_o <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
else
wb_ddr_dat_o <= wb_ddr_fifo_dout(63 downto 0);
end if;
else
wb_ddr_dat_o <= wb_ddr_fifo_dout(63 downto 0);
wb_ddr_stb_o <= '0';
end if;
else
wb_ddr_stb_o <= '0';
end if;
if wb_ddr_fifo_valid = '1' then
wb_ddr_cyc_o <= '1';
wb_ddr_we_o <= '1';
--elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
end if;
if wb_ddr_fifo_valid = '1' then
wb_ddr_cyc_o <= '1';
wb_ddr_we_o <= '1';
--elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
wb_ddr_cyc_o <= '0';
wb_ddr_we_o <= '0';
end if;
wb_ddr_stall_t <= wb_ddr_stall_i;
wb_ddr_stall_t <= wb_ddr_stall_i;
end if;
end process p_wb_master;
end if;
end process p_wb_master;
wb_ddr_sel_o <= X"FF";
wb_ddr_sel_o <= X"FF";
end rtl;
end rtl;
hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @ b48832a9
......@@ -37,6 +37,8 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
package fmc_adc_100Ms_core_pkg is
......@@ -51,7 +53,7 @@ package fmc_adc_100Ms_core_pkg is
component fmc_adc_100Ms_core
generic(
g_multishot_ram_size : natural := 2048;
g_carrier_type : string := "SPEC"
g_carrier_type : string := "SPEC"
);
port (
-- Clock, reset
......@@ -85,6 +87,9 @@ package fmc_adc_100Ms_core_pkg is
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
......
hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @ b48832a9
......@@ -43,12 +43,13 @@ use IEEE.NUMERIC_STD.all;
library work;
use work.fmc_adc_100Ms_core_pkg.all;
use work.wishbone_pkg.all;
use work.timetag_core_pkg.all;
entity fmc_adc_mezzanine is
generic(
g_multishot_ram_size : natural := 2048;
g_carrier_type : string := "SPEC"
g_carrier_type : string := "SPEC"
);
port (
-- Clock, reset
......@@ -83,6 +84,9 @@ entity fmc_adc_mezzanine is
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
......@@ -213,8 +217,8 @@ architecture rtl of fmc_adc_mezzanine is
signal si570_sda_oe_n : std_logic;
-- Mezzanine 1-wire
signal mezz_owr_en : std_logic_vector(0 downto 0);
signal mezz_owr_i : std_logic_vector(0 downto 0);
signal mezz_owr_en : std_logic_vector(0 downto 0);
signal mezz_owr_i : std_logic_vector(0 downto 0);
begin
......@@ -369,7 +373,7 @@ begin
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
generic map (
g_multishot_ram_size => g_multishot_ram_size,
g_carrier_type => g_carrier_type
g_carrier_type => g_carrier_type
)
port map(
sys_clk_i => sys_clk_i,
......@@ -399,6 +403,8 @@ begin
acq_stop_p_o => acq_stop_p_o,
acq_end_p_o => acq_end_p_o,
trigger_tag_i => trigger_tag_i,
ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i,
......
hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ b48832a9
......@@ -37,6 +37,8 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
package fmc_adc_mezzanine_pkg is
......@@ -86,6 +88,9 @@ package fmc_adc_mezzanine_pkg is
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
......
hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
View file @ b48832a9
......@@ -38,7 +38,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.timetag_core_pkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
......@@ -56,6 +56,9 @@ entity timetag_core is
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
-- Trigger time-tag output
trig_tag_o : out t_timetag;
-- Wishbone interface
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
......@@ -116,30 +119,18 @@ architecture rtl of timetag_core is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal timetag_seconds : std_logic_vector(31 downto 0);
signal timetag_seconds_cnt : unsigned(31 downto 0);
signal timetag_seconds_load_value : std_logic_vector(31 downto 0);
signal timetag_seconds_load_en : std_logic;
signal timetag_coarse : std_logic_vector(31 downto 0);
signal timetag_coarse_cnt : unsigned(31 downto 0);
signal timetag_coarse_load_value : std_logic_vector(31 downto 0);
signal timetag_coarse_load_en : std_logic;
signal timetag_trig_tag_meta : std_logic_vector(31 downto 0);
signal timetag_trig_tag_seconds : std_logic_vector(31 downto 0);
signal timetag_trig_tag_coarse : std_logic_vector(31 downto 0);
signal timetag_trig_tag_fine : std_logic_vector(31 downto 0);
signal timetag_acq_start_tag_meta : std_logic_vector(31 downto 0);
signal timetag_acq_start_tag_seconds : std_logic_vector(31 downto 0);
signal timetag_acq_start_tag_coarse : std_logic_vector(31 downto 0);
signal timetag_acq_start_tag_fine : std_logic_vector(31 downto 0);
signal timetag_acq_stop_tag_meta : std_logic_vector(31 downto 0);
signal timetag_acq_stop_tag_seconds : std_logic_vector(31 downto 0);
signal timetag_acq_stop_tag_coarse : std_logic_vector(31 downto 0);
signal timetag_acq_stop_tag_fine : std_logic_vector(31 downto 0);
signal timetag_acq_end_tag_meta : std_logic_vector(31 downto 0);
signal timetag_acq_end_tag_seconds : std_logic_vector(31 downto 0);
signal timetag_acq_end_tag_coarse : std_logic_vector(31 downto 0);
signal timetag_acq_end_tag_fine : std_logic_vector(31 downto 0);
signal timetag_seconds : std_logic_vector(31 downto 0);
signal timetag_seconds_cnt : unsigned(31 downto 0);
signal timetag_seconds_load_value : std_logic_vector(31 downto 0);
signal timetag_seconds_load_en : std_logic;
signal timetag_coarse : std_logic_vector(31 downto 0);
signal timetag_coarse_cnt : unsigned(31 downto 0);
signal timetag_coarse_load_value : std_logic_vector(31 downto 0);
signal timetag_coarse_load_en : std_logic;
signal trig_tag : t_timetag;
signal acq_start_tag : t_timetag;
signal acq_stop_tag : t_timetag;
signal acq_end_tag : t_timetag;
signal local_pps : std_logic;
......@@ -169,22 +160,22 @@ begin
timetag_core_coarse_o => timetag_coarse_load_value,
timetag_core_coarse_i => timetag_coarse,
timetag_core_coarse_load_o => timetag_coarse_load_en,
timetag_core_trig_tag_meta_i => timetag_trig_tag_meta,
timetag_core_trig_tag_seconds_i => timetag_trig_tag_seconds,
timetag_core_trig_tag_coarse_i => timetag_trig_tag_coarse,
timetag_core_trig_tag_fine_i => timetag_trig_tag_fine,
timetag_core_acq_start_tag_meta_i => timetag_acq_start_tag_meta,
timetag_core_acq_start_tag_seconds_i => timetag_acq_start_tag_seconds,
timetag_core_acq_start_tag_coarse_i => timetag_acq_start_tag_coarse,
timetag_core_acq_start_tag_fine_i => timetag_acq_start_tag_fine,
timetag_core_acq_stop_tag_meta_i => timetag_acq_stop_tag_meta,
timetag_core_acq_stop_tag_seconds_i => timetag_acq_stop_tag_seconds,
timetag_core_acq_stop_tag_coarse_i => timetag_acq_stop_tag_coarse,
timetag_core_acq_stop_tag_fine_i => timetag_acq_stop_tag_fine,
timetag_core_acq_end_tag_meta_i => timetag_acq_end_tag_meta,
timetag_core_acq_end_tag_seconds_i => timetag_acq_end_tag_seconds,
timetag_core_acq_end_tag_coarse_i => timetag_acq_end_tag_coarse,
timetag_core_acq_end_tag_fine_i => timetag_acq_end_tag_fine
timetag_core_trig_tag_meta_i => trig_tag.meta,
timetag_core_trig_tag_seconds_i => trig_tag.seconds,
timetag_core_trig_tag_coarse_i => trig_tag.coarse,
timetag_core_trig_tag_fine_i => trig_tag.fine,
timetag_core_acq_start_tag_meta_i => acq_start_tag.meta,
timetag_core_acq_start_tag_seconds_i => acq_start_tag.seconds,
timetag_core_acq_start_tag_coarse_i => acq_start_tag.coarse,
timetag_core_acq_start_tag_fine_i => acq_start_tag.fine,
timetag_core_acq_stop_tag_meta_i => acq_stop_tag.meta,
timetag_core_acq_stop_tag_seconds_i => acq_stop_tag.seconds,
timetag_core_acq_stop_tag_coarse_i => acq_stop_tag.coarse,
timetag_core_acq_stop_tag_fine_i => acq_stop_tag.fine,
timetag_core_acq_end_tag_meta_i => acq_end_tag.meta,
timetag_core_acq_end_tag_seconds_i => acq_end_tag.seconds,
timetag_core_acq_end_tag_coarse_i => acq_end_tag.coarse,
timetag_core_acq_end_tag_fine_i => acq_end_tag.fine
);
------------------------------------------------------------------------------
......@@ -236,17 +227,18 @@ begin
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
timetag_trig_tag_seconds <= (others => '0');
timetag_trig_tag_coarse <= (others => '0');
timetag_trig_tag_fine <= (others => '0');
trig_tag.seconds <= (others => '0');
trig_tag.coarse <= (others => '0');
trig_tag.fine <= (others => '0');
elsif trigger_p_i = '1' then
timetag_trig_tag_seconds <= timetag_seconds;
timetag_trig_tag_coarse <= timetag_coarse;
trig_tag.seconds <= timetag_seconds;
trig_tag.coarse <= timetag_coarse;
end if;
end if;
end process p_trig_tag;
timetag_trig_tag_meta <= X"00000000";
trig_tag.meta <= X"00000000";
trig_tag_o <= trig_tag;
------------------------------------------------------------------------------
-- Last acquisition start event time-tag
......@@ -255,17 +247,17 @@ begin
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
timetag_acq_start_tag_seconds <= (others => '0');
timetag_acq_start_tag_coarse <= (others => '0');
timetag_acq_start_tag_fine <= (others => '0');
acq_start_tag.seconds <= (others => '0');
acq_start_tag.coarse <= (others => '0');
acq_start_tag.fine <= (others => '0');
elsif acq_start_p_i = '1' then
timetag_acq_start_tag_seconds <= timetag_seconds;
timetag_acq_start_tag_coarse <= timetag_coarse;
acq_start_tag.seconds <= timetag_seconds;
acq_start_tag.coarse <= timetag_coarse;
end if;
end if;
end process p_acq_start_tag;
timetag_acq_start_tag_meta <= X"00000000";
acq_start_tag.meta <= X"00000000";
------------------------------------------------------------------------------
-- Last acquisition stop event time-tag
......@@ -274,17 +266,17 @@ begin
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
timetag_acq_stop_tag_seconds <= (others => '0');
timetag_acq_stop_tag_coarse <= (others => '0');
timetag_acq_stop_tag_fine <= (others => '0');
acq_stop_tag.seconds <= (others => '0');
acq_stop_tag.coarse <= (others => '0');
acq_stop_tag.fine <= (others => '0');
elsif acq_stop_p_i = '1' then
timetag_acq_stop_tag_seconds <= timetag_seconds;
timetag_acq_stop_tag_coarse <= timetag_coarse;
acq_stop_tag.seconds <= timetag_seconds;
acq_stop_tag.coarse <= timetag_coarse;
end if;
end if;
end process p_acq_stop_tag;
timetag_acq_stop_tag_meta <= X"00000000";
acq_stop_tag.meta <= X"00000000";
------------------------------------------------------------------------------
-- Last acquisition end event time-tag
......@@ -293,17 +285,17 @@ begin
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
timetag_acq_end_tag_seconds <= (others => '0');
timetag_acq_end_tag_coarse <= (others => '0');
timetag_acq_end_tag_fine <= (others => '0');
acq_end_tag.seconds <= (others => '0');
acq_end_tag.coarse <= (others => '0');
acq_end_tag.fine <= (others => '0');
elsif acq_end_p_i = '1' then
timetag_acq_end_tag_seconds <= timetag_seconds;
timetag_acq_end_tag_coarse <= timetag_coarse;
acq_end_tag.seconds <= timetag_seconds;
acq_end_tag.coarse <= timetag_coarse;
end if;
end if;
end process p_acq_end_tag;
timetag_acq_end_tag_meta <= X"00000000";
acq_end_tag.meta <= X"00000000";
end rtl;
hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
View file @ b48832a9
......@@ -44,6 +44,15 @@ package timetag_core_pkg is
-- Constants declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Types declaration
------------------------------------------------------------------------------
type t_timetag is record
meta : std_logic_vector(31 downto 0);
seconds : std_logic_vector(31 downto 0);
coarse : std_logic_vector(31 downto 0);
fine : std_logic_vector(31 downto 0);
end record t_timetag;
------------------------------------------------------------------------------
-- Components declaration
......@@ -60,6 +69,9 @@ package timetag_core_pkg is
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
-- Trigger time-tag output
trig_tag_o : out t_timetag;
-- Wishbone interface
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ b48832a9
......@@ -489,6 +489,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal acq_start_p : std_logic;
signal acq_stop_p : std_logic;
signal acq_end_p : std_logic;
signal trigger_tag : t_timetag;
-- led pwm
signal led_pwm_update_cnt : unsigned(9 downto 0);
......@@ -795,6 +796,8 @@ begin
acq_stop_p_i => acq_stop_p,
acq_end_p_i => acq_end_p,
trig_tag_o => trigger_tag,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TIMETAG).dat,
......@@ -949,6 +952,8 @@ begin
acq_stop_p_o => acq_stop_p,
acq_end_p_o => acq_end_p,
trigger_tag_i => trigger_tag,
ext_trigger_p_i => adc0_ext_trigger_p_i,
ext_trigger_n_i => adc0_ext_trigger_n_i,
......
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