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FMC ADC 100M 14b 4cha - Gateware
Commit bfce7558 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl/testbench: corrected and expanded new system verilog testbench for SPEC. Tested, works

parent cdaafa33
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.gitignore
View file @ bfce7558
......@@ -5,6 +5,12 @@ hdl/*/sim/vsim.wlf
hdl/*/sim/Makefile
hdl/*/sim/modelsim.ini
hdl/*/sim/work/
hdl/*/testbench/top/transcript
hdl/*/testbench/top/vsim.wlf
hdl/*/testbench/top/Makefile
hdl/*/testbench/top/modelsim.ini
hdl/*/testbench/top/work/
hdl/*/testbench/top/NullFile
hdl/*/sim/fifo_generator_v6_1/
hdl/*/syn/_ngo/
hdl/*/syn/_xmsgs/
......@@ -56,13 +62,13 @@ hdl/*/syn/*_summary.html
hdl/*/release/
hdl/*/chipscope/*.vcd
hdl/*/chipscope/*.wlf
hdl/svec/sim/testbench/fifo_generator_v6_1/
hdl/svec/sim/testbench/modelsim.ini
hdl/svec/sim/testbench/simdrv_defs.svh
hdl/svec/sim/testbench/transcript
hdl/svec/sim/testbench/vsim.wlf
hdl/svec/sim/testbench/vsim_stacktrace.vstf
hdl/svec/sim/testbench/work/
hdl/svec/sim/testbench/top/fifo_generator_v6_1/
hdl/svec/sim/testbench/top/modelsim.ini
hdl/svec/sim/testbench/top/simdrv_defs.svh
hdl/svec/sim/testbench/top/transcript
hdl/svec/sim/testbench/top/vsim.wlf
hdl/svec/sim/testbench/top/vsim_stacktrace.vstf
hdl/svec/sim/testbench/top/work/
doc/manual/*.html
*.texi
*.aux
......
hdl/spec/testbench/top/Manifest.py
View file @ bfce7558
......@@ -6,10 +6,20 @@ fetchto = "../../ip_cores"
syn_device="xc6slx45t"
include_dirs=["../include","gn4124_bfm", "ddr3"]
files = [ "main.sv","ddr3/ddr3.v" ]
files = [
"main.sv",
"ddr3/ddr3.v",
"../../../ip_cores/adc_serdes.vhd",
"../../../ip_cores/monostable/monostable_rtl.vhd",
"../../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd",
"../../../ip_cores/utils/utils_pkg.vhd"]
modules = { "local" : [ "../../rtl", "gn4124_bfm", "../../../adc/rtl", "../../../ip_cores/timetag_core/rtl",
"../../../ip_cores/general-cores", "../../../ip_cores/ddr3-sp6-core",
modules = { "local" : [ "../../rtl",
"gn4124_bfm",
"../../../adc/rtl",
"../../../ip_cores/timetag_core/rtl",
"../../../ip_cores/general-cores",
"../../../ip_cores/ddr3-sp6-core",
"../../../ip_cores/gn4124-core" ]};
ctrls = ["bank3_64b_32b" ]
hdl/spec/testbench/top/ddr3/ddr3.v
View file @ bfce7558
......@@ -80,6 +80,7 @@
// model flags
// `define MODEL_PASR
`define sg15
module ddr3 (
rst_n,
......
hdl/spec/testbench/top/ddr3/ddr3_parameters.vh
View file @ bfce7558
......@@ -559,7 +559,8 @@
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
`else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
......
hdl/spec/testbench/top/gn4124_bfm/gn4124_bfm.svh
View file @ bfce7558
......@@ -229,29 +229,29 @@ endinterface
/* Helper macro for wiring Gennum-Xilinx ports in spec_top */
`define GENNUM_WIRE_SPEC_PINS(IF_NAME) \
.L_RST_N (IF_NAME.SYS.rst_n),\
.L_CLKp (IF_NAME.SYS.lclk_p),\
.L_CLKn (IF_NAME.SYS.lclk_n),\
.p2l_clkp (IF_NAME.P2L.p2l_clk_p),\
.p2l_clkn (IF_NAME.P2L.p2l_clk_n),\
.p2l_data (IF_NAME.P2L.p2l_data),\
.p2l_dframe (IF_NAME.P2L.p2l_dframe),\
.p2l_valid (IF_NAME.P2L.p2l_valid),\
.p2l_rdy (IF_NAME.P2L.p2l_rdy),\
.p_wr_req (IF_NAME.P2L.p_wr_req),\
.p_wr_rdy (IF_NAME.P2L.p_wr_rdy),\
.rx_error (IF_NAME.P2L.rx_error),\
.l2p_clkp (IF_NAME.L2P.l2p_clk_p),\
.l2p_clkn (IF_NAME.L2P.l2p_clk_n),\
.l2p_data (IF_NAME.L2P.l2p_data),\
.l2p_dframe (IF_NAME.L2P.l2p_dframe),\
.l2p_valid (IF_NAME.L2P.l2p_valid),\
.l2p_edb (IF_NAME.L2P.l2p_edb),\
.l2p_rdy (IF_NAME.L2P.l2p_rdy),\
.l_wr_rdy (IF_NAME.L2P.l_wr_rdy),\
.p_rd_d_rdy (IF_NAME.L2P.p_rd_d_rdy),\
.tx_error (IF_NAME.L2P.tx_error),\
.vc_rdy (IF_NAME.P2L.vc_rdy)
.L_RST_N (IF_NAME.rst_n),\
.L_CLKp (IF_NAME.lclk_p),\
.L_CLKn (IF_NAME.lclk_n),\
.p2l_clkp (IF_NAME.p2l_clk_p),\
.p2l_clkn (IF_NAME.p2l_clk_n),\
.p2l_data (IF_NAME.p2l_data),\
.p2l_dframe (IF_NAME.p2l_dframe),\
.p2l_valid (IF_NAME.p2l_valid),\
.p2l_rdy (IF_NAME.p2l_rdy),\
.p_wr_req (IF_NAME.p_wr_req),\
.p_wr_rdy (IF_NAME.p_wr_rdy),\
.rx_error (IF_NAME.rx_error),\
.l2p_clkp (IF_NAME.l2p_clk_p),\
.l2p_clkn (IF_NAME.l2p_clk_n),\
.l2p_data (IF_NAME.l2p_data),\
.l2p_dframe (IF_NAME.l2p_dframe),\
.l2p_valid (IF_NAME.l2p_valid),\
.l2p_edb (IF_NAME.l2p_edb),\
.l2p_rdy (IF_NAME.l2p_rdy),\
.l_wr_rdy (IF_NAME.l_wr_rdy),\
.p_rd_d_rdy (IF_NAME.p_rd_d_rdy),\
.tx_error (IF_NAME.tx_error),\
.vc_rdy (IF_NAME.vc_rdy)
`endif // `ifndef __GN4124_BFM_SVH
hdl/spec/testbench/top/gn4124_bfm/gn412x_bfm.vhd
View file @ bfce7558
......@@ -911,8 +911,8 @@ CMD <= f_cmd_to_string(CMD_INT);
--
--#########################################################################--
process
--file OUT_FILE : text is out "STD_OUTPUT";
file OUT_FILE : text open write_mode is "NullFile";
file OUT_FILE : text is out "STD_OUTPUT";
--file OUT_FILE : text open write_mode is "NullFile";
variable OUTPUT_LINE : line;
variable ERR_CNT : integer;
variable L_CMD : string(1 to 80);
......@@ -2231,8 +2231,8 @@ writeline(OUT_FILE, OUTPUT_LINE);
--
--#########################################################################--
process
--file OUT_FILE : text is out "STD_OUTPUT";
file OUT_FILE : text open write_mode is "NullFile";
file OUT_FILE : text is out "STD_OUTPUT";
--file OUT_FILE : text open write_mode is "NullFile";
variable OUTPUT_LINE : line;
variable HEADER_TC : std_ulogic_vector(2 downto 0);
......@@ -2675,7 +2675,8 @@ writeline(OUT_FILE, OUTPUT_LINE);
end process;
process
file OUT_FILE : text open write_mode is "NullFile";
file OUT_FILE : text is out "STD_OUTPUT";
--file OUT_FILE : text open write_mode is "NullFile";
variable OUTPUT_LINE : line;
variable vHEADER : std_ulogic_vector(31 downto 0);
variable vADDRESS : std_ulogic_vector(63 downto 0);
......@@ -2801,7 +2802,8 @@ writeline(OUT_FILE, OUTPUT_LINE);
--
--#########################################################################--
process
file OUT_FILE : text open write_mode is "NullFile";
file OUT_FILE : text is out "STD_OUTPUT";
--file OUT_FILE : text open write_mode is "NullFile";
variable OUTPUT_LINE : line;
variable vHEADER : std_ulogic_vector(31 downto 0);
variable vADDRESS : std_ulogic_vector(63 downto 0);
......
hdl/spec/testbench/top/main.sv
View file @ bfce7558
......@@ -7,19 +7,15 @@
module main;
reg clk_125m_pllref = 0;
reg clk_20m_vcxo = 0;
reg clk_ext = 0;
reg rst_n = 0;
reg adc0_dco = 0;
reg adc0_fr = 0;
always #5ns adc0_dco <= ~adc0_dco;
always #50ns clk_ext <= ~clk_ext;
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
always #20ns clk_20m_vcxo <= ~clk_20m_vcxo;
always #1.25ns adc0_dco <= ~adc0_dco;
always #25ns clk_20m_vcxo <= ~clk_20m_vcxo;
IGN4124PCIMaster I_Gennum ();
......@@ -70,8 +66,8 @@ module main;
);
ddr3 #(
.DEBUG(1)
) mem (
.DEBUG(1)
) mem (
.rst_n(ddr_reset_n),
.ck(ddr_ck_p),
.ck_n(ddr_ck_n),
......@@ -88,18 +84,17 @@ module main;
.dqs_n({ddr_udqs_n, ddr_ldqs_n}),
.tdqs_n(),
.odt(ddr_odt)
);
);
int adc_div = 0;
always@(posedge adc0_dco)
if(adc_div==3)
begin
adc0_fr <= 1;
if(adc_div==1) begin
adc0_fr <= ~adc0_fr;
adc_div <= 0;
end else begin
adc0_fr <= 0;
end
else begin
adc_div <= adc_div + 1;
end
......@@ -108,39 +103,75 @@ module main;
initial begin
CBusAccessor acc;
uint64_t rv;
uint64_t val;
@(posedge I_Gennum.ready);
acc = I_Gennum.get_accessor();
#40us;
acc.set_default_xfer_size(4);
acc.read(0, rv);
@(posedge DUT.sys_clk_pll_locked);
$display("ID: %x", rv);
#5us;
acc.write('h100c,'h1000); // host addr
acc.write('h1010,0);
acc.read(0, val);
$display("ID: %x", val);
acc.write('h1014,'h1000); // len
acc.write('h1018, 0); // next
acc.write('h101c,0);
acc.read('h3304, val); // status
$display("STATUS: %x", val);
acc.write('h1008,'h0);
acc.write('h1020,'h0); // attrib: pcie -> host
acc.write('h1000,'h1); // xfer start
acc.write('h3308, 'h00000008); // trigger cfg: enable sw trigger
acc.write('h3328, 'h00000000); // #pre-samples
acc.write('h332C, 'h00000010); // #post-samples
acc.write('h3314, 'h00000001); // #nshots: single-shot acq
acc.read('h3304, val); // status
$display("STATUS: %x", val);
acc.write('h3300, 'h00000001); // FSM start
#1us;
acc.write('h3310, 'hFFFFFFFF); // soft trigger
#2us;
end
acc.write('h3314, 'h00000003); // #nshots: 3x multi-shot acq
acc.write('h3300, 'h00000001); // FSM start
endmodule // main
#1us;
acc.write('h3310, 'hFFFFFFFE); // soft trigger
#1us;
acc.write('h3310, 'hFFFFFFFD); // soft trigger
#1us;
acc.write('h3310, 'hFFFFFFFC); // soft trigger
#2us;
// DMA transfer
acc.write('h100C, 'h00001000); // host addr
acc.write('h1010, 'h00000000);
acc.write('h1014, 'h00001000); // len
acc.write('h1018, 'h00000000); // next
acc.write('h101C, 'h00000000);
acc.write('h1008, 'h00000000);
acc.write('h1020, 'h00000000); // attrib: pcie -> host
acc.write('h1000, 'h00000001); // xfer start
end
endmodule // main
hdl/spec/testbench/top/run.do
View file @ bfce7558
......@@ -3,6 +3,6 @@ set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 100us
run 50us
wave zoomfull
radix -hexadecimal
hdl/spec/testbench/top/wave.do
View file @ bfce7558
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