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FMC ADC 100M 14b 4cha - Gateware
Commit c41460ea authored by Matthieu Cattin's avatar Matthieu Cattin
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dbg: Adding some chipscope projects used to debug hdl.

parent c49479e0
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hdl/spec/chipscope/end_acq_irq_bug.cdc 0 → 100644
View file @ c41460ea
#ChipScope Core Inserter Project File Version 3.0
#Thu Mar 28 10:47:52 CET 2013
Project.device.designInputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.designOutputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=*acq_end_rst*
Project.filter<10>=*post_trig_*
Project.filter<11>=*post_trig_value*
Project.filter<12>=*post_trig*
Project.filter<13>=*acq_in_post*
Project.filter<14>=*acq_start*
Project.filter<15>=*shots*
Project.filter<16>=*post_trig_cnt*
Project.filter<17>=*sync_fifo*
Project.filter<18>=*ddr*count*
Project.filter<1>=*byte*
Project.filter<2>=*wr_coun*
Project.filter<3>=*ddr_cmd*
Project.filter<4>=*acq*
Project.filter<5>=*p0_wr*
Project.filter<6>=*wr_fifo_*
Project.filter<7>=*underrun*
Project.filter<8>=*error*
Project.filter<9>=*post_samples*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=sys_clk_125
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataDepth=8192
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=101
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=ddr_wr_fifo_empty
Project.unit<0>.triggerChannel<0><100>=
Project.unit<0>.triggerChannel<0><101>=
Project.unit<0>.triggerChannel<0><102>=
Project.unit<0>.triggerChannel<0><103>=
Project.unit<0>.triggerChannel<0><104>=
Project.unit<0>.triggerChannel<0><105>=
Project.unit<0>.triggerChannel<0><106>=
Project.unit<0>.triggerChannel<0><107>=
Project.unit<0>.triggerChannel<0><108>=
Project.unit<0>.triggerChannel<0><109>=
Project.unit<0>.triggerChannel<0><10>=cmp_fmc_adc_100Ms_core/wb_ddr_stall_t
Project.unit<0>.triggerChannel<0><110>=
Project.unit<0>.triggerChannel<0><111>=
Project.unit<0>.triggerChannel<0><112>=
Project.unit<0>.triggerChannel<0><113>=
Project.unit<0>.triggerChannel<0><114>=
Project.unit<0>.triggerChannel<0><115>=
Project.unit<0>.triggerChannel<0><116>=
Project.unit<0>.triggerChannel<0><117>=
Project.unit<0>.triggerChannel<0><118>=
Project.unit<0>.triggerChannel<0><119>=
Project.unit<0>.triggerChannel<0><11>=cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
Project.unit<0>.triggerChannel<0><120>=
Project.unit<0>.triggerChannel<0><121>=
Project.unit<0>.triggerChannel<0><122>=
Project.unit<0>.triggerChannel<0><123>=
Project.unit<0>.triggerChannel<0><124>=
Project.unit<0>.triggerChannel<0><125>=
Project.unit<0>.triggerChannel<0><126>=
Project.unit<0>.triggerChannel<0><127>=
Project.unit<0>.triggerChannel<0><128>=
Project.unit<0>.triggerChannel<0><129>=
Project.unit<0>.triggerChannel<0><12>=cmp_fmc_adc_100Ms_core/cmp_wb_ddr_fifo/wrapped_gen/grf.rf/gl0.rd/grss.rsts/ram_empty_i
Project.unit<0>.triggerChannel<0><130>=
Project.unit<0>.triggerChannel<0><131>=
Project.unit<0>.triggerChannel<0><132>=
Project.unit<0>.triggerChannel<0><133>=
Project.unit<0>.triggerChannel<0><134>=
Project.unit<0>.triggerChannel<0><135>=
Project.unit<0>.triggerChannel<0><136>=
Project.unit<0>.triggerChannel<0><137>=
Project.unit<0>.triggerChannel<0><138>=
Project.unit<0>.triggerChannel<0><139>=
Project.unit<0>.triggerChannel<0><13>=cmp_fmc_adc_100Ms_core/cmp_wb_ddr_fifo/wrapped_gen/grf.rf/gl0.wr/gwss.wsts/ram_full_i
Project.unit<0>.triggerChannel<0><140>=
Project.unit<0>.triggerChannel<0><141>=
Project.unit<0>.triggerChannel<0><142>=
Project.unit<0>.triggerChannel<0><143>=
Project.unit<0>.triggerChannel<0><144>=
Project.unit<0>.triggerChannel<0><145>=
Project.unit<0>.triggerChannel<0><146>=
Project.unit<0>.triggerChannel<0><147>=
Project.unit<0>.triggerChannel<0><148>=
Project.unit<0>.triggerChannel<0><149>=
Project.unit<0>.triggerChannel<0><14>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<0>
Project.unit<0>.triggerChannel<0><15>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<1>
Project.unit<0>.triggerChannel<0><16>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<2>
Project.unit<0>.triggerChannel<0><17>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<3>
Project.unit<0>.triggerChannel<0><18>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<4>
Project.unit<0>.triggerChannel<0><19>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<5>
Project.unit<0>.triggerChannel<0><1>=acq_end
Project.unit<0>.triggerChannel<0><20>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<6>
Project.unit<0>.triggerChannel<0><21>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<7>
Project.unit<0>.triggerChannel<0><22>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<8>
Project.unit<0>.triggerChannel<0><23>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<9>
Project.unit<0>.triggerChannel<0><24>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<10>
Project.unit<0>.triggerChannel<0><25>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<11>
Project.unit<0>.triggerChannel<0><26>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<12>
Project.unit<0>.triggerChannel<0><27>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<13>
Project.unit<0>.triggerChannel<0><28>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<14>
Project.unit<0>.triggerChannel<0><29>=cmp_fmc_adc_100Ms_core/wb_ddr_adr_o<15>
Project.unit<0>.triggerChannel<0><2>=acq_end_irq_p
Project.unit<0>.triggerChannel<0><30>=cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd1
Project.unit<0>.triggerChannel<0><31>=cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd2
Project.unit<0>.triggerChannel<0><32>=cmp_fmc_adc_100Ms_core/acq_fsm_current_state_FSM_FFd3
Project.unit<0>.triggerChannel<0><33>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt<0>
Project.unit<0>.triggerChannel<0><34>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt<1>
Project.unit<0>.triggerChannel<0><35>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt<2>
Project.unit<0>.triggerChannel<0><36>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt<3>
Project.unit<0>.triggerChannel<0><37>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt<4>
Project.unit<0>.triggerChannel<0><38>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt<5>
Project.unit<0>.triggerChannel<0><39>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_en
Project.unit<0>.triggerChannel<0><3>=cmp_irq_controller/irq_p_o
Project.unit<0>.triggerChannel<0><40>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_en
Project.unit<0>.triggerChannel<0><41>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stall_o
Project.unit<0>.triggerChannel<0><42>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_stb_d
Project.unit<0>.triggerChannel<0><43>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/wb_we_d
Project.unit<0>.triggerChannel<0><44>=cmp_ddr_ctrl/p0_rd_full
Project.unit<0>.triggerChannel<0><45>=cmp_ddr_ctrl/p0_wr_full
Project.unit<0>.triggerChannel<0><46>=cmp_ddr_ctrl/p0_cmd_full
Project.unit<0>.triggerChannel<0><47>=cmp_ddr_ctrl/p0_rd_empty
Project.unit<0>.triggerChannel<0><48>=cmp_fmc_adc_100Ms_core/sync_fifo_valid
Project.unit<0>.triggerChannel<0><49>=cmp_fmc_adc_100Ms_core/post_trig_cnt<0>
Project.unit<0>.triggerChannel<0><4>=dma_irq<0>
Project.unit<0>.triggerChannel<0><50>=cmp_fmc_adc_100Ms_core/post_trig_cnt<1>
Project.unit<0>.triggerChannel<0><51>=cmp_fmc_adc_100Ms_core/post_trig_cnt<2>
Project.unit<0>.triggerChannel<0><52>=cmp_fmc_adc_100Ms_core/post_trig_cnt<3>
Project.unit<0>.triggerChannel<0><53>=cmp_fmc_adc_100Ms_core/post_trig_cnt<4>
Project.unit<0>.triggerChannel<0><54>=cmp_fmc_adc_100Ms_core/post_trig_cnt<5>
Project.unit<0>.triggerChannel<0><55>=cmp_fmc_adc_100Ms_core/post_trig_cnt<6>
Project.unit<0>.triggerChannel<0><56>=cmp_fmc_adc_100Ms_core/post_trig_cnt<7>
Project.unit<0>.triggerChannel<0><57>=cmp_fmc_adc_100Ms_core/post_trig_cnt<8>
Project.unit<0>.triggerChannel<0><58>=cmp_fmc_adc_100Ms_core/post_trig_cnt<9>
Project.unit<0>.triggerChannel<0><59>=cmp_fmc_adc_100Ms_core/shots_done
Project.unit<0>.triggerChannel<0><5>=dma_irq<1>
Project.unit<0>.triggerChannel<0><60>=cmp_fmc_adc_100Ms_core/shots_cnt<0>
Project.unit<0>.triggerChannel<0><61>=cmp_fmc_adc_100Ms_core/shots_cnt<1>
Project.unit<0>.triggerChannel<0><62>=acq_start_p
Project.unit<0>.triggerChannel<0><63>=ddr_wr_fifo_empty_d
Project.unit<0>.triggerChannel<0><64>=acq_stop_p
Project.unit<0>.triggerChannel<0><65>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl<0>
Project.unit<0>.triggerChannel<0><66>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl<1>
Project.unit<0>.triggerChannel<0><67>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl<2>
Project.unit<0>.triggerChannel<0><68>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl<3>
Project.unit<0>.triggerChannel<0><69>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl<4>
Project.unit<0>.triggerChannel<0><6>=trigger_p
Project.unit<0>.triggerChannel<0><70>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl<5>
Project.unit<0>.triggerChannel<0><71>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr
Project.unit<0>.triggerChannel<0><72>=cmp_ddr_ctrl/p0_wr_count<1>
Project.unit<0>.triggerChannel<0><73>=cmp_ddr_ctrl/p0_wr_count<2>
Project.unit<0>.triggerChannel<0><74>=cmp_ddr_ctrl/p0_wr_count<3>
Project.unit<0>.triggerChannel<0><75>=cmp_ddr_ctrl/p0_wr_count<4>
Project.unit<0>.triggerChannel<0><76>=cmp_ddr_ctrl/p0_wr_count<5>
Project.unit<0>.triggerChannel<0><77>=cmp_ddr_ctrl/p0_wr_count<6>
Project.unit<0>.triggerChannel<0><78>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<3>
Project.unit<0>.triggerChannel<0><79>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<4>
Project.unit<0>.triggerChannel<0><7>=cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
Project.unit<0>.triggerChannel<0><80>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<5>
Project.unit<0>.triggerChannel<0><81>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<6>
Project.unit<0>.triggerChannel<0><82>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<7>
Project.unit<0>.triggerChannel<0><83>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<8>
Project.unit<0>.triggerChannel<0><84>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<9>
Project.unit<0>.triggerChannel<0><85>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<10>
Project.unit<0>.triggerChannel<0><86>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<11>
Project.unit<0>.triggerChannel<0><87>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<12>
Project.unit<0>.triggerChannel<0><88>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<13>
Project.unit<0>.triggerChannel<0><89>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<14>
Project.unit<0>.triggerChannel<0><8>=cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid
Project.unit<0>.triggerChannel<0><90>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<15>
Project.unit<0>.triggerChannel<0><91>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<16>
Project.unit<0>.triggerChannel<0><92>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<17>
Project.unit<0>.triggerChannel<0><93>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr<18>
Project.unit<0>.triggerChannel<0><94>=
Project.unit<0>.triggerChannel<0><95>=
Project.unit<0>.triggerChannel<0><96>=
Project.unit<0>.triggerChannel<0><97>=
Project.unit<0>.triggerChannel<0><98>=
Project.unit<0>.triggerChannel<0><99>=
Project.unit<0>.triggerChannel<0><9>=cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=2
Project.unit<0>.triggerMatchCountWidth<0><0>=10
Project.unit<0>.triggerMatchCountWidth<0><1>=10
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerMatchType<0><1>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=94
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
hdl/spec/chipscope/gn4124_local_bus_drv_dma_freeze.cdc 0 → 100644
View file @ c41460ea
#ChipScope Core Inserter Project File Version 3.0
#Tue Jul 02 11:05:25 CEST 2013
Project.device.designInputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.designOutputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=*dma_ctrl*
Project.filter<10>=*ddr_ctrl*wb_data*
Project.filter<11>=*cmp_l2p_*data_fifo*
Project.filter<12>=*cmp_l2p_*addr_fifo*
Project.filter<13>=*cmp_l2p_*dma_*cyc*
Project.filter<14>=*cmp_l2p_*dma_*cyc
Project.filter<15>=*cmp_l2p_*dma_*
Project.filter<16>=*cmp_l2p_*dma_adr*
Project.filter<17>=*cmp_l2p_*wb*cnt*
Project.filter<18>=*cmp_l2p_*wb*cnt
Project.filter<1>=*start*
Project.filter<2>=*p2l*
Project.filter<3>=*l2p_dma_master/data*
Project.filter<4>=*l2p_dma_master/*
Project.filter<5>=
Project.filter<6>=*l2p_last_*
Project.filter<7>=**
Project.filter<8>=*ddr_ctrl*wb_st*
Project.filter<9>=*ddr_ctrl*wb_ack*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=2
Project.unit<0>.clockChannel=cmp_gn4124_core/sys_clk
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=cmp_gn4124_core/l2p_edb_o
Project.unit<0>.dataChannel<100>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<5>
Project.unit<0>.dataChannel<101>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<6>
Project.unit<0>.dataChannel<102>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<7>
Project.unit<0>.dataChannel<103>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<8>
Project.unit<0>.dataChannel<104>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<9>
Project.unit<0>.dataChannel<105>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<10>
Project.unit<0>.dataChannel<106>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<11>
Project.unit<0>.dataChannel<107>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<12>
Project.unit<0>.dataChannel<108>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<13>
Project.unit<0>.dataChannel<109>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<14>
Project.unit<0>.dataChannel<10>=cmp_gn4124_core/l_wr_rdy<0>
Project.unit<0>.dataChannel<110>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<15>
Project.unit<0>.dataChannel<111>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<16>
Project.unit<0>.dataChannel<112>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<17>
Project.unit<0>.dataChannel<113>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<18>
Project.unit<0>.dataChannel<114>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<19>
Project.unit<0>.dataChannel<115>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<20>
Project.unit<0>.dataChannel<116>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<21>
Project.unit<0>.dataChannel<117>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<22>
Project.unit<0>.dataChannel<118>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<23>
Project.unit<0>.dataChannel<119>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<24>
Project.unit<0>.dataChannel<11>=cmp_gn4124_core/l_wr_rdy<1>
Project.unit<0>.dataChannel<120>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<25>
Project.unit<0>.dataChannel<121>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<26>
Project.unit<0>.dataChannel<122>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<27>
Project.unit<0>.dataChannel<123>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<28>
Project.unit<0>.dataChannel<124>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<29>
Project.unit<0>.dataChannel<125>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<30>
Project.unit<0>.dataChannel<126>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<31>
Project.unit<0>.dataChannel<12>=cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/almost_full_int
Project.unit<0>.dataChannel<13>=cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/U_Inferred_FIFO/almost_full_int
Project.unit<0>.dataChannel<14>=cmp_gn4124_core/cmp_p2l_dma_master/rx_error_o
Project.unit<0>.dataChannel<15>=cmp_gn4124_core/cmp_dma_controller/dma_status<0>
Project.unit<0>.dataChannel<16>=cmp_gn4124_core/cmp_dma_controller/dma_status<1>
Project.unit<0>.dataChannel<17>=cmp_gn4124_core/cmp_dma_controller/dma_status<2>
Project.unit<0>.dataChannel<18>=cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state_FSM_FFd3
Project.unit<0>.dataChannel<19>=cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state_FSM_FFd2
Project.unit<0>.dataChannel<1>=cmp_gn4124_core/l2p_rdy
Project.unit<0>.dataChannel<20>=cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state_FSM_FFd1
Project.unit<0>.dataChannel<21>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3
Project.unit<0>.dataChannel<22>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd2
Project.unit<0>.dataChannel<23>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd1
Project.unit<0>.dataChannel<24>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_valid
Project.unit<0>.dataChannel<25>=cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/empty_int
Project.unit<0>.dataChannel<26>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd
Project.unit<0>.dataChannel<27>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<0>
Project.unit<0>.dataChannel<28>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<1>
Project.unit<0>.dataChannel<29>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<2>
Project.unit<0>.dataChannel<2>=cmp_gn4124_core/p_rd_d_rdy<0>
Project.unit<0>.dataChannel<30>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<3>
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Project.unit<0>.triggerChannel<0><91>=cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<31>
Project.unit<0>.triggerChannel<0><92>=cmp_gn4124_core/cmp_p2l_des/p2l_dframe_o
Project.unit<0>.triggerChannel<0><93>=cmp_gn4124_core/cmp_p2l_des/p2l_valid_o
Project.unit<0>.triggerChannel<0><94>=cmp_gn4124_core/cmp_p2l_des/p2l_data_o<0>
Project.unit<0>.triggerChannel<0><95>=cmp_gn4124_core/cmp_p2l_des/p2l_data_o<1>
Project.unit<0>.triggerChannel<0><96>=cmp_gn4124_core/cmp_p2l_des/p2l_data_o<2>
Project.unit<0>.triggerChannel<0><97>=cmp_gn4124_core/cmp_p2l_des/p2l_data_o<3>
Project.unit<0>.triggerChannel<0><98>=cmp_gn4124_core/cmp_p2l_des/p2l_data_o<4>
Project.unit<0>.triggerChannel<0><99>=cmp_gn4124_core/cmp_p2l_des/p2l_data_o<5>
Project.unit<0>.triggerChannel<0><9>=cmp_gn4124_core/tx_error
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=5
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=127
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
Project.unit<1>.clockChannel=sys_clk_125
Project.unit<1>.clockEdge=Rising
Project.unit<1>.dataChannel<0>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<0>
Project.unit<1>.dataChannel<10>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<10>
Project.unit<1>.dataChannel<11>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<11>
Project.unit<1>.dataChannel<12>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<0>
Project.unit<1>.dataChannel<13>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<1>
Project.unit<1>.dataChannel<14>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<2>
Project.unit<1>.dataChannel<15>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<3>
Project.unit<1>.dataChannel<16>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<4>
Project.unit<1>.dataChannel<17>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<5>
Project.unit<1>.dataChannel<18>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<6>
Project.unit<1>.dataChannel<19>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<7>
Project.unit<1>.dataChannel<1>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<1>
Project.unit<1>.dataChannel<20>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<8>
Project.unit<1>.dataChannel<21>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<9>
Project.unit<1>.dataChannel<22>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<10>
Project.unit<1>.dataChannel<23>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<11>
Project.unit<1>.dataChannel<24>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<0>
Project.unit<1>.dataChannel<25>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<1>
Project.unit<1>.dataChannel<26>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<2>
Project.unit<1>.dataChannel<27>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<3>
Project.unit<1>.dataChannel<28>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<4>
Project.unit<1>.dataChannel<29>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<5>
Project.unit<1>.dataChannel<2>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<2>
Project.unit<1>.dataChannel<30>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<6>
Project.unit<1>.dataChannel<31>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<7>
Project.unit<1>.dataChannel<32>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<8>
Project.unit<1>.dataChannel<33>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<9>
Project.unit<1>.dataChannel<34>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<10>
Project.unit<1>.dataChannel<35>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<11>
Project.unit<1>.dataChannel<36>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<12>
Project.unit<1>.dataChannel<37>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<13>
Project.unit<1>.dataChannel<38>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<14>
Project.unit<1>.dataChannel<39>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<15>
Project.unit<1>.dataChannel<3>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<3>
Project.unit<1>.dataChannel<40>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<16>
Project.unit<1>.dataChannel<41>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<17>
Project.unit<1>.dataChannel<42>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<18>
Project.unit<1>.dataChannel<43>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<19>
Project.unit<1>.dataChannel<44>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<20>
Project.unit<1>.dataChannel<45>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<21>
Project.unit<1>.dataChannel<46>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<22>
Project.unit<1>.dataChannel<47>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<23>
Project.unit<1>.dataChannel<48>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<24>
Project.unit<1>.dataChannel<49>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<25>
Project.unit<1>.dataChannel<4>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<4>
Project.unit<1>.dataChannel<50>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_cyc_t
Project.unit<1>.dataChannel<51>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_rd
Project.unit<1>.dataChannel<52>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_valid
Project.unit<1>.dataChannel<53>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_wr
Project.unit<1>.dataChannel<54>=cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/almost_full_int
Project.unit<1>.dataChannel<55>=cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/U_Inferred_FIFO/full_int
Project.unit<1>.dataChannel<56>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<31>
Project.unit<1>.dataChannel<57>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<30>
Project.unit<1>.dataChannel<58>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<29>
Project.unit<1>.dataChannel<59>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<28>
Project.unit<1>.dataChannel<5>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<5>
Project.unit<1>.dataChannel<60>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<27>
Project.unit<1>.dataChannel<61>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<26>
Project.unit<1>.dataChannel<62>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<25>
Project.unit<1>.dataChannel<63>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<24>
Project.unit<1>.dataChannel<64>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<23>
Project.unit<1>.dataChannel<65>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<22>
Project.unit<1>.dataChannel<66>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<21>
Project.unit<1>.dataChannel<67>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<20>
Project.unit<1>.dataChannel<68>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<19>
Project.unit<1>.dataChannel<69>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<18>
Project.unit<1>.dataChannel<6>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<6>
Project.unit<1>.dataChannel<70>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<17>
Project.unit<1>.dataChannel<71>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<16>
Project.unit<1>.dataChannel<72>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<15>
Project.unit<1>.dataChannel<73>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<14>
Project.unit<1>.dataChannel<74>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<13>
Project.unit<1>.dataChannel<75>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<12>
Project.unit<1>.dataChannel<76>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<11>
Project.unit<1>.dataChannel<77>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<10>
Project.unit<1>.dataChannel<78>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<9>
Project.unit<1>.dataChannel<79>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<8>
Project.unit<1>.dataChannel<7>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<7>
Project.unit<1>.dataChannel<80>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<7>
Project.unit<1>.dataChannel<81>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<6>
Project.unit<1>.dataChannel<82>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<5>
Project.unit<1>.dataChannel<83>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<4>
Project.unit<1>.dataChannel<84>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<3>
Project.unit<1>.dataChannel<85>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<2>
Project.unit<1>.dataChannel<86>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<1>
Project.unit<1>.dataChannel<87>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<0>
Project.unit<1>.dataChannel<88>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_ack_o
Project.unit<1>.dataChannel<89>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stall_o
Project.unit<1>.dataChannel<8>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<8>
Project.unit<1>.dataChannel<90>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet
Project.unit<1>.dataChannel<9>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<9>
Project.unit<1>.dataDepth=2048
Project.unit<1>.dataEqualsTrigger=true
Project.unit<1>.dataPortWidth=88
Project.unit<1>.enableGaps=false
Project.unit<1>.enableStorageQualification=true
Project.unit<1>.enableTimestamps=false
Project.unit<1>.timestampDepth=0
Project.unit<1>.timestampWidth=0
Project.unit<1>.triggerChannel<0><0>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<0>
Project.unit<1>.triggerChannel<0><10>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<10>
Project.unit<1>.triggerChannel<0><11>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<11>
Project.unit<1>.triggerChannel<0><12>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<0>
Project.unit<1>.triggerChannel<0><13>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<1>
Project.unit<1>.triggerChannel<0><14>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<2>
Project.unit<1>.triggerChannel<0><15>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<3>
Project.unit<1>.triggerChannel<0><16>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<4>
Project.unit<1>.triggerChannel<0><17>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<5>
Project.unit<1>.triggerChannel<0><18>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<6>
Project.unit<1>.triggerChannel<0><19>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<7>
Project.unit<1>.triggerChannel<0><1>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<1>
Project.unit<1>.triggerChannel<0><20>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<8>
Project.unit<1>.triggerChannel<0><21>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<9>
Project.unit<1>.triggerChannel<0><22>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<10>
Project.unit<1>.triggerChannel<0><23>=cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt<11>
Project.unit<1>.triggerChannel<0><24>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<0>
Project.unit<1>.triggerChannel<0><25>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<1>
Project.unit<1>.triggerChannel<0><26>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<2>
Project.unit<1>.triggerChannel<0><27>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<3>
Project.unit<1>.triggerChannel<0><28>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<4>
Project.unit<1>.triggerChannel<0><29>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<5>
Project.unit<1>.triggerChannel<0><2>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<2>
Project.unit<1>.triggerChannel<0><30>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<6>
Project.unit<1>.triggerChannel<0><31>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<7>
Project.unit<1>.triggerChannel<0><32>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<8>
Project.unit<1>.triggerChannel<0><33>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<9>
Project.unit<1>.triggerChannel<0><34>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<10>
Project.unit<1>.triggerChannel<0><35>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<11>
Project.unit<1>.triggerChannel<0><36>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<12>
Project.unit<1>.triggerChannel<0><37>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<13>
Project.unit<1>.triggerChannel<0><38>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<14>
Project.unit<1>.triggerChannel<0><39>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<15>
Project.unit<1>.triggerChannel<0><3>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<3>
Project.unit<1>.triggerChannel<0><40>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<16>
Project.unit<1>.triggerChannel<0><41>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<17>
Project.unit<1>.triggerChannel<0><42>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<18>
Project.unit<1>.triggerChannel<0><43>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<19>
Project.unit<1>.triggerChannel<0><44>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<20>
Project.unit<1>.triggerChannel<0><45>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<21>
Project.unit<1>.triggerChannel<0><46>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<22>
Project.unit<1>.triggerChannel<0><47>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<23>
Project.unit<1>.triggerChannel<0><48>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<24>
Project.unit<1>.triggerChannel<0><49>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<25>
Project.unit<1>.triggerChannel<0><4>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<4>
Project.unit<1>.triggerChannel<0><50>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_cyc_t
Project.unit<1>.triggerChannel<0><51>=cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_valid
Project.unit<1>.triggerChannel<0><52>=cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_wr
Project.unit<1>.triggerChannel<0><53>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<31>
Project.unit<1>.triggerChannel<0><54>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<30>
Project.unit<1>.triggerChannel<0><55>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<29>
Project.unit<1>.triggerChannel<0><56>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<28>
Project.unit<1>.triggerChannel<0><57>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<27>
Project.unit<1>.triggerChannel<0><58>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<26>
Project.unit<1>.triggerChannel<0><59>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<25>
Project.unit<1>.triggerChannel<0><5>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<5>
Project.unit<1>.triggerChannel<0><60>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<24>
Project.unit<1>.triggerChannel<0><61>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<23>
Project.unit<1>.triggerChannel<0><62>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<22>
Project.unit<1>.triggerChannel<0><63>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<21>
Project.unit<1>.triggerChannel<0><64>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<20>
Project.unit<1>.triggerChannel<0><65>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<19>
Project.unit<1>.triggerChannel<0><66>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<18>
Project.unit<1>.triggerChannel<0><67>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<17>
Project.unit<1>.triggerChannel<0><68>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<16>
Project.unit<1>.triggerChannel<0><69>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<15>
Project.unit<1>.triggerChannel<0><6>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<6>
Project.unit<1>.triggerChannel<0><70>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<14>
Project.unit<1>.triggerChannel<0><71>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<13>
Project.unit<1>.triggerChannel<0><72>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<12>
Project.unit<1>.triggerChannel<0><73>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<11>
Project.unit<1>.triggerChannel<0><74>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<10>
Project.unit<1>.triggerChannel<0><75>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<9>
Project.unit<1>.triggerChannel<0><76>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<8>
Project.unit<1>.triggerChannel<0><77>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<7>
Project.unit<1>.triggerChannel<0><78>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<6>
Project.unit<1>.triggerChannel<0><79>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<5>
Project.unit<1>.triggerChannel<0><7>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<7>
Project.unit<1>.triggerChannel<0><80>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<4>
Project.unit<1>.triggerChannel<0><81>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<3>
Project.unit<1>.triggerChannel<0><82>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<2>
Project.unit<1>.triggerChannel<0><83>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<1>
Project.unit<1>.triggerChannel<0><84>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_data_o<0>
Project.unit<1>.triggerChannel<0><85>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_ack_o
Project.unit<1>.triggerChannel<0><86>=cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_1/wb_stall_o
Project.unit<1>.triggerChannel<0><87>=cmp_gn4124_core/cmp_l2p_dma_master/l2p_last_packet
Project.unit<1>.triggerChannel<0><88>=
Project.unit<1>.triggerChannel<0><89>=
Project.unit<1>.triggerChannel<0><8>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<8>
Project.unit<1>.triggerChannel<0><90>=
Project.unit<1>.triggerChannel<0><9>=cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt<9>
Project.unit<1>.triggerConditionCountWidth=0
Project.unit<1>.triggerMatchCount<0>=1
Project.unit<1>.triggerMatchCountWidth<0><0>=0
Project.unit<1>.triggerMatchType<0><0>=1
Project.unit<1>.triggerPortCount=1
Project.unit<1>.triggerPortIsData<0>=true
Project.unit<1>.triggerPortWidth<0>=88
Project.unit<1>.triggerSequencerLevels=16
Project.unit<1>.triggerSequencerType=1
Project.unit<1>.type=ilapro
hdl/spec/chipscope/int_trigger.cdc 0 → 100644
View file @ c41460ea
#ChipScope Core Inserter Project File Version 3.0
#Fri Mar 22 15:09:48 CET 2013
Project.device.designInputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.designOutputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=*fs_clk*
Project.filter<10>=*
Project.filter<11>=*BUF*
Project.filter<12>=*clk*
Project.filter<13>=
Project.filter<14>=*serdes_out*
Project.filter<15>=*fsclk*
Project.filter<16>=*l2p_last_*
Project.filter<17>=**
Project.filter<18>=*ddr_ctrl*wb_st*
Project.filter<1>=*trig_pol*
Project.filter<2>=*trig_sel*
Project.filter<3>=*trig_en*
Project.filter<4>=*trig*
Project.filter<5>=*thres*
Project.filter<6>=cmp_fmc_adc*/*trig*
Project.filter<7>=/cmp_fmc_adc*/*trig*
Project.filter<8>=*/cmp_fmc_adc_100Ms_core/*trig*
Project.filter<9>=/cmp_fmc_adc_100Ms_core/*trig*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=cmp_fmc_adc_100Ms_core/fs_clk
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=cmp_fmc_adc_100Ms_core/trig_align
Project.unit<0>.dataChannel<10>=cmp_fmc_adc_100Ms_core/int_trig_data<8>
Project.unit<0>.dataChannel<11>=cmp_fmc_adc_100Ms_core/int_trig_data<9>
Project.unit<0>.dataChannel<12>=cmp_fmc_adc_100Ms_core/int_trig_data<10>
Project.unit<0>.dataChannel<13>=cmp_fmc_adc_100Ms_core/int_trig_data<11>
Project.unit<0>.dataChannel<14>=cmp_fmc_adc_100Ms_core/int_trig_data<12>
Project.unit<0>.dataChannel<15>=cmp_fmc_adc_100Ms_core/int_trig_data<13>
Project.unit<0>.dataChannel<16>=cmp_fmc_adc_100Ms_core/int_trig_data<14>
Project.unit<0>.dataChannel<17>=cmp_fmc_adc_100Ms_core/int_trig_data<15>
Project.unit<0>.dataChannel<18>=cmp_fmc_adc_100Ms_core/int_trig_over_thres_d
Project.unit<0>.dataChannel<19>=cmp_fmc_adc_100Ms_core/int_trig_over_thres
Project.unit<0>.dataChannel<1>=cmp_fmc_adc_100Ms_core/trig
Project.unit<0>.dataChannel<20>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<0>
Project.unit<0>.dataChannel<21>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<1>
Project.unit<0>.dataChannel<22>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<2>
Project.unit<0>.dataChannel<23>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<3>
Project.unit<0>.dataChannel<24>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<4>
Project.unit<0>.dataChannel<25>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<5>
Project.unit<0>.dataChannel<26>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<6>
Project.unit<0>.dataChannel<27>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<7>
Project.unit<0>.dataChannel<28>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<8>
Project.unit<0>.dataChannel<29>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<9>
Project.unit<0>.dataChannel<2>=cmp_fmc_adc_100Ms_core/int_trig_data<0>
Project.unit<0>.dataChannel<30>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<10>
Project.unit<0>.dataChannel<31>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<11>
Project.unit<0>.dataChannel<32>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<12>
Project.unit<0>.dataChannel<33>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<13>
Project.unit<0>.dataChannel<34>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<14>
Project.unit<0>.dataChannel<35>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<15>
Project.unit<0>.dataChannel<36>=cmp_fmc_adc_100Ms_core/ext_trig_a
Project.unit<0>.dataChannel<37>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_o
Project.unit<0>.dataChannel<38>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_en_o
Project.unit<0>.dataChannel<39>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_sel_o<0>
Project.unit<0>.dataChannel<3>=cmp_fmc_adc_100Ms_core/int_trig_data<1>
Project.unit<0>.dataChannel<40>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_sel_o<1>
Project.unit<0>.dataChannel<41>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_o
Project.unit<0>.dataChannel<4>=cmp_fmc_adc_100Ms_core/int_trig_data<2>
Project.unit<0>.dataChannel<5>=cmp_fmc_adc_100Ms_core/int_trig_data<3>
Project.unit<0>.dataChannel<6>=cmp_fmc_adc_100Ms_core/int_trig_data<4>
Project.unit<0>.dataChannel<7>=cmp_fmc_adc_100Ms_core/int_trig_data<5>
Project.unit<0>.dataChannel<8>=cmp_fmc_adc_100Ms_core/int_trig_data<6>
Project.unit<0>.dataChannel<9>=cmp_fmc_adc_100Ms_core/int_trig_data<7>
Project.unit<0>.dataDepth=2048
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=42
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=cmp_fmc_adc_100Ms_core/trig_align
Project.unit<0>.triggerChannel<0><10>=cmp_fmc_adc_100Ms_core/int_trig_data<8>
Project.unit<0>.triggerChannel<0><11>=cmp_fmc_adc_100Ms_core/int_trig_data<9>
Project.unit<0>.triggerChannel<0><12>=cmp_fmc_adc_100Ms_core/int_trig_data<10>
Project.unit<0>.triggerChannel<0><13>=cmp_fmc_adc_100Ms_core/int_trig_data<11>
Project.unit<0>.triggerChannel<0><14>=cmp_fmc_adc_100Ms_core/int_trig_data<12>
Project.unit<0>.triggerChannel<0><15>=cmp_fmc_adc_100Ms_core/int_trig_data<13>
Project.unit<0>.triggerChannel<0><16>=cmp_fmc_adc_100Ms_core/int_trig_data<14>
Project.unit<0>.triggerChannel<0><17>=cmp_fmc_adc_100Ms_core/int_trig_data<15>
Project.unit<0>.triggerChannel<0><18>=cmp_fmc_adc_100Ms_core/int_trig_over_thres_d
Project.unit<0>.triggerChannel<0><19>=cmp_fmc_adc_100Ms_core/int_trig_over_thres
Project.unit<0>.triggerChannel<0><1>=cmp_fmc_adc_100Ms_core/trig
Project.unit<0>.triggerChannel<0><20>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<0>
Project.unit<0>.triggerChannel<0><21>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<1>
Project.unit<0>.triggerChannel<0><22>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<2>
Project.unit<0>.triggerChannel<0><23>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<3>
Project.unit<0>.triggerChannel<0><24>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<4>
Project.unit<0>.triggerChannel<0><25>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<5>
Project.unit<0>.triggerChannel<0><26>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<6>
Project.unit<0>.triggerChannel<0><27>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<7>
Project.unit<0>.triggerChannel<0><28>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<8>
Project.unit<0>.triggerChannel<0><29>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<9>
Project.unit<0>.triggerChannel<0><2>=cmp_fmc_adc_100Ms_core/int_trig_data<0>
Project.unit<0>.triggerChannel<0><30>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<10>
Project.unit<0>.triggerChannel<0><31>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<11>
Project.unit<0>.triggerChannel<0><32>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<12>
Project.unit<0>.triggerChannel<0><33>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<13>
Project.unit<0>.triggerChannel<0><34>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<14>
Project.unit<0>.triggerChannel<0><35>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<15>
Project.unit<0>.triggerChannel<0><36>=cmp_fmc_adc_100Ms_core/ext_trig_a
Project.unit<0>.triggerChannel<0><37>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_o
Project.unit<0>.triggerChannel<0><38>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_en_o
Project.unit<0>.triggerChannel<0><39>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_sel_o<0>
Project.unit<0>.triggerChannel<0><3>=cmp_fmc_adc_100Ms_core/int_trig_data<1>
Project.unit<0>.triggerChannel<0><40>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_sel_o<1>
Project.unit<0>.triggerChannel<0><41>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_o
Project.unit<0>.triggerChannel<0><4>=cmp_fmc_adc_100Ms_core/int_trig_data<2>
Project.unit<0>.triggerChannel<0><5>=cmp_fmc_adc_100Ms_core/int_trig_data<3>
Project.unit<0>.triggerChannel<0><6>=cmp_fmc_adc_100Ms_core/int_trig_data<4>
Project.unit<0>.triggerChannel<0><7>=cmp_fmc_adc_100Ms_core/int_trig_data<5>
Project.unit<0>.triggerChannel<0><8>=cmp_fmc_adc_100Ms_core/int_trig_data<6>
Project.unit<0>.triggerChannel<0><9>=cmp_fmc_adc_100Ms_core/int_trig_data<7>
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=42
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
hdl/spec/chipscope/irq.cdc 0 → 100644
View file @ c41460ea
#ChipScope Core Inserter Project File Version 3.0
#Fri Mar 22 08:28:00 CET 2013
Project.device.designInputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.designOutputFile=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/spec_top_fmc_adc_100Ms.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/mcattin/projects/svn_to_git/fmc-adc-100m14b4cha_git/hdl/spec/syn/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=*cmp_irq*rddata*
Project.filter<10>=*cmp_adc_sync*
Project.filter<11>=*cmp_adc_sync*_o*
Project.filter<12>=*cmp_adc_sync*q_o*
Project.filter<13>=*cmp_adc_sync*q_o
Project.filter<14>=*sync_fifo_dou*
Project.filter<15>=*acq_in_wait*
Project.filter<16>=*acq_trig*
Project.filter<17>=*acq_fsm*
Project.filter<18>=*sync_fifo_valid*
Project.filter<1>=*cmp_irq*
Project.filter<2>=*cnx_master_in[4]*
Project.filter<3>=*cnx_master_out[4]*
Project.filter<4>=*cnx_master_out*
Project.filter<5>=*dat*
Project.filter<6>=*.dat*
Project.filter<7>=*wb_dat*
Project.filter<8>=*irq_contr*
Project.filter<9>=**
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=sys_clk_125
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=cmp_fmc_adc_100Ms_core/trig_align
Project.unit<0>.dataChannel<10>=cmp_fmc_adc_100Ms_core/int_trig_data<8>
Project.unit<0>.dataChannel<11>=cmp_fmc_adc_100Ms_core/int_trig_data<9>
Project.unit<0>.dataChannel<12>=cmp_fmc_adc_100Ms_core/int_trig_data<10>
Project.unit<0>.dataChannel<13>=cmp_fmc_adc_100Ms_core/int_trig_data<11>
Project.unit<0>.dataChannel<14>=cmp_fmc_adc_100Ms_core/int_trig_data<12>
Project.unit<0>.dataChannel<15>=cmp_fmc_adc_100Ms_core/int_trig_data<13>
Project.unit<0>.dataChannel<16>=cmp_fmc_adc_100Ms_core/int_trig_data<14>
Project.unit<0>.dataChannel<17>=cmp_fmc_adc_100Ms_core/int_trig_data<15>
Project.unit<0>.dataChannel<18>=cmp_fmc_adc_100Ms_core/int_trig_over_thres_d
Project.unit<0>.dataChannel<19>=cmp_fmc_adc_100Ms_core/int_trig_over_thres
Project.unit<0>.dataChannel<1>=cmp_fmc_adc_100Ms_core/trig
Project.unit<0>.dataChannel<20>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<0>
Project.unit<0>.dataChannel<21>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<1>
Project.unit<0>.dataChannel<22>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<2>
Project.unit<0>.dataChannel<23>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<3>
Project.unit<0>.dataChannel<24>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<4>
Project.unit<0>.dataChannel<25>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<5>
Project.unit<0>.dataChannel<26>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<6>
Project.unit<0>.dataChannel<27>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<7>
Project.unit<0>.dataChannel<28>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<8>
Project.unit<0>.dataChannel<29>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<9>
Project.unit<0>.dataChannel<2>=cmp_fmc_adc_100Ms_core/int_trig_data<0>
Project.unit<0>.dataChannel<30>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<10>
Project.unit<0>.dataChannel<31>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<11>
Project.unit<0>.dataChannel<32>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<12>
Project.unit<0>.dataChannel<33>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<13>
Project.unit<0>.dataChannel<34>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<14>
Project.unit<0>.dataChannel<35>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_thres_o<15>
Project.unit<0>.dataChannel<36>=cmp_fmc_adc_100Ms_core/ext_trig_a
Project.unit<0>.dataChannel<37>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_sw_trig_en_o
Project.unit<0>.dataChannel<38>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_en_o
Project.unit<0>.dataChannel<39>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_sel_o<0>
Project.unit<0>.dataChannel<3>=cmp_fmc_adc_100Ms_core/int_trig_data<1>
Project.unit<0>.dataChannel<40>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_int_trig_sel_o<1>
Project.unit<0>.dataChannel<41>=cmp_fmc_adc_100Ms_core/cmp_fmc_adc_100Ms_csr/fmc_adc_core_trig_cfg_hw_trig_pol_o
Project.unit<0>.dataChannel<4>=cmp_fmc_adc_100Ms_core/int_trig_data<2>
Project.unit<0>.dataChannel<5>=cmp_fmc_adc_100Ms_core/int_trig_data<3>
Project.unit<0>.dataChannel<6>=cmp_fmc_adc_100Ms_core/int_trig_data<4>
Project.unit<0>.dataChannel<7>=cmp_fmc_adc_100Ms_core/int_trig_data<5>
Project.unit<0>.dataChannel<8>=cmp_fmc_adc_100Ms_core/int_trig_data<6>
Project.unit<0>.dataChannel<9>=cmp_fmc_adc_100Ms_core/int_trig_data<7>
Project.unit<0>.dataDepth=2048
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=125
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=cmp_irq_controller/irq_p_o
Project.unit<0>.triggerChannel<0><100>=cmp_irq_controller/cmp_irq_controller_regs/rddata_reg<7>
Project.unit<0>.triggerChannel<0><101>=cmp_irq_controller/cmp_irq_controller_regs/rddata_reg<8>
Project.unit<0>.triggerChannel<0><102>=cmp_irq_controller/cmp_irq_controller_regs/rddata_reg<9>
Project.unit<0>.triggerChannel<0><103>=cmp_irq_controller/cmp_irq_controller_regs/rddata_reg<10>
Project.unit<0>.triggerChannel<0><104>=cmp_irq_controller/cmp_irq_controller_regs/rddata_reg<11>
Project.unit<0>.triggerChannel<0><105>=cmp_irq_controller/cmp_irq_controller_regs/rddata_reg<12>
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Project.unit<0>.triggerChannel<0><1>=cmp_irq_controller/irq_pending<0>
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Project.unit<0>.triggerChannel<0><51>=cmp_fmc_adc_100Ms_core/sync_fifo_valid
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Project.unit<0>.triggerChannel<0><55>=cmp_irq_controller/cmp_irq_controller_regs/irq_ctrl_src_load_o
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Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=125
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
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