hdl: fixed identation and updated headers on all modified files, prior to new release

ca9e3875 · Dimitris Lampridis · 1f69cf8c · ca9e3875 · ca9e3875 · ca9e3875
Commit ca9e3875 authored Apr 19, 2016 by Dimitris Lampridis
3 changed files
--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
+-- Title      : FMC ADC 100Ms/s core
-- FMC ADC 100Ms/s core
+-- Project    : FMC ADC 100M 14B 4CHA gateware
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
+-- URL        : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
--
+-- File       : fmc_adc_100Ms_core.vhd
-- unit name: fmc_adc_100Ms_core (fmc_adc_100Ms_core.vhd)
+-- Author(s)  : Matthieu Cattin <matthieu.cattin@cern.ch>
--
+--              Theodor Stana <t.stana@cern.ch>
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+--              Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
--         Theodor Stana (t.stana@cern.ch)
+-- Company    : CERN (BE-CO-HT)
--
+-- Created    : 2011-02-24
-- date: 28-02-2011
+-- Last update: 2016-04-19
--
+-- Standard   : VHDL'93/02
-- description: FMC ADC 100Ms/s core.
+-------------------------------------------------------------------------------
--
+-- Description: FMC ADC 100Ms/s core.
-- dependencies:
+-------------------------------------------------------------------------------
--
+-- Copyright (c) 2011-2016 CERN (BE-CO-HT)
-- references:
+-------------------------------------------------------------------------------
--    [1] Xilinx UG175. FIFO Generator v6.2, July 23, 2010
--
--------------------------------------------------------------------------------
 -- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 -- This source file is free software; you can redistribute it and/or modify it
 -- under the terms of the GNU Lesser General Public License as published by the
 -- Free Software Foundation; either version 2.1 of the License, or (at your
@@ -30,11 +27,16 @@
 -- See the GNU Lesser General Public License for more details. You should have
 -- received a copy of the GNU Lesser General Public License along with this
 -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- last changes: see git log.
+-- Revisions  :
--------------------------------------------------------------------------------
+-- Date        Version  Author
-- TODO: - 
+-- 2016-04-20  4.1      Dimitrios Lampridis
--------------------------------------------------------------------------------
+-- 2014-04-25  4.0      Matthieu Cattin
+-- 2014-01-16  3.0      Matthieu Cattin
+-- 2013-07-29  2.0      Matthieu Cattin
+-- 2013-03-28  1.1      Matthieu Cattin
+-- 2013-03-11  1.0      Matthieu Cattin
+-------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
@@ -90,7 +92,7 @@ entity fmc_adc_100Ms_core is
    trigger_tag_i : t_timetag;
    -- FMC interface
-    ext_trigger_p_i : in std_logic;     -- External trigger
+    ext_trigger_p_i : in std_logic;               -- External trigger
    ext_trigger_n_i : in std_logic;
    adc_dco_p_i  : in std_logic;                     -- ADC data clock
@@ -102,14 +104,14 @@ entity fmc_adc_100Ms_core is
    adc_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
    adc_outb_n_i : in std_logic_vector(3 downto 0);
-    gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
+    gpio_dac_clr_n_o : out std_logic;             -- offset DACs clear (active low)
-    gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
+    gpio_led_acq_o   : out std_logic;             -- Mezzanine front panel power LED (PWR)
-    gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
+    gpio_led_trig_o  : out std_logic;             -- Mezzanine front panel trigger LED (TRIG)
    gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
    gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
    gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
    gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
-    gpio_si570_oe_o  : out std_logic                      -- Si570 (programmable oscillator) output enable
+    gpio_si570_oe_o  : out std_logic              -- Si570 (programmable oscillator) output enable
    );
 end fmc_adc_100Ms_core;
@@ -124,8 +126,8 @@ architecture rtl of fmc_adc_100Ms_core is
  component adc_serdes
    generic
      (
-        sys_w : integer := 9;                 -- width of the data for the system
+        sys_w : integer := 9;                     -- width of the data for the system
-        dev_w : integer := 72                 -- width of the data for the device
+        dev_w : integer := 72                     -- width of the data for the device
        );
    port
      (
@@ -136,13 +138,13 @@ architecture rtl of fmc_adc_100Ms_core is
        -- Data control
        BITSLIP             : in  std_logic;
        -- Clock and reset signals
-        CLK_IN              : in  std_logic;  -- Fast clock from PLL/MMCM
+        CLK_IN              : in  std_logic;      -- Fast clock from PLL/MMCM
        CLK_OUT             : out std_logic;
-        CLK_DIV_IN          : in  std_logic;  -- Slow clock from PLL/MMCM
+        CLK_DIV_IN          : in  std_logic;      -- Slow clock from PLL/MMCM
        LOCKED_IN           : in  std_logic;
        LOCKED_OUT          : out std_logic;
-        CLK_RESET           : in  std_logic;  -- Reset signal for Clock circuit
+        CLK_RESET           : in  std_logic;      -- Reset signal for Clock circuit
-        IO_RESET            : in  std_logic   -- Reset signal for IO circuit
+        IO_RESET            : in  std_logic       -- Reset signal for IO circuit
        );
  end component adc_serdes;
@@ -188,7 +190,7 @@ architecture rtl of fmc_adc_100Ms_core is
      fmc_adc_core_shots_cnt_val_i                : in  std_logic_vector(15 downto 0);
      fmc_adc_core_trig_pos_i                     : in  std_logic_vector(31 downto 0);
      fmc_adc_core_fs_freq_i                      : in  std_logic_vector(31 downto 0);
-      fmc_adc_core_sr_undersample_o                      : out std_logic_vector(31 downto 0);
+      fmc_adc_core_sr_undersample_o               : out std_logic_vector(31 downto 0);
      fmc_adc_core_pre_samples_o                  : out std_logic_vector(31 downto 0);
      fmc_adc_core_post_samples_o                 : out std_logic_vector(31 downto 0);
      fmc_adc_core_samples_cnt_i                  : in  std_logic_vector(31 downto 0);
@@ -212,25 +214,25 @@ architecture rtl of fmc_adc_100Ms_core is
      fmc_adc_core_ch4_gain_val_o                 : out std_logic_vector(15 downto 0);
      fmc_adc_core_ch4_offset_val_o               : out std_logic_vector(15 downto 0);
      fmc_adc_core_ch4_sat_val_o                  : out std_logic_vector(14 downto 0);
-      fmc_adc_core_multi_depth_i                  : in  std_logic_vector(31 downto 0)); 
+      fmc_adc_core_multi_depth_i                  : in  std_logic_vector(31 downto 0));
  end component fmc_adc_100Ms_csr;
  component ext_pulse_sync
    generic(
-      g_MIN_PULSE_WIDTH : natural   := 2;      --! Minimum input pulse width
+      g_MIN_PULSE_WIDTH : natural   := 2;         --! Minimum input pulse width
-                                               --! (in ns), must be >1 clk_i tick
+      --! (in ns), must be >1 clk_i tick
-      g_CLK_FREQUENCY   : natural   := 40;     --! clk_i frequency (in MHz)
+      g_CLK_FREQUENCY   : natural   := 40;        --! clk_i frequency (in MHz)
-      g_OUTPUT_POLARITY : std_logic := '1';    --! pulse_o polarity
+      g_OUTPUT_POLARITY : std_logic := '1';       --! pulse_o polarity
-                                               --! (1=negative, 0=positive)
+      --! (1=negative, 0=positive)
-      g_OUTPUT_RETRIG   : boolean   := false;  --! Retriggerable output monostable
+      g_OUTPUT_RETRIG   : boolean   := FALSE;     --! Retriggerable output monostable
-      g_OUTPUT_LENGTH   : natural   := 1       --! pulse_o lenght (in clk_i ticks)
+      g_OUTPUT_LENGTH   : natural   := 1          --! pulse_o lenght (in clk_i ticks)
      );
    port (
-      rst_n_i          : in  std_logic;        --! Reset (active low)
+      rst_n_i          : in  std_logic;           --! Reset (active low)
-      clk_i            : in  std_logic;        --! Clock to synchronize pulse
+      clk_i            : in  std_logic;           --! Clock to synchronize pulse
-      input_polarity_i : in  std_logic;        --! Input pulse polarity (1=negative, 0=positive)
+      input_polarity_i : in  std_logic;           --! Input pulse polarity (1=negative, 0=positive)
-      pulse_i          : in  std_logic;        --! Asynchronous input pulse
+      pulse_i          : in  std_logic;           --! Asynchronous input pulse
-      pulse_o          : out std_logic         --! Synchronized output pulse
+      pulse_o          : out std_logic            --! Synchronized output pulse
      );
  end component ext_pulse_sync;
@@ -248,18 +250,18 @@ architecture rtl of fmc_adc_100Ms_core is
  component monostable
    generic(
-      g_INPUT_POLARITY  : std_logic := '1';    --! trigger_i polarity
+      g_INPUT_POLARITY  : std_logic := '1';       --! trigger_i polarity
-                                               --! ('0'=negative, 1=positive)
+      --! ('0'=negative, 1=positive)
-      g_OUTPUT_POLARITY : std_logic := '1';    --! pulse_o polarity
+      g_OUTPUT_POLARITY : std_logic := '1';       --! pulse_o polarity
-                                               --! ('0'=negative, 1=positive)
+      --! ('0'=negative, 1=positive)
-      g_OUTPUT_RETRIG   : boolean   := false;  --! Retriggerable output monostable
+      g_OUTPUT_RETRIG   : boolean   := FALSE;     --! Retriggerable output monostable
-      g_OUTPUT_LENGTH   : natural   := 1       --! pulse_o lenght (in clk_i ticks)
+      g_OUTPUT_LENGTH   : natural   := 1          --! pulse_o lenght (in clk_i ticks)
      );
    port (
-      rst_n_i   : in  std_logic;               --! Reset (active low)
+      rst_n_i   : in  std_logic;                  --! Reset (active low)
-      clk_i     : in  std_logic;               --! Clock
+      clk_i     : in  std_logic;                  --! Clock
-      trigger_i : in  std_logic;               --! Trigger input pulse
+      trigger_i : in  std_logic;                  --! Trigger input pulse
-      pulse_o   : out std_logic                --! Monostable output pulse
+      pulse_o   : out std_logic                   --! Monostable output pulse
      );
  end component monostable;
@@ -465,7 +467,7 @@ begin
    generic map(
      g_INPUT_POLARITY  => '1',
      g_OUTPUT_POLARITY => '1',
-      g_OUTPUT_RETRIG   => true,
+      g_OUTPUT_RETRIG   => TRUE,
      g_OUTPUT_LENGTH   => 12500000
      )
    port map(
@@ -481,7 +483,7 @@ begin
    generic map(
      g_INPUT_POLARITY  => '1',
      g_OUTPUT_POLARITY => '1',
-      g_OUTPUT_RETRIG   => true,
+      g_OUTPUT_RETRIG   => TRUE,
      g_OUTPUT_LENGTH   => 12500000
      )
    port map(
@@ -505,7 +507,7 @@ begin
  ------------------------------------------------------------------------------
  cmp_dco_buf : IBUFDS
    generic map (
-      DIFF_TERM  => true,               -- Differential termination
+      DIFF_TERM  => TRUE,                         -- Differential termination
      IOSTANDARD => "LVDS_25")
    port map (
      I  => adc_dco_p_i,
@@ -516,9 +518,9 @@ begin
  cmp_dco_bufio : BUFIO2
    generic map (
      DIVIDE        => 1,
-      DIVIDE_BYPASS => true,
+      DIVIDE_BYPASS => TRUE,
-      I_INVERT      => false,
+      I_INVERT      => FALSE,
-      USE_DOUBLER   => false)
+      USE_DOUBLER   => FALSE)
    port map (
      I            => dco_clk_buf,
      IOCLK        => open,
@@ -573,7 +575,7 @@ begin
  cmp_fb_clk_bufio : BUFIO2FB
    generic map (
-      DIVIDE_BYPASS => true)
+      DIVIDE_BYPASS => TRUE)
    port map (
      I => clk_fb_buf,
      O => clk_fb
@@ -582,7 +584,7 @@ begin
  -- Sampinling clock frequency meter
  cmp_fs_freq : gc_frequency_meter
    generic map(
-      g_with_internal_timebase => true,
+      g_with_internal_timebase => TRUE,
      g_clk_sys_freq           => 125000000,
      g_counter_bits           => 32
      )
@@ -637,7 +639,7 @@ begin
      CLK_DIV_IN          => fs_clk,
      LOCKED_IN           => locked_in,
      LOCKED_OUT          => locked_out,
-      CLK_RESET           => '0',       -- unused
+      CLK_RESET           => '0',                 -- unused
      IO_RESET            => sys_rst
      );
@@ -703,7 +705,7 @@ begin
      bitslip_sreg <= bitslip_sreg(0) & bitslip_sreg(bitslip_sreg'length-1 downto 1);
      -- Generate bitslip and synced signal
-      if(bitslip_sreg(bitslip_sreg'left) = '1') then
+      if(bitslip_sreg(bitslip_sreg'LEFT) = '1') then
        if(serdes_out_fr /= "00001111") then  -- use fr_n pattern (fr_p and fr_n are swapped on the adc mezzanine)
          serdes_auto_bitslip <= '1';
          serdes_synced       <= '0';
@@ -765,7 +767,7 @@ begin
      fmc_adc_core_shots_cnt_val_i                => remaining_shots,
      fmc_adc_core_trig_pos_i                     => trig_addr,
      fmc_adc_core_fs_freq_i                      => fs_freq,
-      fmc_adc_core_sr_undersample_o                      => undersample_factor,
+      fmc_adc_core_sr_undersample_o               => undersample_factor,
      fmc_adc_core_pre_samples_o                  => pre_trig_value,
      fmc_adc_core_post_samples_o                 => post_trig_value,
      fmc_adc_core_samples_cnt_i                  => std_logic_vector(samples_cnt),
@@ -825,11 +827,11 @@ begin
  -- External hardware trigger synchronization
  cmp_trig_sync : ext_pulse_sync
    generic map(
-      g_MIN_PULSE_WIDTH => 1,           -- clk_i ticks
+      g_MIN_PULSE_WIDTH => 1,                     -- clk_i ticks
-      g_CLK_FREQUENCY   => 100,         -- MHz
+      g_CLK_FREQUENCY   => 100,                   -- MHz
-      g_OUTPUT_POLARITY => '0',         -- positive pulse
+      g_OUTPUT_POLARITY => '0',                   -- positive pulse
-      g_OUTPUT_RETRIG   => false,
+      g_OUTPUT_RETRIG   => FALSE,
-      g_OUTPUT_LENGTH   => 1            -- clk_i tick
+      g_OUTPUT_LENGTH   => 1                      -- clk_i tick
      )
    port map(
      rst_n_i          => fs_rst_n,
@@ -884,7 +886,7 @@ begin
  end process;
  int_trig <= int_trig_over_thres_filt and not(int_trig_over_thres_filt_d) when hw_trig_pol = '0' else  -- positive slope
-              not(int_trig_over_thres_filt) and int_trig_over_thres_filt_d;                             -- negative slope
+              not(int_trig_over_thres_filt) and int_trig_over_thres_filt_d;  -- negative slope
  -- Hardware trigger selection
  --    internal = adc data threshold
@@ -978,17 +980,17 @@ begin
    generic map (
      g_data_width             => 65,
      g_size                   => 16,
-      g_show_ahead             => false,
+      g_show_ahead             => FALSE,
-      g_with_rd_empty          => true,
+      g_with_rd_empty          => TRUE,
-      g_with_rd_full           => false,
+      g_with_rd_full           => FALSE,
-      g_with_rd_almost_empty   => false,
+      g_with_rd_almost_empty   => FALSE,
-      g_with_rd_almost_full    => false,
+      g_with_rd_almost_full    => FALSE,
-      g_with_rd_count          => false,
+      g_with_rd_count          => FALSE,
-      g_with_wr_empty          => false,
+      g_with_wr_empty          => FALSE,
-      g_with_wr_full           => true,
+      g_with_wr_full           => TRUE,
-      g_with_wr_almost_empty   => false,
+      g_with_wr_almost_empty   => FALSE,
-      g_with_wr_almost_full    => false,
+      g_with_wr_almost_full    => FALSE,
-      g_with_wr_count          => false,
+      g_with_wr_count          => FALSE,
      g_almost_empty_threshold => 0,
      g_almost_full_threshold  => 0
      )
@@ -997,7 +999,7 @@ begin
      clk_wr_i          => fs_clk,
      d_i               => sync_fifo_din,
      we_i              => sync_fifo_wr,
-      wr_empty_o        => open,        -- sync_fifo_empty,
+      wr_empty_o        => open,                  -- sync_fifo_empty,
      wr_full_o         => sync_fifo_full,
      wr_almost_empty_o => open,
      wr_almost_full_o  => open,
@@ -1014,7 +1016,7 @@ begin
  -- One clock cycle delay for the FIFO's VALID signal. Since the General Cores
  -- package does not offer the possibility to use the FWFT feature of the FIFOs,
-  -- we simulate the valid flag here according to Figure 4-7 in ref. [1].
+  -- we simulate the valid flag here according to Figure 4-7 in Xilinx UG175.
  p_sync_fifo_valid : process (sys_clk_i) is
  begin
    if rising_edge(sys_clk_i) then
@@ -1036,7 +1038,7 @@ begin
    if fs_rst_n = '0' then
      data_calibr_out_d <= (others => (others => '0'));
    elsif rising_edge(fs_clk) then
-      data_calibr_out_d <= data_calibr_out_d(data_calibr_out_d'left-1 downto 0) & data_calibr_out;
+      data_calibr_out_d <= data_calibr_out_d(data_calibr_out_d'LEFT-1 downto 0) & data_calibr_out;
    end if;
  end process p_data_delay;
@@ -1054,7 +1056,7 @@ begin
  --                 "00000000" & serdes_out_fr;
  sync_fifo_wr <= undersample_en and serdes_synced and not(sync_fifo_full);
-  sync_fifo_rd <= not(sync_fifo_empty);  -- read sync fifo as soon as data are available
+  sync_fifo_rd <= not(sync_fifo_empty);           -- read sync fifo as soon as data are available
  --============================================================================
@@ -1183,13 +1185,13 @@ begin
  -- TODO: because of a -yet to be fully understood- bug, acquisition produces
  -- corrupted samples when number_of_samples is exactly equal to multi_shot ram
  -- size. So for now, number_of_samples should be less than multi_shot ram size.
-  p_acq_cfg_ok: process (sys_clk_i)
+  p_acq_cfg_ok : process (sys_clk_i)
  begin
    if rising_edge(sys_clk_i) then
      if sys_rst_n_i = '0' then
        acq_config_ok <= '0';
      elsif unsigned(post_trig_value) = to_unsigned(0, post_trig_value'length) then
-         acq_config_ok <= '0';
+        acq_config_ok <= '0';
      elsif unsigned(shots_value) = to_unsigned(0, shots_value'length) then
        acq_config_ok <= '0';
      elsif single_shot = '0' and
@@ -1398,9 +1400,9 @@ begin
    (
      g_data_width               => 64,
      g_size                     => g_multishot_ram_size,
-      g_with_byte_enable         => false,
+      g_with_byte_enable         => FALSE,
      g_addr_conflict_resolution => "read_first",
-      g_dual_clock               => false
+      g_dual_clock               => FALSE
      -- default values for the rest of the generics are okay
      )
    port map
@@ -1425,9 +1427,9 @@ begin
    (
      g_data_width               => 64,
      g_size                     => g_multishot_ram_size,
-      g_with_byte_enable         => false,
+      g_with_byte_enable         => FALSE,
      g_addr_conflict_resolution => "read_first",
-      g_dual_clock               => false
+      g_dual_clock               => FALSE
      -- default values for the rest of the generics are okay
      )
    port map
@@ -1479,12 +1481,12 @@ begin
    generic map (
      g_data_width             => 65,
      g_size                   => 256,
-      g_show_ahead             => false,
+      g_show_ahead             => FALSE,
-      g_with_empty             => true,
+      g_with_empty             => TRUE,
-      g_with_full              => true,
+      g_with_full              => TRUE,
-      g_with_almost_empty      => false,
+      g_with_almost_empty      => FALSE,
-      g_with_almost_full       => false,
+      g_with_almost_full       => FALSE,
-      g_with_count             => false,
+      g_with_count             => FALSE,
      g_almost_empty_threshold => 0,
      g_almost_full_threshold  => 0
      )
@@ -1585,7 +1587,7 @@ begin
      wb_ddr_stall_t <= '0';
    elsif rising_edge(wb_ddr_clk_i) then
-      if wb_ddr_fifo_valid = '1' then   --if (wb_ddr_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
+      if wb_ddr_fifo_valid = '1' then  --if (wb_ddr_fifo_valid = '1') and (wb_ddr_stall_i = '0') then
        wb_ddr_stb_o <= '1';
        wb_ddr_adr_o <= "0000000" & std_logic_vector(ram_addr_cnt);
        if test_data_en = '1' then
@@ -1600,7 +1602,7 @@ begin
      if wb_ddr_fifo_valid = '1' then
        wb_ddr_cyc_o <= '1';
        wb_ddr_we_o  <= '1';
-        --elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
+      --elsif (wb_ddr_fifo_empty = '1') and (acq_end = '1') then
      elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
        wb_ddr_cyc_o <= '0';
        wb_ddr_we_o  <= '0';

--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
+-- Title      : FMC ADC 100Ms/s SPEC top-level
-- Top level entity for Simple PCIe FMC Carrier
+-- Project    : FMC ADC 100M 14B 4CHA gateware
-- http://www.ohwr.org/projects/spec
+-- URL        : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
--
+-- File       : spec_top_fmc_adc_100Ms.vhd
-- unit name: spec_top_fmc_adc_100Ms (spec_top_fmc_adc_100Ms.vhd)
+-- Author(s)  : Matthieu Cattin <matthieu.cattin@cern.ch>
--
+--            : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+-- Company    : CERN (BE-CO-HT)
--
+-- Created    : 2011-02-24
-- date: 24-02-2011
+-- Last update: 2016-04-19
--
+-- Standard   : VHDL'93/02
-- version: see sdb_meta_pkg.vhd
+-------------------------------------------------------------------------------
--
+-- Description: Top entity of FMC ADC 100Ms/s design for Simple PCIe FMC
-- description: Top entity of FMC ADC 100Ms/s design for SPEC board.
+-- Carrier (SPEC). See also: http://www.ohwr.org/projects/spec
--
+-------------------------------------------------------------------------------
-- dependencies:
+-- Copyright (c) 2011-2016 CERN (BE-CO-HT)
--
+-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
 -- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 -- This source file is free software; you can redistribute it and/or modify it
 -- under the terms of the GNU Lesser General Public License as published by the
 -- Free Software Foundation; either version 2.1 of the License, or (at your
@@ -28,11 +27,16 @@
 -- See the GNU Lesser General Public License for more details. You should have
 -- received a copy of the GNU Lesser General Public License along with this
 -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- last changes: see git log.
+-- Revisions  :
--------------------------------------------------------------------------------
+-- Date        Version  Author
-- TODO: - 
+-- 2016-04-20  4.1      Dimitrios Lampridis
--------------------------------------------------------------------------------
+-- 2014-04-25  4.0      Matthieu Cattin
+-- 2014-01-16  3.0      Matthieu Cattin
+-- 2013-07-29  2.0      Matthieu Cattin
+-- 2013-03-28  1.1      Matthieu Cattin
+-- 2013-03-11  1.0      Matthieu Cattin
+-------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
@@ -58,11 +62,11 @@ entity spec_top_fmc_adc_100Ms is
  port
    (
      -- Local oscillator
-      clk20_vcxo_i : in std_logic;      -- 20MHz VCXO clock
+      clk20_vcxo_i : in std_logic;                -- 20MHz VCXO clock
      -- DAC interface (20MHz and 25MHz VCXO)
-      pll25dac_sync_n_o : out std_logic;  -- 25MHz VCXO
+      pll25dac_sync_n_o : out std_logic;          -- 25MHz VCXO
-      pll20dac_sync_n_o : out std_logic;  -- 20MHz VCXO
+      pll20dac_sync_n_o : out std_logic;          -- 20MHz VCXO
      plldac_din_o      : out std_logic;
      plldac_sclk_o     : out std_logic;
@@ -81,28 +85,28 @@ entity spec_top_fmc_adc_100Ms is
      carrier_one_wire_b : inout std_logic;
      -- GN4124 interface
-      L_CLKp       : in    std_logic;                      -- Local bus clock (frequency set in GN4124 config registers)
+      L_CLKp       : in    std_logic;  -- Local bus clock (frequency set in GN4124 config registers)
-      L_CLKn       : in    std_logic;                      -- Local bus clock (frequency set in GN4124 config registers)
+      L_CLKn       : in    std_logic;  -- Local bus clock (frequency set in GN4124 config registers)
-      L_RST_N      : in    std_logic;                      -- Reset from GN4124 (RSTOUT18_N)
+      L_RST_N      : in    std_logic;             -- Reset from GN4124 (RSTOUT18_N)
-      P2L_RDY      : out   std_logic;                      -- Rx Buffer Full Flag
+      P2L_RDY      : out   std_logic;             -- Rx Buffer Full Flag
-      P2L_CLKn     : in    std_logic;                      -- Receiver Source Synchronous Clock-
+      P2L_CLKn     : in    std_logic;             -- Receiver Source Synchronous Clock-
-      P2L_CLKp     : in    std_logic;                      -- Receiver Source Synchronous Clock+
+      P2L_CLKp     : in    std_logic;             -- Receiver Source Synchronous Clock+
      P2L_DATA     : in    std_logic_vector(15 downto 0);  -- Parallel receive data
-      P2L_DFRAME   : in    std_logic;                      -- Receive Frame
+      P2L_DFRAME   : in    std_logic;             -- Receive Frame
-      P2L_VALID    : in    std_logic;                      -- Receive Data Valid
+      P2L_VALID    : in    std_logic;             -- Receive Data Valid
      P_WR_REQ     : in    std_logic_vector(1 downto 0);   -- PCIe Write Request
      P_WR_RDY     : out   std_logic_vector(1 downto 0);   -- PCIe Write Ready
-      RX_ERROR     : out   std_logic;                      -- Receive Error
+      RX_ERROR     : out   std_logic;             -- Receive Error
      L2P_DATA     : out   std_logic_vector(15 downto 0);  -- Parallel transmit data
-      L2P_DFRAME   : out   std_logic;                      -- Transmit Data Frame
+      L2P_DFRAME   : out   std_logic;             -- Transmit Data Frame
-      L2P_VALID    : out   std_logic;                      -- Transmit Data Valid
+      L2P_VALID    : out   std_logic;             -- Transmit Data Valid
-      L2P_CLKn     : out   std_logic;                      -- Transmitter Source Synchronous Clock-
+      L2P_CLKn     : out   std_logic;             -- Transmitter Source Synchronous Clock-
-      L2P_CLKp     : out   std_logic;                      -- Transmitter Source Synchronous Clock+
+      L2P_CLKp     : out   std_logic;             -- Transmitter Source Synchronous Clock+
-      L2P_EDB      : out   std_logic;                      -- Packet termination and discard
+      L2P_EDB      : out   std_logic;             -- Packet termination and discard
-      L2P_RDY      : in    std_logic;                      -- Tx Buffer Full Flag
+      L2P_RDY      : in    std_logic;             -- Tx Buffer Full Flag
      L_WR_RDY     : in    std_logic_vector(1 downto 0);   -- Local-to-PCIe Write
      P_RD_D_RDY   : in    std_logic_vector(1 downto 0);   -- PCIe-to-Local Read Response Data Ready
-      TX_ERROR     : in    std_logic;                      -- Transmit Error
+      TX_ERROR     : in    std_logic;             -- Transmit Error
      VC_RDY       : in    std_logic_vector(1 downto 0);   -- Channel ready
      GPIO         : inout std_logic_vector(1 downto 0);   -- GPIO[0] -> GN4124 GPIO8
                                                           -- GPIO[1] -> GN4124 GPIO9
@@ -128,7 +132,7 @@ entity spec_top_fmc_adc_100Ms is
      DDR3_RZQ     : inout std_logic;
      -- FMC slot
-      adc0_ext_trigger_p_i : in std_logic;  -- External trigger
+      adc0_ext_trigger_p_i : in std_logic;        -- External trigger
      adc0_ext_trigger_n_i : in std_logic;
      adc0_dco_p_i  : in std_logic;                     -- ADC data clock
@@ -140,34 +144,34 @@ entity spec_top_fmc_adc_100Ms is
      adc0_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
      adc0_outb_n_i : in std_logic_vector(3 downto 0);
-      adc0_spi_din_i       : in  std_logic;  -- SPI data from FMC
+      adc0_spi_din_i       : in  std_logic;       -- SPI data from FMC
-      adc0_spi_dout_o      : out std_logic;  -- SPI data to FMC
+      adc0_spi_dout_o      : out std_logic;       -- SPI data to FMC
-      adc0_spi_sck_o       : out std_logic;  -- SPI clock
+      adc0_spi_sck_o       : out std_logic;       -- SPI clock
-      adc0_spi_cs_adc_n_o  : out std_logic;  -- SPI ADC chip select (active low)
+      adc0_spi_cs_adc_n_o  : out std_logic;       -- SPI ADC chip select (active low)
      adc0_spi_cs_dac1_n_o : out std_logic;  -- SPI channel 1 offset DAC chip select (active low)
      adc0_spi_cs_dac2_n_o : out std_logic;  -- SPI channel 2 offset DAC chip select (active low)
      adc0_spi_cs_dac3_n_o : out std_logic;  -- SPI channel 3 offset DAC chip select (active low)
      adc0_spi_cs_dac4_n_o : out std_logic;  -- SPI channel 4 offset DAC chip select (active low)
-      adc0_gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
+      adc0_gpio_dac_clr_n_o : out std_logic;      -- offset DACs clear (active low)
-      adc0_gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
+      adc0_gpio_led_acq_o   : out std_logic;      -- Mezzanine front panel power LED (PWR)
-      adc0_gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
+      adc0_gpio_led_trig_o  : out std_logic;      -- Mezzanine front panel trigger LED (TRIG)
      adc0_gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
      adc0_gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
      adc0_gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
      adc0_gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
-      adc0_gpio_si570_oe_o  : out std_logic;                     -- Si570 (programmable oscillator) output enable
+      adc0_gpio_si570_oe_o  : out std_logic;      -- Si570 (programmable oscillator) output enable
-      adc0_si570_scl_b : inout std_logic;  -- I2C bus clock (Si570)
+      adc0_si570_scl_b : inout std_logic;         -- I2C bus clock (Si570)
-      adc0_si570_sda_b : inout std_logic;  -- I2C bus data (Si570)
+      adc0_si570_sda_b : inout std_logic;         -- I2C bus data (Si570)
      adc0_one_wire_b : inout std_logic;  -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
      -- FMC slot management
-      fmc0_prsnt_m2c_n_i : in std_logic;  -- Mezzanine present (active low)
+      fmc0_prsnt_m2c_n_i : in std_logic;          -- Mezzanine present (active low)
-      fmc0_sys_scl_b : inout std_logic;  -- Mezzanine system I2C clock (EEPROM)
+      fmc0_sys_scl_b : inout std_logic;           -- Mezzanine system I2C clock (EEPROM)
-      fmc0_sys_sda_b : inout std_logic   -- Mezzanine system I2C data (EEPROM)
+      fmc0_sys_sda_b : inout std_logic            -- Mezzanine system I2C data (EEPROM)
      );
 end spec_top_fmc_adc_100Ms;
@@ -242,58 +246,58 @@ architecture rtl of spec_top_fmc_adc_100Ms is
  constant c_MASTER_GENNUM : integer := 0;
  -- Wishbone slave(s)
-  constant c_WB_SLAVE_DMA      : integer := 0;  -- DMA controller in the Gennum core
+  constant c_WB_SLAVE_DMA      : integer := 0;    -- DMA controller in the Gennum core
-  constant c_WB_SLAVE_ONEWIRE  : integer := 1;  -- Carrier onewire interface
+  constant c_WB_SLAVE_ONEWIRE  : integer := 1;    -- Carrier onewire interface
-  constant c_WB_SLAVE_SPEC_CSR : integer := 2;  -- SPEC control and status registers
+  constant c_WB_SLAVE_SPEC_CSR : integer := 2;    -- SPEC control and status registers
-  constant c_WB_SLAVE_VIC      : integer := 3;  -- Vectored interrupt controller
+  constant c_WB_SLAVE_VIC      : integer := 3;    -- Vectored interrupt controller
-  constant c_WB_SLAVE_DMA_EIC  : integer := 4;  -- DMA interrupt controller
+  constant c_WB_SLAVE_DMA_EIC  : integer := 4;    -- DMA interrupt controller
-  constant c_WB_SLAVE_FMC_ADC  : integer := 5;  -- FMC ADC mezzanine
+  constant c_WB_SLAVE_FMC_ADC  : integer := 5;    -- FMC ADC mezzanine
  -- Devices sdb description
  constant c_wb_dma_ctrl_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
+    abi_class     => x"0000",                     -- undocumented device
    abi_ver_major => x"01",
    abi_ver_minor => x"01",
    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"4",                 -- 32-bit port granularity
+    wbd_width     => x"4",                        -- 32-bit port granularity
    sdb_component => (
      addr_first  => x"0000000000000000",
      addr_last   => x"000000000000003F",
      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
+        vendor_id => x"000000000000CE42",         -- CERN
        device_id => x"00000601",
        version   => x"00000001",
        date      => x"20121116",
        name      => "WB-DMA.Control     ")));
  constant c_wb_spec_csr_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
+    abi_class     => x"0000",                     -- undocumented device
    abi_ver_major => x"01",
    abi_ver_minor => x"01",
    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"4",                 -- 32-bit port granularity
+    wbd_width     => x"4",                        -- 32-bit port granularity
    sdb_component => (
      addr_first  => x"0000000000000000",
      addr_last   => x"000000000000001F",
      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
+        vendor_id => x"000000000000CE42",         -- CERN
        device_id => x"00000603",
        version   => x"00000001",
        date      => x"20121116",
        name      => "WB-SPEC-CSR        ")));
  constant c_wb_dma_eic_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
+    abi_class     => x"0000",                     -- undocumented device
    abi_ver_major => x"01",
    abi_ver_minor => x"01",
    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"4",                 -- 32-bit port granularity
+    wbd_width     => x"4",                        -- 32-bit port granularity
    sdb_component => (
      addr_first  => x"0000000000000000",
      addr_last   => x"000000000000000F",
      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
+        vendor_id => x"000000000000CE42",         -- CERN
-        device_id => x"d5735ab4",          -- echo "WB-DMA.EIC         " | md5sum | cut -c1-8
+        device_id => x"d5735ab4",                 -- echo "WB-DMA.EIC         " | md5sum | cut -c1-8
        version   => x"00000001",
        date      => x"20131204",
        name      => "WB-DMA.EIC         ")));
@@ -522,13 +526,13 @@ begin
  ------------------------------------------------------------------------------
  cmp_l_clk_buf : IBUFDS
    generic map (
-      DIFF_TERM    => false,            -- Differential Termination
+      DIFF_TERM    => FALSE,                      -- Differential Termination
-      IBUF_LOW_PWR => true,             -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+      IBUF_LOW_PWR => TRUE,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD   => "DEFAULT")
    port map (
-      O  => l_clk,                      -- Buffer output
+      O  => l_clk,                                -- Buffer output
-      I  => L_CLKp,                     -- Diff_p buffer input (connect directly to top-level port)
+      I  => L_CLKp,          -- Diff_p buffer input (connect directly to top-level port)
-      IB => L_CLKn                      -- Diff_n buffer input (connect directly to top-level port)
+      IB => L_CLKn           -- Diff_n buffer input (connect directly to top-level port)
      );
  ------------------------------------------------------------------------------
@@ -653,8 +657,8 @@ begin
    generic map (
      g_num_masters => c_NUM_WB_SLAVES,
      g_num_slaves  => c_NUM_WB_MASTERS,
-      g_registered  => true,
+      g_registered  => TRUE,
-      g_wraparound  => true,
+      g_wraparound  => TRUE,
      g_layout      => c_INTERCONNECT_LAYOUT,
      g_sdb_addr    => c_SDB_ADDRESS)
    port map (
@@ -992,7 +996,7 @@ begin
  ------------------------------------------------------------------------------
  -- Assign unused outputs
  ------------------------------------------------------------------------------
-  GPIO(1) <= '0';                       -- connection to GN4124
+  GPIO(1) <= '0';                                 -- connection to GN4124
  ------------------------------------------------------------------------------
  -- FPGA loaded led (heart beat)

--- a/hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+++ b/hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
+-- Title      : FMC ADC 100Ms/s SVEC top-level
-- Top level entity for Simple VME FMC Carrier
+-- Project    : FMC ADC 100M 14B 4CHA gateware
-- http://www.ohwr.org/projects/svec
+-- URL        : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
--
+-- File       : svec_top_fmc_adc_100Ms.vhd
-- unit name: svec_top_fmc_adc_100Ms (svec_top_fmc_adc_100Ms.vhd)
+-- Author(s)  : Matthieu Cattin <matthieu.cattin@cern.ch>
--
+--            : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
+-- Company    : CERN (BE-CO-HT)
--
+-- Created    : 2013-07-04
-- date: 04-07-2013
+-- Last update: 2016-04-19
--
+-- Standard   : VHDL'93/02
-- version: see sdb_meta_pkg.vhd
+-------------------------------------------------------------------------------
--
+-- Description: Top entity of FMC ADC 100Ms/s design for Simple VME FMC
-- description: Top entity of FMC ADC 100Ms/s design for SVEC board.
+-- Carrier (SVEC). See also: http://www.ohwr.org/projects/svec
--
+-------------------------------------------------------------------------------
-- dependencies:
+-- Copyright (c) 2013-2016 CERN (BE-CO-HT)
--
+-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
 -- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 -- This source file is free software; you can redistribute it and/or modify it
 -- under the terms of the GNU Lesser General Public License as published by the
 -- Free Software Foundation; either version 2.1 of the License, or (at your
@@ -28,11 +27,14 @@
 -- See the GNU Lesser General Public License for more details. You should have
 -- received a copy of the GNU Lesser General Public License along with this
 -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- last changes: see git log.
+-- Revisions  :
--------------------------------------------------------------------------------
+-- Date        Version  Author
-- TODO: - 
+-- 2016-04-20  4.1      Dimitrios Lampridis
--------------------------------------------------------------------------------
+-- 2014-04-25  4.0      Matthieu Cattin
+-- 2014-01-16  3.0      Matthieu Cattin
+-- 2013-07-29  1.0      Matthieu Cattin
+-------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
@@ -164,7 +166,7 @@ entity svec_top_fmc_adc_100Ms is
      ------------------------------------------
      -- FMC slot 0
      ------------------------------------------
-      adc0_ext_trigger_p_i : in std_logic;  -- External trigger
+      adc0_ext_trigger_p_i : in std_logic;        -- External trigger
      adc0_ext_trigger_n_i : in std_logic;
      adc0_dco_p_i  : in std_logic;                     -- ADC data clock
@@ -176,33 +178,33 @@ entity svec_top_fmc_adc_100Ms is
      adc0_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
      adc0_outb_n_i : in std_logic_vector(3 downto 0);
-      adc0_spi_din_i       : in  std_logic;  -- SPI data from FMC
+      adc0_spi_din_i       : in  std_logic;       -- SPI data from FMC
-      adc0_spi_dout_o      : out std_logic;  -- SPI data to FMC
+      adc0_spi_dout_o      : out std_logic;       -- SPI data to FMC
-      adc0_spi_sck_o       : out std_logic;  -- SPI clock
+      adc0_spi_sck_o       : out std_logic;       -- SPI clock
-      adc0_spi_cs_adc_n_o  : out std_logic;  -- SPI ADC chip select (active low)
+      adc0_spi_cs_adc_n_o  : out std_logic;       -- SPI ADC chip select (active low)
      adc0_spi_cs_dac1_n_o : out std_logic;  -- SPI channel 1 offset DAC chip select (active low)
      adc0_spi_cs_dac2_n_o : out std_logic;  -- SPI channel 2 offset DAC chip select (active low)
      adc0_spi_cs_dac3_n_o : out std_logic;  -- SPI channel 3 offset DAC chip select (active low)
      adc0_spi_cs_dac4_n_o : out std_logic;  -- SPI channel 4 offset DAC chip select (active low)
-      adc0_gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
+      adc0_gpio_dac_clr_n_o : out std_logic;      -- offset DACs clear (active low)
-      adc0_gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
+      adc0_gpio_led_acq_o   : out std_logic;      -- Mezzanine front panel power LED (PWR)
-      adc0_gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
+      adc0_gpio_led_trig_o  : out std_logic;      -- Mezzanine front panel trigger LED (TRIG)
      adc0_gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
      adc0_gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
      adc0_gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
      adc0_gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
-      adc0_gpio_si570_oe_o  : out std_logic;                     -- Si570 (programmable oscillator) output enable
+      adc0_gpio_si570_oe_o  : out std_logic;      -- Si570 (programmable oscillator) output enable
-      adc0_si570_scl_b : inout std_logic;  -- I2C bus clock (Si570)
+      adc0_si570_scl_b : inout std_logic;         -- I2C bus clock (Si570)
-      adc0_si570_sda_b : inout std_logic;  -- I2C bus data (Si570)
+      adc0_si570_sda_b : inout std_logic;         -- I2C bus data (Si570)
      adc0_one_wire_b : inout std_logic;  -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
      ------------------------------------------
      -- FMC slot 1
      ------------------------------------------
-      adc1_ext_trigger_p_i : in std_logic;  -- External trigger
+      adc1_ext_trigger_p_i : in std_logic;        -- External trigger
      adc1_ext_trigger_n_i : in std_logic;
      adc1_dco_p_i  : in std_logic;                     -- ADC data clock
@@ -214,39 +216,39 @@ entity svec_top_fmc_adc_100Ms is
      adc1_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
      adc1_outb_n_i : in std_logic_vector(3 downto 0);
-      adc1_spi_din_i       : in  std_logic;  -- SPI data from FMC
+      adc1_spi_din_i       : in  std_logic;       -- SPI data from FMC
-      adc1_spi_dout_o      : out std_logic;  -- SPI data to FMC
+      adc1_spi_dout_o      : out std_logic;       -- SPI data to FMC
-      adc1_spi_sck_o       : out std_logic;  -- SPI clock
+      adc1_spi_sck_o       : out std_logic;       -- SPI clock
-      adc1_spi_cs_adc_n_o  : out std_logic;  -- SPI ADC chip select (active low)
+      adc1_spi_cs_adc_n_o  : out std_logic;       -- SPI ADC chip select (active low)
      adc1_spi_cs_dac1_n_o : out std_logic;  -- SPI channel 1 offset DAC chip select (active low)
      adc1_spi_cs_dac2_n_o : out std_logic;  -- SPI channel 2 offset DAC chip select (active low)
      adc1_spi_cs_dac3_n_o : out std_logic;  -- SPI channel 3 offset DAC chip select (active low)
      adc1_spi_cs_dac4_n_o : out std_logic;  -- SPI channel 4 offset DAC chip select (active low)
-      adc1_gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
+      adc1_gpio_dac_clr_n_o : out std_logic;      -- offset DACs clear (active low)
-      adc1_gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
+      adc1_gpio_led_acq_o   : out std_logic;      -- Mezzanine front panel power LED (PWR)
-      adc1_gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
+      adc1_gpio_led_trig_o  : out std_logic;      -- Mezzanine front panel trigger LED (TRIG)
      adc1_gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
      adc1_gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
      adc1_gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
      adc1_gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
-      adc1_gpio_si570_oe_o  : out std_logic;                     -- Si570 (programmable oscillator) output enable
+      adc1_gpio_si570_oe_o  : out std_logic;      -- Si570 (programmable oscillator) output enable
-      adc1_si570_scl_b : inout std_logic;  -- I2C bus clock (Si570)
+      adc1_si570_scl_b : inout std_logic;         -- I2C bus clock (Si570)
-      adc1_si570_sda_b : inout std_logic;  -- I2C bus data (Si570)
+      adc1_si570_sda_b : inout std_logic;         -- I2C bus data (Si570)
      adc1_one_wire_b : inout std_logic;  -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
      ------------------------------------------
      -- FMC slot management
      ------------------------------------------
-      fmc0_prsnt_m2c_n_i : in    std_logic;  -- Mezzanine present (active low)
+      fmc0_prsnt_m2c_n_i : in    std_logic;       -- Mezzanine present (active low)
-      fmc0_scl_b         : inout std_logic;  -- Mezzanine system I2C clock (EEPROM)
+      fmc0_scl_b         : inout std_logic;       -- Mezzanine system I2C clock (EEPROM)
-      fmc0_sda_b         : inout std_logic;  -- Mezzanine system I2C data (EEPROM)
+      fmc0_sda_b         : inout std_logic;       -- Mezzanine system I2C data (EEPROM)
-      fmc1_prsnt_m2c_n_i : in    std_logic;  -- Mezzanine present (active low)
+      fmc1_prsnt_m2c_n_i : in    std_logic;       -- Mezzanine present (active low)
-      fmc1_scl_b         : inout std_logic;  -- Mezzanine system I2C clock (EEPROM)
+      fmc1_scl_b         : inout std_logic;       -- Mezzanine system I2C clock (EEPROM)
-      fmc1_sda_b         : inout std_logic   -- Mezzanine system I2C data (EEPROM)
+      fmc1_sda_b         : inout std_logic        -- Mezzanine system I2C data (EEPROM)
      );
 end svec_top_fmc_adc_100Ms;
@@ -337,48 +339,48 @@ architecture rtl of svec_top_fmc_adc_100Ms is
  -- Devices sdb description
  constant c_wb_svec_csr_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
+    abi_class     => x"0000",                     -- undocumented device
    abi_ver_major => x"01",
    abi_ver_minor => x"01",
    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"4",                 -- 32-bit port granularity
+    wbd_width     => x"4",                        -- 32-bit port granularity
    sdb_component => (
      addr_first  => x"0000000000000000",
      addr_last   => x"000000000000001F",
      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
+        vendor_id => x"000000000000CE42",         -- CERN
        device_id => x"00006603",
        version   => x"00000001",
        date      => x"20121116",
        name      => "WB-SVEC-CSR        ")));
  constant c_wb_ddr_dat_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
+    abi_class     => x"0000",                     -- undocumented device
    abi_ver_major => x"01",
    abi_ver_minor => x"01",
    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"4",                 -- 32-bit port granularity
+    wbd_width     => x"4",                        -- 32-bit port granularity
    sdb_component => (
      addr_first  => x"0000000000000000",
      addr_last   => x"0000000000000FFF",
      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
+        vendor_id => x"000000000000CE42",         -- CERN
        device_id => x"10006610",
        version   => x"00000001",
        date      => x"20130704",
        name      => "WB-DDR-Data-Access ")));
  constant c_wb_ddr_adr_sdb : t_sdb_device := (
-    abi_class     => x"0000",              -- undocumented device
+    abi_class     => x"0000",                     -- undocumented device
    abi_ver_major => x"01",
    abi_ver_minor => x"01",
    wbd_endian    => c_sdb_endian_big,
-    wbd_width     => x"4",                 -- 32-bit port granularity
+    wbd_width     => x"4",                        -- 32-bit port granularity
    sdb_component => (
      addr_first  => x"0000000000000000",
      addr_last   => x"0000000000000003",
      product     => (
-        vendor_id => x"000000000000CE42",  -- CERN
+        vendor_id => x"000000000000CE42",         -- CERN
        device_id => x"10006611",
        version   => x"00000001",
        date      => x"20130704",
@@ -775,8 +777,8 @@ begin
    generic map (
      g_num_masters => c_NUM_WB_SLAVES,
      g_num_slaves  => c_NUM_WB_MASTERS,
-      g_registered  => true,
+      g_registered  => TRUE,
-      g_wraparound  => true,
+      g_wraparound  => TRUE,
      g_layout      => c_INTERCONNECT_LAYOUT,
      g_sdb_addr    => c_SDB_ADDRESS)
    port map (
@@ -1412,20 +1414,20 @@ begin
  ------------------------------------------------------------------------------
  -- Front panel LED control
-  --  
+  --
  ------------------------------------------------------------------------------
  cmp_led_controller : gc_bicolor_led_ctrl
    generic map(
      g_nb_column    => 4,
      g_nb_line      => 2,
-      g_clk_freq     => 125000000,      -- in Hz
+      g_clk_freq     => 125000000,                -- in Hz
-      g_refresh_rate => 250             -- in Hz
+      g_refresh_rate => 250                       -- in Hz
      )
    port map(
      rst_n_i => sys_rst_n,
      clk_i   => sys_clk_125,
-      led_intensity_i => "1100100",     -- in %
+      led_intensity_i => "1100100",               -- in %
      led_state_i => led_state,
@@ -1467,25 +1469,25 @@ begin
  -- LED 1 : VME access
  led_state(1 downto 0) <= c_led_green when vme_access = '1' else c_led_off;
-  -- LED 2 : 
+  -- LED 2 :
  led_state(3 downto 2) <= c_led_red;
-  -- LED 3 : 
+  -- LED 3 :
  led_state(5 downto 4) <= c_led_red_green;
-  -- LED 4 : 
+  -- LED 4 :
  led_state(7 downto 6) <= '0' & led_pwm;
-  -- LED 5 : 
+  -- LED 5 :
  led_state(9 downto 8) <= fmc0_trig_irq_led & '0';
-  -- LED 6 : 
+  -- LED 6 :
  led_state(11 downto 10) <= fmc0_acq_end_irq_led & '0';
-  -- LED 7 : 
+  -- LED 7 :
  led_state(13 downto 12) <= '0' & fmc_irq(0);
-  -- LED 8 : 
+  -- LED 8 :
  led_state(15 downto 14) <= '0' & irq_to_vme_sync;
  --led_state(15 downto 12) <= led_state_man(15 downto 12);