Skip to content

F
FMC ADC 100M 14b 4cha - Gateware
Commit ca9e3875 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

hdl: fixed identation and updated headers on all modified files, prior to new release

parent 1f69cf8c
Expand all Show whitespace changes
Inline Side-by-side
Showing with 273 additions and 265 deletions
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ ca9e3875
This diff is collapsed.
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ ca9e3875
-------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- CERN (BE-CO-HT) -- Title : FMC ADC 100Ms/s SPEC top-level
-- Top level entity for Simple PCIe FMC Carrier -- Project : FMC ADC 100M 14B 4CHA gateware
-- http://www.ohwr.org/projects/spec -- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- -- File : spec_top_fmc_adc_100Ms.vhd
-- unit name: spec_top_fmc_adc_100Ms (spec_top_fmc_adc_100Ms.vhd) -- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- -- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- author: Matthieu Cattin (matthieu.cattin@cern.ch) -- Company : CERN (BE-CO-HT)
-- -- Created : 2011-02-24
-- date: 24-02-2011 -- Last update: 2016-04-19
-- -- Standard : VHDL'93/02
-- version: see sdb_meta_pkg.vhd -------------------------------------------------------------------------------
-- -- Description: Top entity of FMC ADC 100Ms/s design for Simple PCIe FMC
-- description: Top entity of FMC ADC 100Ms/s design for SPEC board. -- Carrier (SPEC). See also: http://www.ohwr.org/projects/spec
-- -------------------------------------------------------------------------------
-- dependencies: -- Copyright (c) 2011-2016 CERN (BE-CO-HT)
-- -------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it -- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the -- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your -- Free Software Foundation; either version 2.1 of the License, or (at your
...@@ -28,11 +27,16 @@ ...@@ -28,11 +27,16 @@
-- See the GNU Lesser General Public License for more details. You should have -- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this -- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: see git log. -- Revisions :
-------------------------------------------------------------------------------- -- Date Version Author
-- TODO: - -- 2016-04-20 4.1 Dimitrios Lampridis
-------------------------------------------------------------------------------- -- 2014-04-25 4.0 Matthieu Cattin
-- 2014-01-16 3.0 Matthieu Cattin
-- 2013-07-29 2.0 Matthieu Cattin
-- 2013-03-28 1.1 Matthieu Cattin
-- 2013-03-11 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_1164.all;
...@@ -522,8 +526,8 @@ begin ...@@ -522,8 +526,8 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_l_clk_buf : IBUFDS cmp_l_clk_buf : IBUFDS
generic map ( generic map (
DIFF_TERM => false, -- Differential Termination DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT") IOSTANDARD => "DEFAULT")
port map ( port map (
O => l_clk, -- Buffer output O => l_clk, -- Buffer output
...@@ -653,8 +657,8 @@ begin ...@@ -653,8 +657,8 @@ begin
generic map ( generic map (
g_num_masters => c_NUM_WB_SLAVES, g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS, g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true, g_registered => TRUE,
g_wraparound => true, g_wraparound => TRUE,
g_layout => c_INTERCONNECT_LAYOUT, g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS) g_sdb_addr => c_SDB_ADDRESS)
port map ( port map (
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ ca9e3875
-------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- CERN (BE-CO-HT) -- Title : FMC ADC 100Ms/s SVEC top-level
-- Top level entity for Simple VME FMC Carrier -- Project : FMC ADC 100M 14B 4CHA gateware
-- http://www.ohwr.org/projects/svec -- URL : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
-------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- -- File : svec_top_fmc_adc_100Ms.vhd
-- unit name: svec_top_fmc_adc_100Ms (svec_top_fmc_adc_100Ms.vhd) -- Author(s) : Matthieu Cattin <matthieu.cattin@cern.ch>
-- -- : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- author: Matthieu Cattin (matthieu.cattin@cern.ch) -- Company : CERN (BE-CO-HT)
-- -- Created : 2013-07-04
-- date: 04-07-2013 -- Last update: 2016-04-19
-- -- Standard : VHDL'93/02
-- version: see sdb_meta_pkg.vhd -------------------------------------------------------------------------------
-- -- Description: Top entity of FMC ADC 100Ms/s design for Simple VME FMC
-- description: Top entity of FMC ADC 100Ms/s design for SVEC board. -- Carrier (SVEC). See also: http://www.ohwr.org/projects/svec
-- -------------------------------------------------------------------------------
-- dependencies: -- Copyright (c) 2013-2016 CERN (BE-CO-HT)
-- -------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it -- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the -- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your -- Free Software Foundation; either version 2.1 of the License, or (at your
...@@ -28,11 +27,14 @@ ...@@ -28,11 +27,14 @@
-- See the GNU Lesser General Public License for more details. You should have -- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this -- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: see git log. -- Revisions :
-------------------------------------------------------------------------------- -- Date Version Author
-- TODO: - -- 2016-04-20 4.1 Dimitrios Lampridis
-------------------------------------------------------------------------------- -- 2014-04-25 4.0 Matthieu Cattin
-- 2014-01-16 3.0 Matthieu Cattin
-- 2013-07-29 1.0 Matthieu Cattin
-------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_1164.all;
...@@ -775,8 +777,8 @@ begin ...@@ -775,8 +777,8 @@ begin
generic map ( generic map (
g_num_masters => c_NUM_WB_SLAVES, g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS, g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true, g_registered => TRUE,
g_wraparound => true, g_wraparound => TRUE,
g_layout => c_INTERCONNECT_LAYOUT, g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS) g_sdb_addr => c_SDB_ADDRESS)
port map ( port map (
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment