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FMC ADC 100M 14b 4cha - Gateware
Commit d7d2bf24 authored by mcattin's avatar mcattin
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fix dir struct mistake 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@35 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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hdl/ise_project/_xmsgs/pn_parser.xmsgs deleted 100644 → 0
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hdl/ise_project/ddr3_ctrl_summary.html deleted 100644 → 0
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>ddr3_ctrl Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>spec_fmc_adc_100Ms.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>ddr3_ctrl</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
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</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/24/2011 - 10:27:57</center>
</BODY></HTML>
\ No newline at end of file
hdl/ise_project/iseconfig/ddr3_ctrl.xreport deleted 100644 → 0
View file @ b8854945
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hdl/ise_project/iseconfig/spec_fmc_adc_100Ms.projectmgr deleted 100644 → 0
View file @ b8854945
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hdl/ise_project/iseconfig/spec_top.xreport deleted 100644 → 0
View file @ b8854945
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hdl/ise_project/spec_fmc_adc_100Ms.gise deleted 100644 → 0
View file @ b8854945
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hdl/ise_project/spec_fmc_adc_100Ms.xise deleted 100644 → 0
View file @ b8854945
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<autoManagedFiles>
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<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/ise_project/spec_top_summary.html deleted 100644 → 0
View file @ b8854945
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>spec_top Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>spec_fmc_adc_100Ms.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>spec_top</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/24/2011 - 10:24:35</center>
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hdl/rtl/spec_top_fmc_adc_100Ms.vhd deleted 100644 → 0
View file @ b8854945
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_top_fmc_adc_100Ms (spec_top_fmc_adc_100Ms.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 24-02-2011
--
-- version: 1.0
--
-- description: Top entity of FMC ADC 100Ms/s design for SPEC board.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
generic(
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE");
port
(
-- Global ports
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
--clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
--clk_125m_pllref_n_i : in std_logic;
-- From GN4124 Local bus
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
LED_RED : out std_logic;
LED_GREEN : out std_logic;
-- DDR3 interface
DDR3_CAS_N : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_DQ : inout std_logic_vector(15 downto 0);
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_ZIO : inout std_logic;
DDR3_RZQ : inout std_logic
);
end spec_top;
architecture rtl of spec_top is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component gn4124_core
generic(
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
);
port
(
---------------------------------------------------------
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i : in std_logic;
-- P2L clock PLL locked
p2l_pll_locked : out std_logic;
-- Debug ouputs
debug_o : out std_logic_vector(7 downto 0);
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_cyc_o : out std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
wb_dat_i : in std_logic_vector((32*g_CSR_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_dat_i : in std_logic_vector((32*g_DMA_WB_SLAVES_NB)-1 downto 0); -- Data in
dma_ack_i : in std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_stall_i : in std_logic--_vector(g_DMA_WB_SLAVES_NB-1 downto 0) -- for pipelined Wishbone
);
end component; -- gn4124_core
component ddr3_ctrl
generic(
g_MEMCLK_PERIOD : integer := 3200; -- in ps
g_RST_ACT_LOW : integer := 1; -- 1=active low
g_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE";
g_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- BANK_ROW_COLUMN or ROW_BANK_COLUMN
g_NUM_DQ_PINS : integer := 16;
g_MEM_ADDR_WIDTH : integer := 14;
g_MEM_BANKADDR_WIDTH : integer := 3;
g_P0_MASK_SIZE : integer := 4;
g_P0_DATA_PORT_SIZE : integer := 32;
g_P1_MASK_SIZE : integer := 4;
g_P1_DATA_PORT_SIZE : integer := 32
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
calib_done : out std_logic;
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_odt_o : out std_logic;
ddr3_rst_n_o : out std_logic;
ddr3_cke_o : out std_logic;
ddr3_dm_o : out std_logic;
ddr3_udm_o : out std_logic;
ddr3_dqs_p_b : inout std_logic;
ddr3_dqs_n_b : inout std_logic;
ddr3_udqs_p_b : inout std_logic;
ddr3_udqs_n_b : inout std_logic;
ddr3_clk_p_o : out std_logic;
ddr3_clk_n_o : out std_logic;
ddr3_rzq_b : inout std_logic;
ddr3_zio_b : inout std_logic;
wb0_clk_i : in std_logic;
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
wb0_cyc_i : in std_logic;
wb0_stb_i : in std_logic;
wb0_we_i : in std_logic;
wb0_addr_i : in std_logic_vector(29 downto 0);
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_ack_o : out std_logic;
wb0_stall_o : out std_logic;
wb1_clk_i : in std_logic;
wb1_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_addr_i : in std_logic_vector(29 downto 0);
wb1_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb1_ack_o : out std_logic;
wb1_stall_o : out std_logic
);
end component ddr3_ctrl;
component gpio_regs
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
gpio_stat_i : in std_logic_vector(31 downto 0);
gpio_ctrl_1_o : out std_logic_vector(31 downto 0);
gpio_ctrl_2_o : out std_logic_vector(31 downto 0);
gpio_ctrl_3_o : out std_logic_vector(31 downto 0);
gpio_led_ctrl_o : out std_logic_vector(31 downto 0)
);
end component gpio_regs;
component monostable
generic(
g_INPUT_POLARITY : std_logic := '1'; --! trigger_i polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_POLARITY : std_logic := '1'; --! pulse_o polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_RETRIG : boolean := false; --! Retriggerable output monostable
g_OUTPUT_LENGTH : natural := 1 --! pulse_o lenght (in clk_i ticks)
);
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
trigger_i : in std_logic; --! Trigger input pulse
pulse_o : out std_logic --! Monostable output pulse
);
end component monostable;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 20;
constant c_CSR_WB_SLAVES_NB : integer := 3;
constant c_DMA_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_ADDR_WIDTH : integer := 26;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- System clock
signal sys_clk_in : std_logic;
signal sys_clk_50_buf : std_logic;
signal sys_clk_200_buf : std_logic;
signal sys_clk_50 : std_logic;
signal sys_clk_200 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L clock PLL status
signal p2l_pll_locked : std_logic;
-- Reset
signal rst : std_logic;
-- CSR wishbone bus
signal wb_adr : std_logic_vector(c_BAR0_APERTURE-log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal spi_wb_adr : std_logic_vector(4 downto 0);
signal ddr_wb_adr : std_logic_vector(29 downto 0);
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stall : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal ram_we : std_logic_vector(0 downto 0);
signal ddr_dma_adr : std_logic_vector(29 downto 0);
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(1 downto 0);
-- CSR whisbone slaves for test
signal gpio_stat : std_logic_vector(31 downto 0);
signal gpio_ctrl_1 : std_logic_vector(31 downto 0);
signal gpio_ctrl_2 : std_logic_vector(31 downto 0);
signal gpio_ctrl_3 : std_logic_vector(31 downto 0);
signal gpio_led_ctrl : std_logic_vector(31 downto 0);
-- DDR3
signal ddr3_calib_done : std_logic;
begin
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 50.000 MHz system clock
-- 200.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
cmp_sys_clk_buf : IBUFG
port map (
I => clk_20m_vcxo_i,
O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 20,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 40.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_50_buf,
CLKOUT1 => sys_clk_200_buf,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_clk_pll_locked,
RST => '0',
CLKFBIN => sys_clk_fb,
CLKIN => sys_clk_in);
cmp_clk_50_buf : BUFG
port map (
O => sys_clk_50,
I => sys_clk_50_buf);
cmp_clk_200_buf : BUFG
port map (
O => sys_clk_200,
I => sys_clk_200_buf);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
cmp_l_clk_buf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => l_clk, -- Buffer output
I => L_CLKp, -- Diff_p buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
rst <= not(L_RST_N);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
generic map (
g_BAR0_APERTURE => c_BAR0_APERTURE,
g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB,
g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB,
g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH)
port map(
---------------------------------------------------------
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i => L_RST_N,
-- P2L clock PLL locked
p2l_pll_locked => p2l_pll_locked,
-- Debug outputs
debug_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => irq_sources,
irq_p_i => irq_to_gn4124,
irq_p_o => GPIO(0),
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i => sys_clk_50,
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
---------------------------------------------------------
-- DMA wishbone interface (pipelined)
dma_clk_i => sys_clk_50,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_o,
dma_sel_o => dma_sel,
dma_stb_o => dma_stb,
dma_we_o => dma_we,
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_i,
dma_ack_i => dma_ack,
dma_stall_i => dma_stall);
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
-- 0 -> Not connected
-- 1 -> gpio registers
-- 2 -> DDR3 controller port0
------------------------------------------------------------------------------
cmp_gpio_regs : gpio_regs
port map(
rst_n_i => L_RST_N,
wb_clk_i => sys_clk_50,
wb_addr_i => wb_adr(2 downto 0),
wb_data_i => wb_dat_o,
wb_data_o => wb_dat_i(63 downto 32),
wb_cyc_i => wb_cyc(1),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(1),
gpio_stat_i => gpio_stat,
gpio_ctrl_1_o => gpio_ctrl_1,
gpio_ctrl_2_o => gpio_ctrl_2,
gpio_ctrl_3_o => gpio_ctrl_3,
gpio_led_ctrl_o => gpio_led_ctrl);
gpio_stat <= X"DEAD000"
& '0'
& ddr3_calib_done
& sys_clk_pll_locked
& p2l_pll_locked;
gen_irq_led : for I in 0 to 1 generate
cmp_irq_led : monostable
generic map(
g_INPUT_POLARITY => '1',
g_OUTPUT_POLARITY => '1',
g_OUTPUT_RETRIG => false,
g_OUTPUT_LENGTH => 5000000)
port map(
rst_n_i => L_RST_N,
clk_i => sys_clk_50,
trigger_i => irq_sources(I),
pulse_o => irq_sources_2_led(I));
end generate gen_irq_led;
LED_RED <= gpio_led_ctrl(0) or irq_sources_2_led(0);
LED_GREEN <= gpio_led_ctrl(1) or irq_sources_2_led(1);
------------------------------------------------------------------------------
-- Interrupt stuff
------------------------------------------------------------------------------
-- just forward irq pulses for test
irq_to_gn4124 <= irq_sources(1) or irq_sources(0);
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
------------------------------------------------------------------------------
cmp_ddr_ctrl : ddr3_ctrl
generic map(
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => g_SIMULATION,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP)
port map (
clk_i => ddr_clk,
rst_n_i => L_RST_N,
calib_done => ddr3_calib_done,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_clk_i => sys_clk_50, --'0',
wb0_sel_i => "1111",
wb0_cyc_i => wb_cyc(2), --'0',
wb0_stb_i => wb_stb, --'0',
wb0_we_i => wb_we, --'0',
wb0_addr_i => ddr_wb_adr, --X"0000000" & "00",
wb0_data_i => wb_dat_o, --X"00000000",
wb0_data_o => wb_dat_i(95 downto 64), --open,
wb0_ack_o => wb_ack(2), --open,
wb0_stall_o => open,
wb1_clk_i => sys_clk_50,
wb1_sel_i => "1111",
wb1_cyc_i => dma_cyc,
wb1_stb_i => dma_stb,
wb1_we_i => dma_we,
wb1_addr_i => ddr_dma_adr,
wb1_data_i => dma_dat_o,
wb1_data_o => dma_dat_i,
wb1_ack_o => dma_ack,
wb1_stall_o => dma_stall);
-- 32-bit word to byte address
ddr_wb_adr <= "0000000000" & wb_adr & "00";
-- 32-bit word to byte address
ddr_dma_adr <= dma_adr(27 downto 0) & "00";
------------------------------------------------------------------------------
-- Assign unused outputs
------------------------------------------------------------------------------
GPIO(1) <= '0';
end rtl;
hdl/spec_top_fmc_adc_100Ms.ucf deleted 100644 → 0
View file @ b8854945
#---------------------------------------------------------------------------------------------
# The IO Location Constraints
#---------------------------------------------------------------------------------------------
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
#NET "EN_FB_RX" LOC = D5;
#NET "EN_FB_RX" IOSTANDARD = "LVCMOS25";
#NET "EN_FB_TX" LOC = E5;
#NET "EN_FB_TX" IOSTANDARD = "LVCMOS25";
#NET "FB_N" LOC = A18;
#NET "FB_N" IOSTANDARD = "LVDS_25";
#NET "FB_P" LOC = B18;
#NET "FB_P" IOSTANDARD = "LVCMOS25";
#NET "clk_125m_pllref_n_i" LOC = F10;
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_p_i" LOC = G9;
#NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#NET "LA31_N" LOC = C18;
#NET "LA31_N" IOSTANDARD = "LVCMOS25";
#NET "LA31_P" LOC = D17;
#NET "LA31_P" IOSTANDARD = "LVCMOS25";
#NET "LA32_N" LOC = A20;
#NET "LA32_N" IOSTANDARD = "LVCMOS25";
#NET "LA32_P" LOC = B20;
#NET "LA32_P" IOSTANDARD = "LVCMOS25";
#NET "LA33_N" LOC = A19;
#NET "LA33_N" IOSTANDARD = "LVCMOS25";
#NET "LA33_P" LOC = C19;
#NET "LA33_P" IOSTANDARD = "LVCMOS25";
#NET "OE_SI57X" LOC = H13;
#NET "OE_SI57X" IOSTANDARD = "LVCMOS25";
#NET "PG_C2M" LOC = B2;
#NET "PG_C2M" IOSTANDARD = "LVCMOS25";
#NET "dac_cs1_n_o" LOC = A3;
#NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_cs2_n_o" LOC = B3;
#NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
#NET "dac_din_o" LOC = C4;
#NET "dac_din_o" IOSTANDARD = "LVCMOS25";
#NET "dac_sclk_o" LOC = A4;
#NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
#NET "SI57X_CLK_N" LOC = F15;
#NET "SI57X_CLK_N" IOSTANDARD = "LVDS_25";
#NET "SI57X_CLK_P" LOC = F14;
#NET "SI57X_CLK_P" IOSTANDARD = "LVDS_25";
#NET "TCK_TO_FMC" LOC = G8;
#NET "TCK_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TDI_TO_FMC" LOC = H11;
#NET "TDI_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "THERMO_ID" LOC = D4;
#NET "THERMO_ID" IOSTANDARD = "LVCMOS25";
#NET "TMS_TO_FMC" LOC = H10;
#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "PRSNT_M2C_L" LOC = A2;
#NET "PRSNT_M2C_L" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_FAULT" LOC = A17;
#NET "SFP_TX_FAULT" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_DISABLE" LOC = C17;
#NET "SFP_TX_DISABLE" IOSTANDARD = "LVCMOS25";
#NET "SFP_LOS" LOC = D18;
#NET "SFP_LOS" IOSTANDARD = "LVCMOS25";
#NET "TRST_TO_FMC" LOC = E6;
#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_P" LOC = E16;
#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
#NET "scl0_b" LOC = C5;
#NET "scl0_b" IOSTANDARD = "LVCMOS25";
#NET "FPGA_SCL" LOC = C5;
#NET "FPGA_SCL" IOSTANDARD = "LVCMOS25";
#NET "sda0_b" LOC = F8;
#NET "sda0_b" IOSTANDARD = "LVCMOS25";
#NET "FPGA_SDA" LOC = F8;
#NET "FPGA_SDA" IOSTANDARD = "LVCMOS25";
#NET "TDO_FROM_FMC" LOC = F9;
#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_N" LOC = F16;
#NET "CLK0_M2C_N" IOSTANDARD = "LVDS_25";
#NET "SFP_MOD_DEF1" LOC = F17;
#NET "SFP_MOD_DEF1" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF0" LOC = G15;
#NET "SFP_MOD_DEF0" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF2" LOC = G16;
#NET "SFP_MOD_DEF2" IOSTANDARD = "LVCMOS25";
#NET "SFP_RATE_SELECT" LOC = H14;
#NET "SFP_RATE_SELECT" IOSTANDARD = "LVCMOS25";
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L_CLKN" LOC = N19;
NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L_CLKP" LOC = P20;
NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = N22;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "GPIO[0]" LOC = U16;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "GPIO[1]" LOC = AB19;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
#NET "CLK1_M2C_P" LOC = L20;
#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
#NET "CLK1_M2C_N" LOC = L22;
#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
#NET "LA00_N" LOC = AB11;
#NET "LA00_N" IOSTANDARD = "LVCMOS25";
#NET "LA00_P" LOC = Y11;
#NET "LA00_P" IOSTANDARD = "LVCMOS25";
#NET "LA01_N" LOC = AB12;
#NET "LA01_N" IOSTANDARD = "LVCMOS25";
#NET "LA01_P" LOC = AA12;
#NET "LA01_P" IOSTANDARD = "LVCMOS25";
#NET "sda1_b" LOC = Y6;
#NET "sda1_b" IOSTANDARD = "LVCMOS25";
#NET "scl1_b" LOC = W6;
#NET "scl1_b" IOSTANDARD = "LVCMOS25";
#NET "LA02_N" LOC = Y6;
#NET "LA02_N" IOSTANDARD = "LVCMOS25";
#NET "LA02_P" LOC = W6;
#NET "LA02_P" IOSTANDARD = "LVCMOS25";
#NET "LA03_N" LOC = W8;
#NET "LA03_N" IOSTANDARD = "LVCMOS25";
#NET "LA03_P" LOC = V7;
#NET "LA03_P" IOSTANDARD = "LVCMOS25";
#NET "LA04_N" LOC = U8;
#NET "LA04_N" IOSTANDARD = "LVCMOS25";
#NET "LA04_P" LOC = T8;
#NET "LA04_P" IOSTANDARD = "LVCMOS25";
#NET "LA05_N" LOC = AB6;
#NET "LA05_N" IOSTANDARD = "LVCMOS25";
#NET "LA05_P" LOC = AA6;
#NET "LA05_P" IOSTANDARD = "LVCMOS25";
#NET "LA06_N" LOC = AB5;
#NET "LA06_N" IOSTANDARD = "LVCMOS25";
#NET "LA06_P" LOC = Y5;
#NET "LA06_P" IOSTANDARD = "LVCMOS25";
#NET "LA07_N" LOC = V9;
#NET "LA07_N" IOSTANDARD = "LVCMOS25";
#NET "LA07_P" LOC = U9;
#NET "LA07_P" IOSTANDARD = "LVCMOS25";
#NET "LA08_N" LOC = R8;
#NET "LA08_N" IOSTANDARD = "LVCMOS25";
#NET "LA08_P" LOC = R9;
#NET "LA08_P" IOSTANDARD = "LVCMOS25";
#NET "LA09_N" LOC = AB7;
#NET "LA09_N" IOSTANDARD = "LVCMOS25";
#NET "LA09_P" LOC = Y7;
#NET "LA09_P" IOSTANDARD = "LVCMOS25";
#NET "LA10_N" LOC = AB8;
#NET "LA10_N" IOSTANDARD = "LVCMOS25";
#NET "LA10_P" LOC = AA8;
#NET "LA10_P" IOSTANDARD = "LVCMOS25";
#NET "LA11_N" LOC = Y10;
#NET "LA11_N" IOSTANDARD = "LVCMOS25";
#NET "LA11_P" LOC = W10;
#NET "LA11_P" IOSTANDARD = "LVCMOS25";
#NET "LA12_N" LOC = U10;
#NET "LA12_N" IOSTANDARD = "LVCMOS25";
#NET "LA12_P" LOC = T10;
#NET "LA12_P" IOSTANDARD = "LVCMOS25";
#NET "LA13_N" LOC = AB9;
#NET "LA13_N" IOSTANDARD = "LVCMOS25";
#NET "LA13_P" LOC = Y9;
#NET "LA13_P" IOSTANDARD = "LVCMOS25";
#NET "LA14_N" LOC = AB4;
#NET "LA14_N" IOSTANDARD = "LVCMOS25";
#NET "LA14_P" LOC = AA4;
#NET "LA14_P" IOSTANDARD = "LVCMOS25";
#NET "LA15_N" LOC = W11;
#NET "LA15_N" IOSTANDARD = "LVCMOS25";
#NET "LA15_P" LOC = V11;
#NET "LA15_P" IOSTANDARD = "LVCMOS25";
#NET "LA16_N" LOC = AB15;
#NET "LA16_N" IOSTANDARD = "LVCMOS25";
#NET "LA16_P" LOC = Y15;
#NET "LA16_P" IOSTANDARD = "LVCMOS25";
#NET "LA17_N" LOC = AB13;
#NET "LA17_N" IOSTANDARD = "LVCMOS25";
#NET "LA17_P" LOC = Y13;
#NET "LA17_P" IOSTANDARD = "LVCMOS25";
#NET "LA18_N" LOC = U12;
#NET "LA18_N" IOSTANDARD = "LVCMOS25";
#NET "LA18_P" LOC = T12;
#NET "LA18_P" IOSTANDARD = "LVCMOS25";
#NET "LA19_N" LOC = Y12;
#NET "LA19_N" IOSTANDARD = "LVCMOS25";
#NET "LA19_P" LOC = W12;
#NET "LA19_P" IOSTANDARD = "LVCMOS25";
#NET "LA20_N" LOC = T11;
#NET "LA20_N" IOSTANDARD = "LVCMOS25";
#NET "LA20_P" LOC = R11;
#NET "LA20_P" IOSTANDARD = "LVCMOS25";
#NET "LA21_N" LOC = W13;
#NET "LA21_N" IOSTANDARD = "LVCMOS25";
#NET "LA21_P" LOC = V13;
#NET "LA21_P" IOSTANDARD = "LVCMOS25";
#NET "LA22_N" LOC = T14;
#NET "LA22_N" IOSTANDARD = "LVCMOS25";
#NET "LA22_P" LOC = R13;
#NET "LA22_P" IOSTANDARD = "LVCMOS25";
#NET "LA23_N" LOC = AB16;
#NET "LA23_N" IOSTANDARD = "LVCMOS25";
#NET "LA23_P" LOC = AA16;
#NET "LA23_P" IOSTANDARD = "LVCMOS25";
#NET "LA24_N" LOC = Y14;
#NET "LA24_N" IOSTANDARD = "LVCMOS25";
#NET "LA24_P" LOC = W14;
#NET "LA24_P" IOSTANDARD = "LVCMOS25";
#NET "LA25_N" LOC = U15;
#NET "LA25_N" IOSTANDARD = "LVCMOS25";
#NET "LA25_P" LOC = T15;
#NET "LA25_P" IOSTANDARD = "LVCMOS25";
#NET "LA26_N" LOC = AB17;
#NET "LA26_N" IOSTANDARD = "LVCMOS25";
#NET "LA26_P" LOC = Y17;
#NET "LA26_P" IOSTANDARD = "LVCMOS25";
#NET "LA27_N" LOC = AB18;
#NET "LA27_N" IOSTANDARD = "LVCMOS25";
#NET "LA27_P" LOC = AA18;
#NET "LA27_P" IOSTANDARD = "LVCMOS25";
#NET "LA28_N" LOC = W15;
#NET "LA28_N" IOSTANDARD = "LVCMOS25";
#NET "LA28_P" LOC = Y16;
#NET "LA28_P" IOSTANDARD = "LVCMOS25";
#NET "LA29_N" LOC = Y18;
#NET "LA29_N" IOSTANDARD = "LVCMOS25";
#NET "LA29_P" LOC = W17;
#NET "LA29_P" IOSTANDARD = "LVCMOS25";
#NET "LA30_N" LOC = W18;
#NET "LA30_N" IOSTANDARD = "LVCMOS25";
#NET "LA30_P" LOC = V17;
#NET "LA30_P" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SCL" LOC = AA14;
#NET "SI57X_SCL" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SDA" LOC = AB14;
#NET "SI57X_SDA" IOSTANDARD = "LVCMOS25";
NET "LED_RED" LOC = T6;
NET "LED_RED" IOSTANDARD = "LVCMOS15";
NET "LED_GREEN" LOC = Y3;
NET "LED_GREEN" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[0]" LOC = P5;
#NET "PCB_VER[0]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[1]" LOC = P4;
#NET "PCB_VER[1]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[2]" LOC = AA2;
#NET "PCB_VER[2]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[3]" LOC = AA1;
#NET "PCB_VER[3]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[4]" LOC = N6;
#NET "PCB_VER[4]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[5]" LOC = N7;
#NET "PCB_VER[5]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[6]" LOC = U4;
#NET "PCB_VER[6]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[7]" LOC = T4;
#NET "PCB_VER[7]" IOSTANDARD = "LVCMOS15";
NET "DDR3_CAS_N" LOC = M4;
NET "DDR3_CAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_CK_N" LOC = K3;
NET "DDR3_CK_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CK_P" LOC = K4;
NET "DDR3_CK_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CKE" LOC = F2;
NET "DDR3_CKE" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDM" LOC = N4;
NET "DDR3_LDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDQS_N" LOC = N1;
NET "DDR3_LDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_LDQS_P" LOC = N3;
NET "DDR3_LDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_ODT" LOC = L6;
NET "DDR3_ODT" IOSTANDARD = "SSTL15_II";
NET "DDR3_RAS_N" LOC = M5;
NET "DDR3_RAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RESET_N" LOC = E3;
NET "DDR3_RESET_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDM" LOC = P3;
NET "DDR3_UDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDQS_N" LOC = V1;
NET "DDR3_UDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_UDQS_P" LOC = V2;
NET "DDR3_UDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_WE_N" LOC = H2;
NET "DDR3_WE_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RZQ" LOC = K7;
NET "DDR3_RZQ" IOSTANDARD = "SSTL15_II";
NET "DDR3_ZIO" LOC = M7;
NET "DDR3_ZIO" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[0]" LOC = K2;
NET "DDR3_A[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[1]" LOC = K1;
NET "DDR3_A[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[2]" LOC = K5;
NET "DDR3_A[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[3]" LOC = M6;
NET "DDR3_A[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[4]" LOC = H3;
NET "DDR3_A[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[5]" LOC = M3;
NET "DDR3_A[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[6]" LOC = L4;
NET "DDR3_A[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[7]" LOC = K6;
NET "DDR3_A[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[8]" LOC = G3;
NET "DDR3_A[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[9]" LOC = G1;
NET "DDR3_A[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[10]" LOC = J4;
NET "DDR3_A[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[11]" LOC = E1;
NET "DDR3_A[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[12]" LOC = F1;
NET "DDR3_A[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[13]" LOC = J6;
NET "DDR3_A[13]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[14]" LOC = H5;
#NET "DDR3_A[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[0]" LOC = J3;
NET "DDR3_BA[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[1]" LOC = J1;
NET "DDR3_BA[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[2]" LOC = H1;
NET "DDR3_BA[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[0]" LOC = R3;
NET "DDR3_DQ[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[1]" LOC = R1;
NET "DDR3_DQ[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[2]" LOC = P2;
NET "DDR3_DQ[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[3]" LOC = P1;
NET "DDR3_DQ[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[4]" LOC = L3;
NET "DDR3_DQ[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[5]" LOC = L1;
NET "DDR3_DQ[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[6]" LOC = M2;
NET "DDR3_DQ[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[7]" LOC = M1;
NET "DDR3_DQ[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[8]" LOC = T2;
NET "DDR3_DQ[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[9]" LOC = T1;
NET "DDR3_DQ[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[10]" LOC = U3;
NET "DDR3_DQ[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[11]" LOC = U1;
NET "DDR3_DQ[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[12]" LOC = W3;
NET "DDR3_DQ[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[13]" LOC = W1;
NET "DDR3_DQ[13]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[14]" LOC = Y2;
NET "DDR3_DQ[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[15]" LOC = Y1;
NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
#---------------------------------------------------------------------------------------------
# IOBs
#---------------------------------------------------------------------------------------------
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
#---------------------------------------------------------------------------------------------
# Terminations
#---------------------------------------------------------------------------------------------
# DDR3
NET "DDR3_DQ[*]" IN_TERM = NONE;
NET "DDR3_LDQS_P" IN_TERM = NONE;
NET "DDR3_LDQS_N" IN_TERM = NONE;
NET "DDR3_UDQS_P" IN_TERM = NONE;
NET "DDR3_UDQS_N" IN_TERM = NONE;
#---------------------------------------------------------------------------------------------
# Clock constraints
#---------------------------------------------------------------------------------------------
# GN4124
NET "L_CLKp" TNM_NET = "l_clkp_grp";
TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 10 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 10 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 10 ns HIGH 50%;
# System clock
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i_grp";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i_grp" 50 ns HIGH 50%;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr_controller/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
#---------------------------------------------------------------------------------------------
# False Path
#---------------------------------------------------------------------------------------------
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr_controller/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr_controller/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr_controller/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
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