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FMC ADC 100M 14b 4cha - Gateware
Commit df8d5123 authored by Matthieu Cattin's avatar Matthieu Cattin
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syn: Svec firmware release 1.0

parent d742c0b8
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hdl/svec/rtl/sdb_meta_pkg.vhd
View file @ df8d5123
......@@ -53,14 +53,14 @@ package sdb_meta_pkg is
-- Top module name (string, 16 char)
syn_module_name => "svec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-320
syn_commit_id => "d8644900e0d9b8544a5e20da9d0567dd",
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "5a411766d8fdc519df7cf02a1832c76b",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130704",
syn_date => x"20130729",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
......@@ -69,8 +69,8 @@ package sdb_meta_pkg is
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"5c01a632", -- echo "svec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00010001", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130704", -- yyyymmdd
version => x"00010000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130729", -- yyyymmdd
name => "svec_fmcadc100m14b "));
......
hdl/svec/syn/svec_top_fmc_adc_100Ms.par 0 → 100644
View file @ df8d5123
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Mon Jul 29 12:34:43 2013
par -w -intstyle ise -ol high -mt off svec_top_fmc_adc_100Ms_map.ncd
svec_top_fmc_adc_100Ms.ncd svec_top_fmc_adc_100Ms.pcf
Constraints file: svec_top_fmc_adc_100Ms.pcf.
Loading device for application Rf_Device from file '6slx150t.nph' in environment /opt/Xilinx/13.3/ISE_DS/ISE/.
"svec_top_fmc_adc_100Ms" is an NCD, version 3.2, device xc6slx150t, package fgg900, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.20 2011-10-03".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 8,946 out of 184,304 4%
Number used as Flip Flops: 8,946
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 10,792 out of 92,152 11%
Number used as logic: 10,331 out of 92,152 11%
Number using O6 output only: 7,741
Number using O5 output only: 317
Number using O5 and O6: 2,273
Number used as ROM: 0
Number used as Memory: 27 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 27
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 18
Number used exclusively as route-thrus: 434
Number with same-slice register load: 417
Number with same-slice carry load: 17
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,077 out of 23,038 17%
Nummber of MUXCYs used: 2,192 out of 46,076 4%
Number of LUT Flip Flop pairs used: 12,538
Number with an unused Flip Flop: 4,665 out of 12,538 37%
Number with an unused LUT: 1,746 out of 12,538 13%
Number of fully used LUT-FF pairs: 6,127 out of 12,538 48%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 350 out of 540 64%
Number of LOCed IOBs: 350 out of 350 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 41 out of 268 15%
Number of RAMB8BWERs: 8 out of 536 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6%
Number used as BUFIO2FBs: 2
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 5
Number used as BUFGMUX: 2
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 36 out of 586 6%
Number used as ILOGIC2s: 0
Number used as ISERDES2s: 36
Number of IODELAY2/IODRP2/IODRP2_MCBs: 46 out of 586 7%
Number used as IODELAY2s: 0
Number used as IODRP2s: 2
Number used as IODRP2_MCBs: 44
Number of OLOGIC2/OSERDES2s: 94 out of 586 16%
Number used as OLOGIC2s: 0
Number used as OSERDES2s: 94
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 2 out of 8 25%
Number of BUFPLL_MCBs: 2 out of 4 50%
Number of DSP48A1s: 8 out of 180 4%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 2 out of 4 50%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 5 out of 6 83%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 22 secs
Finished initial Timing Analysis. REAL time: 23 secs
Starting Router
Phase 1 : 69454 unrouted; REAL time: 27 secs
Phase 2 : 60393 unrouted; REAL time: 1 mins
Phase 3 : 23648 unrouted; REAL time: 1 mins 52 secs
Phase 4 : 23989 unrouted; (Setup:2409, Hold:0, Component Switching Limit:0) REAL time: 2 mins 11 secs
Updating file: svec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:2775, Hold:0, Component Switching Limit:0) REAL time: 3 mins 35 secs
Phase 6 : 0 unrouted; (Setup:2273, Hold:0, Component Switching Limit:0) REAL time: 3 mins 43 secs
Updating file: svec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:363, Hold:0, Component Switching Limit:0) REAL time: 6 mins 36 secs
Phase 8 : 0 unrouted; (Setup:363, Hold:0, Component Switching Limit:0) REAL time: 6 mins 36 secs
Phase 9 : 0 unrouted; (Setup:363, Hold:0, Component Switching Limit:0) REAL time: 6 mins 36 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 41 secs
Total REAL time to Router completion: 6 mins 41 secs
Total CPU time to Router completion: 7 mins 1 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_1/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y10| No | 153 | 0.377 | 1.463 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X2Y1| No | 1820 | 0.352 | 1.436 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y12| No | 165 | 0.375 | 1.463 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_62_5 | BUFGMUX_X2Y2| No | 563 | 0.214 | 1.436 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c5 | | | | | |
| _mcb_drp_clk | BUFGMUX_X3Y13| No | 77 | 0.196 | 1.289 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c4 | | | | | |
| _mcb_drp_clk | BUFGMUX_X2Y3| No | 77 | 0.163 | 1.438 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_infrastructure_i | | | | | |
| nst/sys_clk_ibufg | BUFGMUX_X2Y9| No | 3 | 0.000 | 1.281 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_1/cmp_fmc_adc_100M | | | | | |
| s_core/clk_fb_buf | Local| | 19 | 0.000 | 2.017 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/clk_fb_buf | Local| | 19 | 0.000 | 2.017 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c5 | | | | | |
| _sysclk_2x | Local| | 35 | 0.576 | 1.953 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c4 | | | | | |
| _sysclk_2x | Local| | 35 | 0.571 | 1.948 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc5_wrapper_inst/mem | | | | | |
|c5_mcb_raw_wrapper_i | | | | | |
|nst/idelay_dqs_ioi_s | | | | | |
| | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc5_wrapper_inst/mem | | | | | |
|c5_mcb_raw_wrapper_i | | | | | |
|nst/idelay_dqs_ioi_m | | | | | |
| | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc5_wrapper_inst/mem | | | | | |
|c5_mcb_raw_wrapper_i | | | | | |
| nst/ioi_drp_clk | Local| | 22 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c5 | | | | | |
| _sysclk_2x_180 | Local| | 37 | 0.590 | 1.967 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc5_wrapper_inst/mem | | | | | |
|c5_mcb_raw_wrapper_i | | | | | |
|nst/idelay_udqs_ioi_ | | | | | |
| s | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank5/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank5_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc5_wrapper_inst/mem | | | | | |
|c5_mcb_raw_wrapper_i | | | | | |
|nst/idelay_udqs_ioi_ | | | | | |
| m | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_wrapper_inst/mem | | | | | |
|c4_mcb_raw_wrapper_i | | | | | |
| nst/ioi_drp_clk | Local| | 22 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/c4 | | | | | |
| _sysclk_2x_180 | Local| | 37 | 0.590 | 1.967 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_wrapper_inst/mem | | | | | |
|c4_mcb_raw_wrapper_i | | | | | |
|nst/idelay_dqs_ioi_s | | | | | |
| | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_wrapper_inst/mem | | | | | |
|c4_mcb_raw_wrapper_i | | | | | |
|nst/idelay_dqs_ioi_m | | | | | |
| | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_wrapper_inst/mem | | | | | |
|c4_mcb_raw_wrapper_i | | | | | |
|nst/idelay_udqs_ioi_ | | | | | |
| s | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl_bank4/c | | | | | |
|mp_ddr3_ctrl_wrapper | | | | | |
|/gen_svec_bank4_64b_ | | | | | |
|32b.cmp_ddr3_ctrl/me | | | | | |
|mc4_wrapper_inst/mem | | | | | |
|c4_mcb_raw_wrapper_i | | | | | |
|nst/idelay_udqs_ioi_ | | | | | |
| m | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 12
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapp | MINPERIOD | 0.001ns| 1.499ns| 0| 0
er_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m | | | | |
emc4_infrastructure_inst_clk_2x_180 | | | | |
= PERIOD TIMEGRP "cmp_ddr_ctrl | | | | |
_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_ban | | | | |
k4_64b_32b_cmp_ddr3_ctrl_memc4_infrastruc | | | | |
ture_inst_clk_2x_180" TS_ddr_clk_ | | | | |
buf / 2 PHASE 0.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapp | MINPERIOD | 0.001ns| 1.499ns| 0| 0
er_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m | | | | |
emc4_infrastructure_inst_clk_2x_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr_ctrl_b | | | | |
ank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4 | | | | |
_64b_32b_cmp_ddr3_ctrl_memc4_infrastructu | | | | |
re_inst_clk_2x_0" TS_ddr_clk_buf | | | | |
/ 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapp | MINPERIOD | 0.001ns| 1.499ns| 0| 0
er_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m | | | | |
emc5_infrastructure_inst_clk_2x_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr_ctrl_b | | | | |
ank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5 | | | | |
_64b_32b_cmp_ddr3_ctrl_memc5_infrastructu | | | | |
re_inst_clk_2x_0" TS_ddr_clk_buf | | | | |
/ 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapp | MINPERIOD | 0.001ns| 1.499ns| 0| 0
er_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m | | | | |
emc5_infrastructure_inst_clk_2x_180 | | | | |
= PERIOD TIMEGRP "cmp_ddr_ctrl | | | | |
_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_ban | | | | |
k5_64b_32b_cmp_ddr3_ctrl_memc5_infrastruc | | | | |
ture_inst_clk_2x_180" TS_ddr_clk_ | | | | |
buf / 2 PHASE 0.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
0Ms_core_dco_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100 | | | | |
Ms_core_dco_clk" TS_adc0_dco_n_i | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_10 | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
0Ms_core_dco_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_100 | | | | |
Ms_core_dco_clk" TS_adc1_dco_n_i | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.157ns| 7.843ns| 0| 0
clk_125_buf" TS_clk_20m_vcxo_i / 6.25 | HOLD | 0.352ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_10 | SETUP | 0.242ns| 7.758ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.399ns| | 0| 0
"cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_ | | | | |
100Ms_core_fs_clk_buf" TS_cmp_fmc | | | | |
_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | SETUP | 0.283ns| 7.717ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.381ns| | 0| 0
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_ | | | | |
100Ms_core_fs_clk_buf" TS_cmp_fmc | | | | |
_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_62_5_buf = PERIOD TIMEGRP "sys | SETUP | 0.366ns| 15.634ns| 0| 0
_clk_62_5_buf" TS_clk_20m_vcxo_i / | HOLD | 0.265ns| | 0| 0
3.125 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_ | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
buf" TS_clk_20m_vcxo_i / 16.6666667 | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_adc0_dco_n_i = PERIOD TIMEGRP "adc0_dc | MINPERIOD | 1.075ns| 0.925ns| 0| 0
o_n_i" 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_adc1_dco_n_i = PERIOD TIMEGRP "adc1_dc | MINPERIOD | 1.075ns| 0.925ns| 0| 0
o_n_i" 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | MINLOWPULSE | 30.000ns| 20.000ns| 0| 0
0m_vcxo_i" 50 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapp | SETUP | 4.665ns| 7.334ns| 0| 0
er_gen_svec_bank5_64b_32b_cmp_ddr3_ctrl_m | HOLD | 0.425ns| | 0| 0
emc5_infrastructure_inst_mcb_drp_clk_bufg | | | | |
_in = PERIOD TIMEGRP "cmp | | | | |
_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen | | | | |
_svec_bank5_64b_32b_cmp_ddr3_ctrl_memc5_i | | | | |
nfrastructure_inst_mcb_drp_clk_bufg_in" | | | | |
TS_ddr_clk_buf / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapp | SETUP | 4.967ns| 7.032ns| 0| 0
er_gen_svec_bank4_64b_32b_cmp_ddr3_ctrl_m | HOLD | 0.410ns| | 0| 0
emc4_infrastructure_inst_mcb_drp_clk_bufg | | | | |
_in = PERIOD TIMEGRP "cmp | | | | |
_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen | | | | |
_svec_bank4_64b_32b_cmp_ddr3_ctrl_memc4_i | | | | |
nfrastructure_inst_mcb_drp_clk_bufg_in" | | | | |
TS_ddr_clk_buf / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | N/A | N/A| N/A| N/A| N/A
0Ms_core_serdes_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_ | | | | |
100Ms_core_serdes_clk" TS_cmp_fmc | | | | |
_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_10 | N/A | N/A| N/A| N/A| N/A
0Ms_core_serdes_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_1_cmp_fmc_adc_ | | | | |
100Ms_core_serdes_clk" TS_cmp_fmc | | | | |
_adc_mezzanine_1_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_clk_20m_vcxo_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 2572497|
| TS_sys_clk_62_5_buf | 16.000ns| 15.634ns| N/A| 0| 0| 1754810| 0|
| TS_sys_clk_125_buf | 8.000ns| 7.843ns| N/A| 0| 0| 796755| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 20932|
| TS_cmp_ddr_ctrl_bank4_cmp_ddr| 12.000ns| 7.032ns| N/A| 0| 0| 10471| 0|
| 3_ctrl_wrapper_gen_svec_bank4| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc4_| | | | | | | |
| infrastructure_inst_mcb_drp_c| | | | | | | |
| lk_bufg_in | | | | | | | |
| TS_cmp_ddr_ctrl_bank4_cmp_ddr| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| 3_ctrl_wrapper_gen_svec_bank4| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc4_| | | | | | | |
| infrastructure_inst_clk_2x_18| | | | | | | |
| 0 | | | | | | | |
| TS_cmp_ddr_ctrl_bank4_cmp_ddr| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| 3_ctrl_wrapper_gen_svec_bank4| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc4_| | | | | | | |
| infrastructure_inst_clk_2x_0 | | | | | | | |
| TS_cmp_ddr_ctrl_bank5_cmp_ddr| 12.000ns| 7.334ns| N/A| 0| 0| 10461| 0|
| 3_ctrl_wrapper_gen_svec_bank5| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc5_| | | | | | | |
| infrastructure_inst_mcb_drp_c| | | | | | | |
| lk_bufg_in | | | | | | | |
| TS_cmp_ddr_ctrl_bank5_cmp_ddr| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| 3_ctrl_wrapper_gen_svec_bank5| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc5_| | | | | | | |
| infrastructure_inst_clk_2x_18| | | | | | | |
| 0 | | | | | | | |
| TS_cmp_ddr_ctrl_bank5_cmp_ddr| 1.500ns| 1.499ns| N/A| 0| 0| 0| 0|
| 3_ctrl_wrapper_gen_svec_bank5| | | | | | | |
| _64b_32b_cmp_ddr3_ctrl_memc5_| | | | | | | |
| infrastructure_inst_clk_2x_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_adc0_dco_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc0_dco_n_i | 2.000ns| 0.925ns| 1.929ns| 0| 0| 0| 16183|
| TS_cmp_fmc_adc_mezzanine_0_cmp| 2.000ns| 1.636ns| 1.929ns| 0| 0| 0| 16183|
| _fmc_adc_100Ms_core_dco_clk | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 8.000ns| 7.717ns| N/A| 0| 0| 16183| 0|
| p_fmc_adc_100Ms_core_fs_clk_b| | | | | | | |
| uf | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 1.000ns| N/A| N/A| 0| 0| 0| 0|
| p_fmc_adc_100Ms_core_serdes_c| | | | | | | |
| lk | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_adc1_dco_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc1_dco_n_i | 2.000ns| 0.925ns| 1.940ns| 0| 0| 0| 16183|
| TS_cmp_fmc_adc_mezzanine_1_cmp| 2.000ns| 1.636ns| 1.940ns| 0| 0| 0| 16183|
| _fmc_adc_100Ms_core_dco_clk | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_1_cm| 8.000ns| 7.758ns| N/A| 0| 0| 16183| 0|
| p_fmc_adc_100Ms_core_fs_clk_b| | | | | | | |
| uf | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_1_cm| 1.000ns| N/A| N/A| 0| 0| 0| 0|
| p_fmc_adc_100Ms_core_serdes_c| | | | | | | |
| lk | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 6 mins 49 secs
Total CPU time to PAR completion: 7 mins 9 secs
Peak Memory Usage: 605 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0
Writing design to file svec_top_fmc_adc_100Ms.ncd
PAR done!
hdl/svec/syn/svec_top_fmc_adc_100Ms.syr 0 → 100644
View file @ df8d5123
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/svec/syn/svec_top_fmc_adc_100Ms.twr 0 → 100644
View file @ df8d5123
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/svec/syn/svec_top_fmc_adc_100Ms_map.mrp 0 → 100644
View file @ df8d5123
Release 13.3 Map O.76xd (lin)
Xilinx Mapping Report File for Design 'svec_top_fmc_adc_100Ms'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr
off -lc off -power off -o svec_top_fmc_adc_100Ms_map.ncd
svec_top_fmc_adc_100Ms.ngd svec_top_fmc_adc_100Ms.pcf
Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jul 29 12:27:12 2013
Design Summary
--------------
Number of errors: 0
Number of warnings: 7
Slice Logic Utilization:
Number of Slice Registers: 8,946 out of 184,304 4%
Number used as Flip Flops: 8,946
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 10,792 out of 92,152 11%
Number used as logic: 10,331 out of 92,152 11%
Number using O6 output only: 7,741
Number using O5 output only: 317
Number using O5 and O6: 2,273
Number used as ROM: 0
Number used as Memory: 27 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 27
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 18
Number used exclusively as route-thrus: 434
Number with same-slice register load: 417
Number with same-slice carry load: 17
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,077 out of 23,038 17%
Nummber of MUXCYs used: 2,192 out of 46,076 4%
Number of LUT Flip Flop pairs used: 12,538
Number with an unused Flip Flop: 4,665 out of 12,538 37%
Number with an unused LUT: 1,746 out of 12,538 13%
Number of fully used LUT-FF pairs: 6,127 out of 12,538 48%
Number of unique control sets: 347
Number of slice register sites lost
to control set restrictions: 777 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 350 out of 540 64%
Number of LOCed IOBs: 350 out of 350 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 41 out of 268 15%
Number of RAMB8BWERs: 8 out of 536 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6%
Number used as BUFIO2FBs: 2
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 5
Number used as BUFGMUX: 2
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 36 out of 586 6%
Number used as ILOGIC2s: 0
Number used as ISERDES2s: 36
Number of IODELAY2/IODRP2/IODRP2_MCBs: 46 out of 586 7%
Number used as IODELAY2s: 0
Number used as IODRP2s: 2
Number used as IODRP2_MCBs: 44
Number of OLOGIC2/OSERDES2s: 94 out of 586 16%
Number used as OLOGIC2s: 0
Number used as OSERDES2s: 94
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 2 out of 8 25%
Number of BUFPLL_MCBs: 2 out of 4 50%
Number of DSP48A1s: 8 out of 180 4%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 2 out of 4 50%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 5 out of 6 83%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.02
Peak Memory Usage: 622 MB
Total REAL time to MAP completion: 7 mins 24 secs
Total CPU time to MAP completion (all processors): 7 mins 40 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:MapLib:701 - Signal ddr0_zio_b connected to top level port ddr0_zio_b
has been removed.
WARNING:MapLib:701 - Signal ddr1_zio_b connected to top level port ddr1_zio_b
has been removed.
WARNING:MapLib:41 - All members of TNM group
"cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctr
l_memc4_infrastructure_inst_clk0_bufg_in" have been optimized out of the
design.
WARNING:MapLib:41 - All members of TNM group
"cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctr
l_memc5_infrastructure_inst_clk0_bufg_in" have been optimized out of the
design.
WARNING:MapLib:50 - The period specification
"TS_cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_
ctrl_memc4_infrastructure_inst_clk0_bufg_in" has been discarded because the
group
"cmp_ddr_ctrl_bank4_cmp_ddr3_ctrl_wrapper_gen_svec_bank4_64b_32b_cmp_ddr3_ctr
l_memc4_infrastructure_inst_clk0_bufg_in" has been optimized away.
WARNING:MapLib:50 - The period specification
"TS_cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_
ctrl_memc5_infrastructure_inst_clk0_bufg_in" has been discarded because the
group
"cmp_ddr_ctrl_bank5_cmp_ddr3_ctrl_wrapper_gen_svec_bank5_64b_32b_cmp_ddr3_ctr
l_memc5_infrastructure_inst_clk0_bufg_in" has been optimized away.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run.
INFO:LIT:243 - Logical network
cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl
/memc4_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 6 more times for the following
(max. 5 shown):
cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl
/memc5_infrastructure_inst/rst0_sync_r<24>,
N1685,
N1687,
N1691,
N1693
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
60 block(s) removed
2 block(s) optimized away
60 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<24>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_24" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/clk0_bufg" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/U_BUFG_CLK0" (CKBUF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/clk0_bufg_in" is loadless and has been removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<23>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_23" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<22>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_22" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<21>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_21" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<20>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_20" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<19>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_19" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<18>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_18" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<17>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_17" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<16>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_16" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<15>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_15" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<14>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_14" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<13>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_13" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<12>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_12" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<11>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_11" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<10>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_10" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<9>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_9" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<8>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_8" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<7>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_7" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<6>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_6" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<5>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_5" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<4>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_4" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<3>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_3" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<2>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_2" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<1>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_1" (FF) removed.
The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r<0>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst0_sync_r_0" (FF) removed.
*The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst_tmp" is loadless and has been removed.
* Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/rst_tmp1" (ROM) removed.
* The signal
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/syn_clk0_powerup_pll_locked" is loadless and has been
removed.
* Loadless block
"cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl/m
emc4_infrastructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<24>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_24" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/clk0_bufg" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/U_BUFG_CLK0" (CKBUF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/clk0_bufg_in" is loadless and has been removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<23>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_23" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<22>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_22" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<21>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_21" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<20>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_20" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<19>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_19" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<18>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_18" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<17>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_17" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<16>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_16" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<15>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_15" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<14>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_14" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<13>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_13" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<12>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_12" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<11>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_11" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<10>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_10" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<9>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_9" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<8>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_8" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<7>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_7" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<6>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_6" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<5>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_5" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<4>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_4" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<3>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_3" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<2>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_2" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<1>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_1" (FF) removed.
The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r<0>" is loadless and has been removed.
Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst0_sync_r_0" (FF) removed.
*The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst_tmp" is loadless and has been removed.
* Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/rst_tmp1" (ROM) removed.
* The signal
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/syn_clk0_powerup_pll_locked" is loadless and has been
removed.
* Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
The trimmed logic reported below is either:
1. part of a cycle
2. part of disabled logic
3. a side-effect of other trimmed logic
The signal "ddr0_zio_b" is unused and has been removed.
Unused block "ddr0_zio_b_OBUFT" (TRI) removed.
The signal "ddr1_zio_b" is unused and has been removed.
Unused block "ddr1_zio_b_OBUFT" (TRI) removed.
Unused block "ddr0_zio_b" (PAD) removed.
Unused block "ddr1_zio_b" (PAD) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| adc0_dco_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_dco_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_ext_trigger_n_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| adc0_ext_trigger_p_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| adc0_fr_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_fr_p_i | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_gpio_dac_clr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_led_acq_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_led_trig_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_si570_oe_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch1_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch2_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch3_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_gpio_ssr_ch4_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_one_wire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc0_outa_n_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_n_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_n_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_n_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outa_p_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outa_p_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outa_p_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outa_p_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_n_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_n_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_n_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_n_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc0_outb_p_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_p_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_p_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_outb_p_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc0_si570_scl_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc0_si570_sda_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_adc_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac1_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac2_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac3_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_cs_dac4_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_din_i | IOB | INPUT | LVCMOS25 | | | | | | |
| adc0_spi_dout_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc0_spi_sck_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_dco_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_dco_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_ext_trigger_n_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| adc1_ext_trigger_p_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| adc1_fr_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_fr_p_i | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_gpio_dac_clr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_led_acq_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_led_trig_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_si570_oe_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch1_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch2_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch3_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_gpio_ssr_ch4_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_one_wire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc1_outa_n_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outa_n_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outa_n_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outa_n_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outa_p_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outa_p_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outa_p_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outa_p_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outb_n_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outb_n_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outb_n_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outb_n_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| adc1_outb_p_i<0> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outb_p_i<1> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outb_p_i<2> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_outb_p_i<3> | IOB | INPUT | LVDS_25 | TRUE | | | ISERDES | | |
| adc1_si570_scl_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc1_si570_sda_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_cs_adc_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_cs_dac1_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_cs_dac2_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_cs_dac3_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_cs_dac4_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_din_i | IOB | INPUT | LVCMOS25 | | | | | | |
| adc1_spi_dout_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| adc1_spi_sck_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| carrier_one_wire_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| carrier_scl_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| carrier_sda_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| clk_20m_vcxo_i | IOB | INPUT | LVCMOS33 | | | | | | |
| ddr0_a_o<0> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<1> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<2> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<3> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<4> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<5> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<6> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<7> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<8> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<9> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<10> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<11> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<12> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_a_o<13> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_ba_o<0> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_ba_o<1> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_ba_o<2> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_cas_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_ck_n_o | IOB | OUTPUT | DIFF_SSTL15_II | | | | OSERDES | | |
| ddr0_ck_p_o | IOB | OUTPUT | DIFF_SSTL15_II | | | | OSERDES | | |
| ddr0_cke_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_dq_b<0> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<1> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<2> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<3> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<4> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<5> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<6> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<7> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<8> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<9> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<10> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<11> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<12> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<13> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<14> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_dq_b<15> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr0_ldm_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| ddr0_ldqs_n_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLUP | |
| ddr0_ldqs_p_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLDOWN | |
| ddr0_odt_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_ras_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_reset_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr0_rzq_b | IOB | BIDIR | SSTL15_II | | | | | | DEFAULT |
| ddr0_udm_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| ddr0_udqs_n_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLUP | |
| ddr0_udqs_p_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLDOWN | |
| ddr0_we_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<0> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<1> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<2> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<3> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<4> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<5> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<6> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<7> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<8> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<9> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<10> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<11> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<12> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_a_o<13> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_ba_o<0> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_ba_o<1> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_ba_o<2> | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_cas_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_ck_n_o | IOB | OUTPUT | DIFF_SSTL15_II | | | | OSERDES | | |
| ddr1_ck_p_o | IOB | OUTPUT | DIFF_SSTL15_II | | | | OSERDES | | |
| ddr1_cke_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_dq_b<0> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<1> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<2> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<3> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<4> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<5> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<6> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<7> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<8> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<9> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<10> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<11> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<12> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<13> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<14> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_dq_b<15> | IOB | BIDIR | SSTL15_II | | | | | | |
| ddr1_ldm_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| ddr1_ldqs_n_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLUP | |
| ddr1_ldqs_p_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLDOWN | |
| ddr1_odt_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_ras_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_reset_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| ddr1_rzq_b | IOB | BIDIR | SSTL15_II | | | | | | DEFAULT |
| ddr1_udm_o | IOB | OUTPUT | SSTL15_II | | | | | | |
| ddr1_udqs_n_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLUP | |
| ddr1_udqs_p_b | IOB | BIDIR | DIFF_SSTL15_II | | | | | PULLDOWN | |
| ddr1_we_n_o | IOB | OUTPUT | SSTL15_II | | | | OSERDES | | |
| fmc0_prsnt_m2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| fmc0_scl_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| fmc0_sda_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| fmc1_prsnt_m2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| fmc1_scl_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| fmc1_sda_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_oen_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_oen_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pcbrev_i<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| pcbrev_i<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| pcbrev_i<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| pcbrev_i<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| pcbrev_i<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| rst_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_addr_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_dir_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_oe_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_am_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_am_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_am_i<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_am_i<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_am_i<4> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_am_i<5> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_as_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_berr_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<0> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_b<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_dir_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_data_oe_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_ds_n_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ds_n_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_dtack_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_dtack_oe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_ga_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ga_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ga_i<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ga_i<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ga_i<4> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_ga_i<5> | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_iack_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_iackin_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_iackout_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<4> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<5> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<6> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_irq_n_o<7> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_lword_n_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_retry_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_retry_oe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| vme_sysreset_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_write_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
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