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FMC ADC 100M 14b 4cha - Gateware
Commit e084c507 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Migrate ADC CSR to Cheby

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== Memory map summary
FMC ADC 100MS/s core registers
|===
|HW address | Type | Name | HDL name
|0x000
|REG
|ctl
|ctl
|0x004
|REG
|sta
|sta
|0x008
|REG
|trig_stat
|trig_stat
|0x00c
|REG
|trig_en
|trig_en
|0x010
|REG
|trig_pol
|trig_pol
|0x014
|REG
|ext_trig_dly
|ext_trig_dly
|0x018
|REG
|sw_trig
|sw_trig
|0x01c
|REG
|shots
|shots
|0x020
|REG
|multi_depth
|multi_depth
|0x024
|REG
|trig_pos
|trig_pos
|0x028
|REG
|fs_freq
|fs_freq
|0x02c
|REG
|undersample
|undersample
|0x030
|REG
|pre_samples
|pre_samples
|0x034
|REG
|post_samples
|post_samples
|0x038
|REG
|samples_cnt
|samples_cnt
|0x080
|REG
|ch1_ctl
|ch1_ctl
|0x084
|REG
|ch1_sta
|ch1_sta
|0x088
|REG
|ch1_calib
|ch1_calib
|0x08c
|REG
|ch1_sat
|ch1_sat
|0x090
|REG
|ch1_trig_thres
|ch1_trig_thres
|0x094
|REG
|ch1_trig_dly
|ch1_trig_dly
|0x0c0
|REG
|ch2_ctl
|ch2_ctl
|0x0c4
|REG
|ch2_sta
|ch2_sta
|0x0c8
|REG
|ch2_calib
|ch2_calib
|0x0cc
|REG
|ch2_sat
|ch2_sat
|0x0d0
|REG
|ch2_trig_thres
|ch2_trig_thres
|0x0d4
|REG
|ch2_trig_dly
|ch2_trig_dly
|0x100
|REG
|ch3_ctl
|ch3_ctl
|0x104
|REG
|ch3_sta
|ch3_sta
|0x108
|REG
|ch3_calib
|ch3_calib
|0x10c
|REG
|ch3_sat
|ch3_sat
|0x110
|REG
|ch3_trig_thres
|ch3_trig_thres
|0x114
|REG
|ch3_trig_dly
|ch3_trig_dly
|0x140
|REG
|ch4_ctl
|ch4_ctl
|0x144
|REG
|ch4_sta
|ch4_sta
|0x148
|REG
|ch4_calib
|ch4_calib
|0x14c
|REG
|ch4_sat
|ch4_sat
|0x150
|REG
|ch4_trig_thres
|ch4_trig_thres
|0x154
|REG
|ch4_trig_dly
|ch4_trig_dly
|===
== Registers description
=== ctl
[horizontal]
HDL name:: ctl
address:: 0x0
block offset:: 0x0
access mode:: rw
Control register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
s| clear_trig_stat
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
s| acq_led
s| trig_led
s| test_data_en
s| man_bitslip
s| offset_dac_clr_n
s| fmc_clk_oe
2+s| fsm_cmd[1:0]
|===
fsm_cmd:: 1: ACQ_START (start acquisition, only when FSM is idle)
2: ACQ_STOP (stop acquisition, anytime)
fmc_clk_oe:: FMC Si750 output enable
offset_dac_clr_n:: Offset DACs clear (active low)
man_bitslip:: Manual serdes bitslip (ignore on read)
test_data_en:: Write the DDR RAM address counter value instead of ADC data to DDR.
Note that no timetags are appended at the end of test data.
trig_led:: Manual control of the front panel TRIG LED
acq_led:: Manual control of the front panel ACQ LED
clear_trig_stat:: Write 1 to clear the last trigger status register. Auto-resets to zero.
=== sta
[horizontal]
HDL name:: sta
address:: 0x4
block offset:: 0x4
access mode:: ro
Status register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
| -
s| acq_cfg
s| serdes_synced
s| serdes_pll
3+s| fsm[2:0]
|===
fsm:: States:
0: illegal
1: IDLE
2: PRE_TRIG
3: WAIT_TRIG
4: POST_TRIG
5: TRIG_TAG
6: DECR_SHOT
7: illegal
serdes_pll:: Sampling clock recovery PLL.
0: not locked
1: locked
serdes_synced:: 0: bitslip in progress
1: serdes synchronized
acq_cfg:: 0: Unauthorised acquisition configuration (will prevent acquisition to start)
1: Valid acquisition configuration
- Shot number > 0
- Post-trigger sample > 0
=== trig_stat
[horizontal]
HDL name:: trig_stat
address:: 0x8
block offset:: 0x8
access mode:: ro
Trigger status
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
s| ch4
s| ch3
s| ch2
s| ch1
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
| -
| -
s| time
| -
| -
s| sw
s| ext
|===
ext:: 0: not triggered
1: triggered
sw:: 0: not triggered
1: triggered
time:: 0: not triggered
1: triggered
ch1:: 0: not triggered
1: triggered
ch2:: 0: not triggered
1: triggered
ch3:: 0: not triggered
1: triggered
ch4:: 0: not triggered
1: triggered
=== trig_en
[horizontal]
HDL name:: trig_en
address:: 0xc
block offset:: 0xc
access mode:: rw
Trigger enable
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
s| fwd_ch4
s| fwd_ch3
s| fwd_ch2
s| fwd_ch1
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
s| fwd_ext
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
s| ch4
s| ch3
s| ch2
s| ch1
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
| -
s| alt_time
s| time
| -
| -
s| sw
s| ext
|===
ext:: 0: disable
1: enable
sw:: 0: disable
1: enable
time:: 0: disable
1: enable
alt_time:: 0: disable
1: enable
ch1:: 0: disable
1: enable
ch2:: 0: disable
1: enable
ch3:: 0: disable
1: enable
ch4:: 0: disable
1: enable
fwd_ext:: 0: disable
1: enable
fwd_ch1:: 0: disable
1: enable
fwd_ch2:: 0: disable
1: enable
fwd_ch3:: 0: disable
1: enable
fwd_ch4:: 0: disable
1: enable
=== trig_pol
[horizontal]
HDL name:: trig_pol
address:: 0x10
block offset:: 0x10
access mode:: rw
Trigger polarity
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
s| ch4
s| ch3
s| ch2
s| ch1
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
| -
| -
| -
| -
| -
| -
s| ext
|===
ext:: 0: positive edge/slope
1: negative edge/slope
ch1:: 0: positive edge/slope
1: negative edge/slope
ch2:: 0: positive edge/slope
1: negative edge/slope
ch3:: 0: positive edge/slope
1: negative edge/slope
ch4:: 0: positive edge/slope
1: negative edge/slope
=== ext_trig_dly
[horizontal]
HDL name:: ext_trig_dly
address:: 0x14
block offset:: 0x14
access mode:: rw
External trigger delay
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| ext_trig_dly[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| ext_trig_dly[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| ext_trig_dly[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| ext_trig_dly[7:0]
|===
=== sw_trig
[horizontal]
HDL name:: sw_trig
address:: 0x18
block offset:: 0x18
access mode:: wo
Software trigger
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| sw_trig[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| sw_trig[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| sw_trig[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| sw_trig[7:0]
|===
=== shots
[horizontal]
HDL name:: shots
address:: 0x1c
block offset:: 0x1c
access mode:: rw
Number of shots
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| remain[15:8]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| remain[7:0]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| nbr[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| nbr[7:0]
|===
nbr:: Number of shots required in multi-shot mode, set to one for single-shot mode.
remain:: Counts the number of remaining shots to acquire.
=== multi_depth
[horizontal]
HDL name:: multi_depth
address:: 0x20
block offset:: 0x20
access mode:: ro
Multi-shot sample depth register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| multi_depth[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| multi_depth[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| multi_depth[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| multi_depth[7:0]
|===
=== trig_pos
[horizontal]
HDL name:: trig_pos
address:: 0x24
block offset:: 0x24
access mode:: ro
Trigger address register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| trig_pos[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| trig_pos[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| trig_pos[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| trig_pos[7:0]
|===
=== fs_freq
[horizontal]
HDL name:: fs_freq
address:: 0x28
block offset:: 0x28
access mode:: ro
Sampling clock frequency
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| fs_freq[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| fs_freq[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| fs_freq[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| fs_freq[7:0]
|===
=== undersample
[horizontal]
HDL name:: undersample
address:: 0x2c
block offset:: 0x2c
access mode:: rw
Undersampling ratio
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| undersample[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| undersample[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| undersample[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| undersample[7:0]
|===
=== pre_samples
[horizontal]
HDL name:: pre_samples
address:: 0x30
block offset:: 0x30
access mode:: rw
Pre-trigger samples
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| pre_samples[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| pre_samples[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| pre_samples[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| pre_samples[7:0]
|===
=== post_samples
[horizontal]
HDL name:: post_samples
address:: 0x34
block offset:: 0x34
access mode:: rw
Post-trigger samples
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| post_samples[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| post_samples[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| post_samples[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| post_samples[7:0]
|===
=== samples_cnt
[horizontal]
HDL name:: samples_cnt
address:: 0x38
block offset:: 0x38
access mode:: ro
Samples counter
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| samples_cnt[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| samples_cnt[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| samples_cnt[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| samples_cnt[7:0]
|===
=== ch1_ctl
[horizontal]
HDL name:: ch1_ctl
address:: 0x80
block offset:: 0x80
access mode:: rw
Channel 1 control register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
7+s| ssr[6:0]
|===
ssr:: Controls input voltage range, termination and DC offset error calibration
0x23: 100mV range
0x11: 1V range
0x45: 10V range
0x00: Open input
0x42: 100mV range calibration
0x40: 1V range calibration
0x44: 10V range calibration
Bit3 is indepandant of the others and enables the 50ohms termination.
=== ch1_sta
[horizontal]
HDL name:: ch1_sta
address:: 0x84
block offset:: 0x84
access mode:: ro
Channel 1 status register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| val[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Current ADC raw value. The format is binary two\'s complement.
=== ch1_calib
[horizontal]
HDL name:: ch1_calib
address:: 0x88
block offset:: 0x88
access mode:: rw
Channel 1 calibration register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| offset[15:8]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| offset[7:0]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| gain[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| gain[7:0]
|===
gain:: Gain applied to all data coming from the ADC.
Fixed point format:
Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
offset:: Offset applied to all data coming from the ADC. The format is binary two\'s complement.
=== ch1_sat
[horizontal]
HDL name:: ch1_sat
address:: 0x8c
block offset:: 0x8c
access mode:: rw
Channel 1 saturation register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
7+s| val[14:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
=== ch1_trig_thres
[horizontal]
HDL name:: ch1_trig_thres
address:: 0x90
block offset:: 0x90
access mode:: rw
Channel 1 trigger threshold configuration register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| hyst[15:8]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| hyst[7:0]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| val[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Treated as binary two\'s complement and compared to raw ADC data.
hyst:: Configures the internal trigger threshold hysteresis.
The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
=== ch1_trig_dly
[horizontal]
HDL name:: ch1_trig_dly
address:: 0x94
block offset:: 0x94
access mode:: rw
Channel 1 trigger delay
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| ch1_trig_dly[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| ch1_trig_dly[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| ch1_trig_dly[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| ch1_trig_dly[7:0]
|===
=== ch2_ctl
[horizontal]
HDL name:: ch2_ctl
address:: 0xc0
block offset:: 0xc0
access mode:: rw
Channel 2 control register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
7+s| ssr[6:0]
|===
ssr:: Controls input voltage range, termination and DC offset error calibration
0x23: 100mV range
0x11: 1V range
0x45: 10V range
0x00: Open input
0x42: 100mV range calibration
0x40: 1V range calibration
0x44: 10V range calibration
Bit3 is indepandant of the others and enables the 50ohms termination.
=== ch2_sta
[horizontal]
HDL name:: ch2_sta
address:: 0xc4
block offset:: 0xc4
access mode:: ro
Channel 2 status register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| val[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Current ADC raw value. The format is binary two\'s complement.
=== ch2_calib
[horizontal]
HDL name:: ch2_calib
address:: 0xc8
block offset:: 0xc8
access mode:: rw
Channel 2 calibration register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| offset[15:8]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| offset[7:0]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| gain[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| gain[7:0]
|===
gain:: Gain applied to all data coming from the ADC.
Fixed point format:
Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
offset:: Offset applied to all data coming from the ADC. The format is binary two\'s complement.
=== ch2_sat
[horizontal]
HDL name:: ch2_sat
address:: 0xcc
block offset:: 0xcc
access mode:: rw
Channel 2 saturation register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
7+s| val[14:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
=== ch2_trig_thres
[horizontal]
HDL name:: ch2_trig_thres
address:: 0xd0
block offset:: 0xd0
access mode:: rw
Channel 2 trigger threshold configuration register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| hyst[15:8]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| hyst[7:0]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| val[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Treated as binary two\'s complement and compared to raw ADC data.
hyst:: Configures the internal trigger threshold hysteresis.
The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
=== ch2_trig_dly
[horizontal]
HDL name:: ch2_trig_dly
address:: 0xd4
block offset:: 0xd4
access mode:: rw
Channel 2 trigger delay
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| ch2_trig_dly[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| ch2_trig_dly[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| ch2_trig_dly[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| ch2_trig_dly[7:0]
|===
=== ch3_ctl
[horizontal]
HDL name:: ch3_ctl
address:: 0x100
block offset:: 0x100
access mode:: rw
Channel 3 control register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
7+s| ssr[6:0]
|===
ssr:: Controls input voltage range, termination and DC offset error calibration
0x23: 100mV range
0x11: 1V range
0x45: 10V range
0x00: Open input
0x42: 100mV range calibration
0x40: 1V range calibration
0x44: 10V range calibration
Bit3 is indepandant of the others and enables the 50ohms termination.
=== ch3_sta
[horizontal]
HDL name:: ch3_sta
address:: 0x104
block offset:: 0x104
access mode:: ro
Channel 3 status register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| val[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Current ADC raw value. The format is binary two\'s complement.
=== ch3_calib
[horizontal]
HDL name:: ch3_calib
address:: 0x108
block offset:: 0x108
access mode:: rw
Channel 3 calibration register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| offset[15:8]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| offset[7:0]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| gain[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| gain[7:0]
|===
gain:: Gain applied to all data coming from the ADC.
Fixed point format:
Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
offset:: Offset applied to all data coming from the ADC. The format is binary two\'s complement.
=== ch3_sat
[horizontal]
HDL name:: ch3_sat
address:: 0x10c
block offset:: 0x10c
access mode:: rw
Channel 3 saturation register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
7+s| val[14:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
=== ch3_trig_thres
[horizontal]
HDL name:: ch3_trig_thres
address:: 0x110
block offset:: 0x110
access mode:: rw
Channel 3 trigger threshold configuration register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| hyst[15:8]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| hyst[7:0]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| val[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Treated as binary two\'s complement and compared to raw ADC data.
hyst:: Configures the internal trigger threshold hysteresis.
The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
=== ch3_trig_dly
[horizontal]
HDL name:: ch3_trig_dly
address:: 0x114
block offset:: 0x114
access mode:: rw
Channel 3 trigger delay
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| ch3_trig_dly[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| ch3_trig_dly[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| ch3_trig_dly[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| ch3_trig_dly[7:0]
|===
=== ch4_ctl
[horizontal]
HDL name:: ch4_ctl
address:: 0x140
block offset:: 0x140
access mode:: rw
Channel 4 control register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
7+s| ssr[6:0]
|===
ssr:: Controls input voltage range, termination and DC offset error calibration
0x23: 100mV range
0x11: 1V range
0x45: 10V range
0x00: Open input
0x42: 100mV range calibration
0x40: 1V range calibration
0x44: 10V range calibration
Bit3 is indepandant of the others and enables the 50ohms termination.
=== ch4_sta
[horizontal]
HDL name:: ch4_sta
address:: 0x144
block offset:: 0x144
access mode:: ro
Channel 4 status register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| val[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Current ADC raw value. The format is binary two\'s complement.
=== ch4_calib
[horizontal]
HDL name:: ch4_calib
address:: 0x148
block offset:: 0x148
access mode:: rw
Channel 4 gain calibration register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| offset[15:8]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| offset[7:0]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| gain[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| gain[7:0]
|===
gain:: Gain applied to all data coming from the ADC.
Fixed point format:
Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
offset:: Offset applied to all data coming from the ADC. The format is binary two\'s complement.
=== ch4_sat
[horizontal]
HDL name:: ch4_sat
address:: 0x14c
block offset:: 0x14c
access mode:: rw
Channel 4 saturation register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
7+s| val[14:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
=== ch4_trig_thres
[horizontal]
HDL name:: ch4_trig_thres
address:: 0x150
block offset:: 0x150
access mode:: rw
Channel 4 trigger threshold configuration register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| hyst[15:8]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| hyst[7:0]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| val[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| val[7:0]
|===
val:: Treated as binary two\'s complement and compared to raw ADC data.
hyst:: Configures the internal trigger threshold hysteresis.
The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
=== ch4_trig_dly
[horizontal]
HDL name:: ch4_trig_dly
address:: 0x154
block offset:: 0x154
access mode:: rw
Channel 4 trigger delay
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| ch4_trig_dly[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| ch4_trig_dly[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| ch4_trig_dly[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| ch4_trig_dly[7:0]
|===
doc/manual/fmc_adc_alt_trigin.adoc 0 → 100644
View file @ e084c507
== Memory map summary
FMC ADC alt trigger out registers
|===
|HW address | Type | Name | HDL name
|0x00
|REG
|version
|version
|0x04
|REG
|ctrl
|ctrl
|0x08
|REG
|seconds
|seconds
|0x10
|REG
|cycles
|cycles
|===
== Registers description
=== version
[horizontal]
HDL name:: version
address:: 0x0
block offset:: 0x0
access mode:: ro
Core version
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| version[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| version[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| version[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| version[7:0]
|===
=== ctrl
[horizontal]
HDL name:: ctrl
address:: 0x4
block offset:: 0x4
access mode:: rw
Control register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
| -
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
| -
| -
| -
| -
| -
| -
s| enable
|===
enable:: Enable trigger, cleared when triggered
=== seconds
[horizontal]
HDL name:: seconds
address:: 0x8
block offset:: 0x8
access mode:: rw
Time (seconds) to trigger
[cols="8*^"]
|===
| 63
| 62
| 61
| 60
| 59
| 58
| 57
| 56
8+s| seconds[63:56]
| 55
| 54
| 53
| 52
| 51
| 50
| 49
| 48
8+s| seconds[55:48]
| 47
| 46
| 45
| 44
| 43
| 42
| 41
| 40
8+s| seconds[47:40]
| 39
| 38
| 37
| 36
| 35
| 34
| 33
| 32
8+s| seconds[39:32]
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| seconds[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| seconds[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| seconds[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| seconds[7:0]
|===
=== cycles
[horizontal]
HDL name:: cycles
address:: 0x10
block offset:: 0x10
access mode:: rw
Time (cycles) to trigger
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| cycles[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| cycles[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| cycles[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| cycles[7:0]
|===
doc/manual/fmc_adc_alt_trigout.adoc 0 → 100644
View file @ e084c507
== Memory map summary
FMC ADC alt trigger out registers
|===
|HW address | Type | Name | HDL name
|0x00
|REG
|status
|status
|0x08
|REG
|ts_mask_sec
|ts_mask_sec
|0x10
|REG
|ts_cycles
|ts_cycles
|===
== Registers description
=== status
[horizontal]
HDL name:: status
address:: 0x0
block offset:: 0x0
access mode:: ro
Status register
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
| -
| -
| -
| -
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
| -
| -
| -
| -
| -
| -
| -
| -
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
| -
| -
| -
| -
| -
| -
| -
s| ts_present
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
| -
| -
| -
| -
| -
s| wr_valid
s| wr_link
s| wr_enable
|===
wr_enable:: Set when WR is enabled
wr_link:: WR link status
wr_valid:: Set when WR time is valid
ts_present:: Set when the timestamp fifo is not empty
=== ts_mask_sec
[horizontal]
HDL name:: ts_mask_sec
address:: 0x8
block offset:: 0x8
access mode:: ro
Time (seconds) of the last event
[cols="8*^"]
|===
| 63
| 62
| 61
| 60
| 59
| 58
| 57
| 56
| -
| -
| -
| -
| -
| -
| -
s| ext_mask
| 55
| 54
| 53
| 52
| 51
| 50
| 49
| 48
| -
| -
| -
| -
s| ch4_mask
s| ch3_mask
s| ch2_mask
s| ch1_mask
| 47
| 46
| 45
| 44
| 43
| 42
| 41
| 40
| -
| -
| -
| -
| -
| -
| -
| -
| 39
| 38
| 37
| 36
| 35
| 34
| 33
| 32
8+s| ts_sec[39:32]
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
8+s| ts_sec[31:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| ts_sec[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| ts_sec[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| ts_sec[7:0]
|===
ts_sec:: Seconds part of the timestamp
ch1_mask:: Set if channel 1 triggered
ch2_mask:: Set if channel 2 triggered
ch3_mask:: Set if channel 3 triggered
ch4_mask:: Set if channel 4 triggered
ext_mask:: Set if external trigger
=== ts_cycles
[horizontal]
HDL name:: ts_cycles
address:: 0x10
block offset:: 0x10
access mode:: ro
Cycles part of timestamp fifo.
[cols="8*^"]
|===
| 31
| 30
| 29
| 28
| 27
| 26
| 25
| 24
| -
| -
| -
| -
4+s| cycles[27:24]
| 23
| 22
| 21
| 20
| 19
| 18
| 17
| 16
8+s| cycles[23:16]
| 15
| 14
| 13
| 12
| 11
| 10
| 9
| 8
8+s| cycles[15:8]
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
8+s| cycles[7:0]
|===
cycles:: Cycles
general-cores @ eaacde90
Subproject commit 28cd756047ce9f85cf7c134367c7439f1189114d
Subproject commit eaacde903ef842af456c867947a0f1005f8bb4f3
hdl/rtl/Makefile 0 → 100644
View file @ e084c507
SIM =../testbench/include
DOC =../../doc/manual
SOURCES = $(wildcard *.cheby)
TARGETS = $(SOURCES:.cheby=.vhd)
all: $(TARGETS)
.PHONY: $(TARGETS)
$(TARGETS): %.vhd : %.cheby
@echo "\n\033[34m\033[1m-> Processing file $<\033[0m"
@cheby -i $< --gen-hdl=$@
@cheby -i $< --doc=md --gen-doc=$(DOC)/$(@:.vhd=.adoc)
@cheby -i $< --gen-consts=$(SIM)/$(@:.vhd=.v)
hdl/rtl/Manifest.py
View file @ e084c507
......@@ -4,7 +4,6 @@ files = [
"fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"fmc_adc_100Ms_csr_wbgen2_pkg.vhd",
"fmc_adc_alt_trigin.vhd",
"fmc_adc_alt_trigout.vhd",
"fmc_adc_eic.vhd",
......
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ e084c507
......@@ -37,7 +37,7 @@ use work.timetag_core_pkg.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.fmc_adc_100Ms_csr_wbgen2_pkg.all;
use work.fmc_adc_100ms_csr_pkg.all;
entity fmc_adc_100Ms_core is
generic (
......@@ -119,24 +119,6 @@ architecture rtl of fmc_adc_100Ms_core is
-- Components declaration
------------------------------------------------------------------------------
component fmc_adc_100Ms_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
regs_i : in t_fmc_adc_100Ms_csr_in_registers;
regs_o : out t_fmc_adc_100Ms_csr_out_registers);
end component fmc_adc_100Ms_csr;
component offset_gain_s
port (
rst_n_i : in std_logic; --! Reset (active low)
......@@ -191,9 +173,12 @@ architecture rtl of fmc_adc_100Ms_core is
attribute keep of fs_clk : signal is "TRUE";
-- SerDes
signal serdes_out_data : std_logic_vector(63 downto 0);
signal serdes_man_bitslip : std_logic;
signal serdes_synced : std_logic;
signal serdes_out_data : std_logic_vector(63 downto 0);
signal serdes_out_data_synced : std_logic_vector(63 downto 0);
signal serdes_man_bitslip : std_logic;
signal serdes_man_bitslip_sync : std_logic;
signal serdes_synced : std_logic;
signal serdes_synced_sync : std_logic;
-- Trigger
signal ext_trig_a, ext_trig : std_logic;
......@@ -208,16 +193,23 @@ architecture rtl of fmc_adc_100Ms_core is
signal int_trig : std_logic_vector(1 to 4);
signal int_trig_d : std_logic_vector(1 to 4);
signal int_trig_data : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_delay_in : t_fmc_adc_vec32_array(1 to 4);
signal int_trig_delay : t_fmc_adc_vec32_array(1 to 4);
signal int_trig_delay_cnt : t_fmc_adc_uint32_array(1 to 4);
signal int_trig_delay_bsy : std_logic_vector(1 to 4);
signal int_trig_en_in : std_logic_vector(1 to 4);
signal int_trig_pol_in : std_logic_vector(1 to 4);
signal int_trig_en : std_logic_vector(1 to 4);
signal int_trig_pol : std_logic_vector(1 to 4);
signal int_trig_thres : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_thres_hyst : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_thres_in : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_thres_hyst_in : t_fmc_adc_vec16_array(1 to 4);
signal sw_trig : std_logic;
signal sw_trig_en : std_logic;
signal sw_trig_fixed_delay : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
signal sw_trig_in : std_logic := '0';
signal sw_trig_sync_ack : std_logic := '0';
signal time_trig : std_logic;
signal time_trig_en : std_logic;
signal time_trig_fixed_delay : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
......@@ -231,7 +223,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal trig_src_vector : std_logic_vector(7 downto 0);
-- Under-sampling
signal undersample_factor : std_logic_vector(31 downto 0);
signal undersample_factor : std_logic_vector(31 downto 0) := (others => '0');
signal undersample_cnt : unsigned(31 downto 0);
signal undersample_en : std_logic;
......@@ -247,18 +239,21 @@ architecture rtl of fmc_adc_100Ms_core is
-- Gain/offset calibration and saturation value
signal gain_calibr : std_logic_vector(63 downto 0);
signal offset_calibr : std_logic_vector(63 downto 0);
signal gain_calibr_in : std_logic_vector(63 downto 0);
signal offset_calibr_in : std_logic_vector(63 downto 0);
signal data_calibr_in : std_logic_vector(63 downto 0);
signal data_calibr_out : std_logic_vector(63 downto 0);
signal data_calibr_out_d1 : std_logic_vector(63 downto 0);
signal data_calibr_out_d2 : std_logic_vector(63 downto 0);
signal data_calibr_out_d3 : std_logic_vector(63 downto 0);
signal sat_val : std_logic_vector(59 downto 0);
signal sat_val_in : std_logic_vector(59 downto 0);
-- Acquisition FSM
signal acq_fsm_current_state : t_acq_fsm_state;
signal acq_fsm_state : std_logic_vector(2 downto 0);
signal fsm_cmd : std_logic_vector(1 downto 0);
signal fsm_cmd_wr : std_logic;
signal ctl_reg_wr : std_logic;
signal acq_start : std_logic;
signal acq_stop : std_logic;
signal acq_trig : std_logic;
......@@ -335,8 +330,8 @@ architecture rtl of fmc_adc_100Ms_core is
signal wb_ddr_stall_t : std_logic;
-- IO from CSR registers
signal csr_regin : t_fmc_adc_100Ms_csr_in_registers;
signal csr_regout : t_fmc_adc_100Ms_csr_out_registers;
signal csr_regin : t_fmc_adc_100ms_csr_master_in;
signal csr_regout : t_fmc_adc_100ms_csr_master_out;
-- LEDs
signal trig_led : std_logic;
......@@ -358,7 +353,7 @@ begin
generic map (
g_master_use_struct => TRUE,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_master_granularity => BYTE,
g_slave_use_struct => TRUE,
g_slave_mode => g_WB_CSR_MODE,
g_slave_granularity => g_WB_CSR_GRANULARITY)
......@@ -414,9 +409,10 @@ begin
cmp_fs_freq : gc_frequency_meter
generic map(
g_with_internal_timebase => TRUE,
g_clk_sys_freq => 125000000,
g_counter_bits => 32
g_WITH_INTERNAL_TIMEBASE => TRUE,
g_CLK_SYS_FREQ => 125000000,
g_SYNC_OUT => TRUE,
g_COUNTER_BITS => 32
)
port map(
clk_sys_i => sys_clk_i,
......@@ -427,15 +423,11 @@ begin
freq_valid_o => fs_freq_valid
);
p_fs_freq : process (fs_clk)
p_fs_freq : process (sys_clk_i)
begin
if rising_edge(fs_clk) then
if fs_rst_n = '0' then
fs_freq <= (others => '0');
else
if fs_freq_valid = '1' then
fs_freq <= fs_freq_t;
end if;
if rising_edge(sys_clk_i) then
if fs_freq_valid = '1' then
fs_freq <= fs_freq_t;
end if;
end if;
end process p_fs_freq;
......@@ -443,6 +435,12 @@ begin
------------------------------------------------------------------------------
-- ADC SerDes
------------------------------------------------------------------------------
cmp_man_bitslip_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => serdes_man_bitslip,
synced_o => serdes_man_bitslip_sync);
cmp_adc_serdes : entity work.ltc2174_2l16b_receiver
generic map (
......@@ -457,119 +455,277 @@ begin
adc_outb_p_i => adc_outb_p_i,
adc_outb_n_i => adc_outb_n_i,
serdes_arst_i => serdes_arst,
serdes_bslip_i => serdes_man_bitslip,
serdes_bslip_i => serdes_man_bitslip_sync,
serdes_synced_o => serdes_synced,
adc_data_o => serdes_out_data,
adc_clk_o => fs_clk);
cmp_serdes_synced_sync : gc_sync_ffs
port map (
clk_i => sys_clk_i,
rst_n_i => '1',
data_i => serdes_synced,
synced_o => serdes_synced_sync);
------------------------------------------------------------------------------
-- ADC core control and status registers (CSR)
------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_csr : fmc_adc_100Ms_csr
cmp_fmc_adc_100Ms_csr : entity work.fmc_adc_100Ms_csr
port map (
rst_n_i => sys_rst_n_i,
clk_sys_i => sys_clk_i,
wb_adr_i => wb_csr_in.adr(7 downto 0),
wb_dat_i => wb_csr_in.dat,
wb_dat_o => wb_csr_out.dat,
wb_cyc_i => wb_csr_in.cyc,
wb_sel_i => wb_csr_in.sel,
wb_stb_i => wb_csr_in.stb,
wb_we_i => wb_csr_in.we,
wb_ack_o => wb_csr_out.ack,
wb_stall_o => wb_csr_out.stall,
fs_clk_i => fs_clk,
regs_i => csr_regin,
regs_o => csr_regout);
-- drive unused wb outputs
wb_csr_out.err <= '0';
wb_csr_out.rty <= '0';
csr_regin.sta_fsm_i <= acq_fsm_state;
csr_regin.sta_serdes_pll_i <= '1';
csr_regin.sta_serdes_synced_i <= serdes_synced;
csr_regin.sta_acq_cfg_i <= acq_config_ok;
csr_regin.trig_stat_ext_i <= trig_storage(0);
csr_regin.trig_stat_sw_i <= trig_storage(1);
csr_regin.trig_stat_time_i <= trig_storage(4);
csr_regin.trig_stat_ch1_i <= trig_storage(8);
csr_regin.trig_stat_ch2_i <= trig_storage(9);
csr_regin.trig_stat_ch3_i <= trig_storage(10);
csr_regin.trig_stat_ch4_i <= trig_storage(11);
csr_regin.shots_cnt_val_i <= remaining_shots;
csr_regin.trig_pos_i <= trig_addr;
csr_regin.fs_freq_i <= fs_freq;
csr_regin.samples_cnt_i <= std_logic_vector(samples_cnt);
csr_regin.ch1_sta_val_i <= serdes_out_data(15 downto 0);
csr_regin.ch2_sta_val_i <= serdes_out_data(31 downto 16);
csr_regin.ch3_sta_val_i <= serdes_out_data(47 downto 32);
csr_regin.ch4_sta_val_i <= serdes_out_data(63 downto 48);
csr_regin.multi_depth_i <= c_MULTISHOT_SAMPLE_DEPTH;
fsm_cmd <= csr_regout.ctl_fsm_cmd_o;
fsm_cmd_wr <= csr_regout.ctl_fsm_cmd_wr_o;
serdes_man_bitslip <= csr_regout.ctl_man_bitslip_o;
test_data_en <= csr_regout.ctl_test_data_en_o;
trig_led_man <= csr_regout.ctl_trig_led_o;
acq_led_man <= csr_regout.ctl_acq_led_o;
trig_storage_clear <= csr_regout.ctl_clear_trig_stat_o;
ext_trig_delay <= csr_regout.ext_trig_dly_o;
ext_trig_en <= csr_regout.trig_en_ext_o;
ext_trig_pol <= csr_regout.trig_pol_ext_o;
int_trig_delay(1) <= csr_regout.ch1_trig_dly_o;
int_trig_delay(2) <= csr_regout.ch2_trig_dly_o;
int_trig_delay(3) <= csr_regout.ch3_trig_dly_o;
int_trig_delay(4) <= csr_regout.ch4_trig_dly_o;
int_trig_en(1) <= csr_regout.trig_en_ch1_o;
int_trig_en(2) <= csr_regout.trig_en_ch2_o;
int_trig_en(3) <= csr_regout.trig_en_ch3_o;
int_trig_en(4) <= csr_regout.trig_en_ch4_o;
int_trig_pol(1) <= csr_regout.trig_pol_ch1_o;
int_trig_pol(2) <= csr_regout.trig_pol_ch2_o;
int_trig_pol(3) <= csr_regout.trig_pol_ch3_o;
int_trig_pol(4) <= csr_regout.trig_pol_ch4_o;
int_trig_thres(1) <= csr_regout.ch1_trig_thres_val_o;
int_trig_thres(2) <= csr_regout.ch2_trig_thres_val_o;
int_trig_thres(3) <= csr_regout.ch3_trig_thres_val_o;
int_trig_thres(4) <= csr_regout.ch4_trig_thres_val_o;
int_trig_thres_hyst(1) <= csr_regout.ch1_trig_thres_hyst_o;
int_trig_thres_hyst(2) <= csr_regout.ch2_trig_thres_hyst_o;
int_trig_thres_hyst(3) <= csr_regout.ch3_trig_thres_hyst_o;
int_trig_thres_hyst(4) <= csr_regout.ch4_trig_thres_hyst_o;
sw_trig <= csr_regout.sw_trig_wr_o;
sw_trig_en <= csr_regout.trig_en_sw_o;
time_trig_en <= csr_regout.trig_en_time_o;
alt_time_trig_en <= csr_regout.trig_en_alt_time_o;
shots_value <= csr_regout.shots_nb_o;
undersample_factor <= csr_regout.sr_undersample_o;
pre_trig_value <= csr_regout.pre_samples_o;
post_trig_value <= csr_regout.post_samples_o;
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
wb_i => wb_csr_in,
wb_o => wb_csr_out,
fmc_adc_100Ms_csr_i => csr_regin,
fmc_adc_100Ms_csr_o => csr_regout);
csr_regin.sta_fsm <= acq_fsm_state;
csr_regin.sta_serdes_pll <= '1';
csr_regin.sta_serdes_synced <= serdes_synced_sync;
csr_regin.sta_acq_cfg <= acq_config_ok;
csr_regin.trig_stat_ext <= trig_storage(0);
csr_regin.trig_stat_sw <= trig_storage(1);
csr_regin.trig_stat_time <= trig_storage(4);
csr_regin.trig_stat_ch1 <= trig_storage(8);
csr_regin.trig_stat_ch2 <= trig_storage(9);
csr_regin.trig_stat_ch3 <= trig_storage(10);
csr_regin.trig_stat_ch4 <= trig_storage(11);
csr_regin.shots_remain <= remaining_shots;
csr_regin.trig_pos <= trig_addr;
csr_regin.fs_freq <= fs_freq;
csr_regin.samples_cnt <= std_logic_vector(samples_cnt);
csr_regin.ch1_sta_val <= serdes_out_data_synced(15 downto 0);
csr_regin.ch2_sta_val <= serdes_out_data_synced(31 downto 16);
csr_regin.ch3_sta_val <= serdes_out_data_synced(47 downto 32);
csr_regin.ch4_sta_val <= serdes_out_data_synced(63 downto 48);
csr_regin.multi_depth <= c_MULTISHOT_SAMPLE_DEPTH;
ctl_reg_wr <= csr_regout.ctl_wr;
fsm_cmd <= csr_regout.ctl_fsm_cmd;
serdes_man_bitslip <= csr_regout.ctl_man_bitslip and ctl_reg_wr;
test_data_en <= csr_regout.ctl_test_data_en;
trig_led_man <= csr_regout.ctl_trig_led;
acq_led_man <= csr_regout.ctl_acq_led;
trig_storage_clear <= csr_regout.ctl_clear_trig_stat and ctl_reg_wr;
int_trig_delay_in(1) <= csr_regout.ch1_trig_dly;
int_trig_delay_in(2) <= csr_regout.ch2_trig_dly;
int_trig_delay_in(3) <= csr_regout.ch3_trig_dly;
int_trig_delay_in(4) <= csr_regout.ch4_trig_dly;
int_trig_en_in(1) <= csr_regout.trig_en_ch1;
int_trig_en_in(2) <= csr_regout.trig_en_ch2;
int_trig_en_in(3) <= csr_regout.trig_en_ch3;
int_trig_en_in(4) <= csr_regout.trig_en_ch4;
int_trig_pol_in(1) <= csr_regout.trig_pol_ch1;
int_trig_pol_in(2) <= csr_regout.trig_pol_ch2;
int_trig_pol_in(3) <= csr_regout.trig_pol_ch3;
int_trig_pol_in(4) <= csr_regout.trig_pol_ch4;
int_trig_thres_in(1) <= csr_regout.ch1_trig_thres_val;
int_trig_thres_in(2) <= csr_regout.ch1_trig_thres_val;
int_trig_thres_in(3) <= csr_regout.ch1_trig_thres_val;
int_trig_thres_in(4) <= csr_regout.ch1_trig_thres_val;
int_trig_thres_hyst_in(1) <= csr_regout.ch1_trig_thres_hyst;
int_trig_thres_hyst_in(2) <= csr_regout.ch1_trig_thres_hyst;
int_trig_thres_hyst_in(3) <= csr_regout.ch1_trig_thres_hyst;
int_trig_thres_hyst_in(4) <= csr_regout.ch1_trig_thres_hyst;
shots_value <= csr_regout.shots_nbr;
pre_trig_value <= csr_regout.pre_samples;
post_trig_value <= csr_regout.post_samples;
gain_calibr_in <= csr_regout.ch4_calib_gain & csr_regout.ch3_calib_gain &
csr_regout.ch2_calib_gain & csr_regout.ch1_calib_gain;
offset_calibr_in <= csr_regout.ch4_calib_offset & csr_regout.ch3_calib_offset &
csr_regout.ch2_calib_offset & csr_regout.ch1_calib_offset;
sat_val_in <= csr_regout.ch4_sat_val & csr_regout.ch3_sat_val &
csr_regout.ch2_sat_val & csr_regout.ch1_sat_val;
-- NOTE: trigger forwards are read from CSR in the b_trigout block later
gain_calibr <= csr_regout.ch4_gain_val_o & csr_regout.ch3_gain_val_o &
csr_regout.ch2_gain_val_o & csr_regout.ch1_gain_val_o;
offset_calibr <= csr_regout.ch4_offset_val_o & csr_regout.ch3_offset_val_o &
csr_regout.ch2_offset_val_o & csr_regout.ch1_offset_val_o;
sat_val <= csr_regout.ch4_sat_val_o & csr_regout.ch3_sat_val_o &
csr_regout.ch2_sat_val_o & csr_regout.ch1_sat_val_o;
-- Delays for user-controlled GPIO outputs to help with timing
p_delay_gpio_ssr : process (sys_clk_i) is
begin
if rising_edge(sys_clk_i) then
gpio_si570_oe_o <= csr_regout.ctl_fmc_clk_oe_o;
gpio_dac_clr_n_o <= csr_regout.ctl_offset_dac_clr_n_o;
gpio_ssr_ch1_o <= csr_regout.ch1_ctl_ssr_o;
gpio_ssr_ch2_o <= csr_regout.ch2_ctl_ssr_o;
gpio_ssr_ch3_o <= csr_regout.ch3_ctl_ssr_o;
gpio_ssr_ch4_o <= csr_regout.ch4_ctl_ssr_o;
gpio_si570_oe_o <= csr_regout.ctl_fmc_clk_oe;
gpio_dac_clr_n_o <= csr_regout.ctl_offset_dac_clr_n;
gpio_ssr_ch1_o <= csr_regout.ch1_ctl_ssr;
gpio_ssr_ch2_o <= csr_regout.ch2_ctl_ssr;
gpio_ssr_ch3_o <= csr_regout.ch3_ctl_ssr;
gpio_ssr_ch4_o <= csr_regout.ch4_ctl_ssr;
end if;
end process p_delay_gpio_ssr;
cmp_ext_trig_en_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => csr_regout.trig_en_ext,
synced_o => ext_trig_en);
cmp_ext_trig_pol_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => csr_regout.trig_pol_ext,
synced_o => ext_trig_pol);
cmp_sw_trig_en_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => csr_regout.trig_en_sw,
synced_o => sw_trig_en);
cmp_time_trig_en_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => csr_regout.trig_en_time,
synced_o => time_trig_en);
cmp_alt_time_trig_en_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => csr_regout.trig_en_alt_time,
synced_o => alt_time_trig_en);
cmp_undersample_sync : gc_sync_word_wr
generic map (
g_AUTO_WR => TRUE,
g_WIDTH => 32)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => csr_regout.undersample,
data_o => undersample_factor);
cmp_ch_sta_sync : gc_sync_word_wr
generic map (
g_AUTO_WR => TRUE,
g_WIDTH => 64)
port map (
clk_in_i => fs_clk,
rst_in_n_i => '1',
clk_out_i => sys_clk_i,
rst_out_n_i => '1',
data_i => serdes_out_data,
data_o => serdes_out_data_synced);
cmp_ext_trig_delay_sync : gc_sync_word_wr
generic map (
g_AUTO_WR => TRUE,
g_WIDTH => 32)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => csr_regout.ext_trig_dly,
data_o => ext_trig_delay);
gen_ch_reg_sync : for I in 1 to 4 generate
cmp_int_trig_en_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => int_trig_en_in(I),
synced_o => int_trig_en(I));
cmp_int_trig_pol_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => int_trig_pol_in(I),
synced_o => int_trig_pol(I));
cmp_ch_trig_thres_sync : gc_sync_word_wr
generic map (
g_AUTO_WR => TRUE,
g_WIDTH => 32)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i(15 downto 0) => int_trig_thres_in(I),
data_i(31 downto 16) => int_trig_thres_hyst_in(I),
data_o(15 downto 0) => int_trig_thres(I),
data_o(31 downto 16) => int_trig_thres_hyst(I));
cmp_ch_sat_sync : gc_sync_word_wr
generic map (
g_AUTO_WR => TRUE,
g_WIDTH => 15)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => sat_val_in(15*I-1 downto 15*(I-1)),
data_o => sat_val(15*I-1 downto 15*(I-1)));
cmp_ch_gain_sync : gc_sync_word_wr
generic map (
g_AUTO_WR => TRUE,
g_WIDTH => 16)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => gain_calibr_in(16*I-1 downto 16*(I-1)),
data_o => gain_calibr(16*I-1 downto 16*(I-1)));
cmp_ch_offset_sync : gc_sync_word_wr
generic map (
g_AUTO_WR => TRUE,
g_WIDTH => 16)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => offset_calibr_in(16*I-1 downto 16*(I-1)),
data_o => offset_calibr(16*I-1 downto 16*(I-1)));
cmp_ch_trig_delay_sync : gc_sync_word_wr
generic map (
g_AUTO_WR => TRUE,
g_WIDTH => 32)
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
clk_out_i => fs_clk,
rst_out_n_i => '1',
data_i => int_trig_delay_in(I),
data_o => int_trig_delay(I));
end generate gen_ch_reg_sync;
cmp_sw_trig_sync : gc_pulse_synchronizer2
port map (
clk_in_i => sys_clk_i,
rst_in_n_i => '1',
clk_out_i => fs_clk,
rst_out_n_i => '1',
d_ack_p_o => sw_trig_sync_ack,
d_p_i => sw_trig_in,
q_p_o => sw_trig);
p_sw_trig_gen : process (sys_clk_i) is
begin
if rising_edge(sys_clk_i) then
if csr_regout.sw_trig_wr = '1' then
sw_trig_in <= '1';
elsif sw_trig_in = '1' and sw_trig_sync_ack = '1' then
sw_trig_in <= '0';
end if;
end if;
end process p_sw_trig_gen;
------------------------------------------------------------------------------
-- Offset and gain calibration
------------------------------------------------------------------------------
......@@ -997,8 +1153,8 @@ begin
acq_end_p_o <= acq_end and not(acq_end_d);
-- FSM commands
acq_start <= '1' when fsm_cmd_wr = '1' and fsm_cmd = "01" else '0';
acq_stop <= '1' when fsm_cmd_wr = '1' and fsm_cmd = "10" else '0';
acq_start <= '1' when ctl_reg_wr = '1' and fsm_cmd = "01" else '0';
acq_stop <= '1' when ctl_reg_wr = '1' and fsm_cmd = "10" else '0';
acq_trig <= sync_fifo_valid and sync_fifo_dout(64) and acq_in_wait_trig;
acq_end <= trig_tag_done and shots_done;
......@@ -1518,11 +1674,11 @@ begin
trigout_triggers(3) <= trig_storage(11);
trigout_triggers(4) <= trig_storage(0);
trigout_en(0) <= csr_regout.trig_en_fwd_ch1_o;
trigout_en(1) <= csr_regout.trig_en_fwd_ch2_o;
trigout_en(2) <= csr_regout.trig_en_fwd_ch3_o;
trigout_en(3) <= csr_regout.trig_en_fwd_ch4_o;
trigout_en(4) <= csr_regout.trig_en_fwd_ext_o;
trigout_en(0) <= csr_regout.trig_en_fwd_ch1;
trigout_en(1) <= csr_regout.trig_en_fwd_ch2;
trigout_en(2) <= csr_regout.trig_en_fwd_ch3;
trigout_en(3) <= csr_regout.trig_en_fwd_ch4;
trigout_en(4) <= csr_regout.trig_en_fwd_ext;
trigout_trig <= f_reduce_or (trigout_triggers and trigout_en);
......
hdl/rtl/fmc_adc_100Ms_csr.cheby 0 → 100644
View file @ e084c507
memory-map:
bus: wb-32-be
name: fmc_adc_100ms_csr
description: FMC ADC 100MS/s core registers
comment: |
Wishbone slave for FMC ADC 100MS/s core
x-hdl:
busgroup: True
iogroup: fmc_adc_100ms_csr
children:
- reg:
name: ctl
address: 0x00000000
width: 32
access: rw
description: Control register
x-hdl:
write-strobe: True
children:
- field:
name: fsm_cmd
range: 1-0
description: State machine commands (ignore on read)
comment: |
1: ACQ_START (start acquisition, only when FSM is idle)
2: ACQ_STOP (stop acquisition, anytime)
x-hdl:
type: wire
- field:
name: fmc_clk_oe
range: 2
description: FMC Si750 output enable
- field:
name: offset_dac_clr_n
range: 3
description: Offset DACs clear (active low)
- field:
name: man_bitslip
range: 4
description: Manual serdes bitslip (ignore on read)
x-hdl:
type: wire
- field:
name: test_data_en
range: 5
description: Enable test data
comment: |
Write the DDR RAM address counter value instead of ADC data to DDR.
Note that no timetags are appended at the end of test data.
- field:
name: trig_led
range: 6
description: Manual TRIG LED
comment: |
Manual control of the front panel TRIG LED
- field:
name: acq_led
range: 7
description: Manual ACQ LED
comment: |
Manual control of the front panel ACQ LED
- field:
name: clear_trig_stat
range: 8
description: Clear trigger status
comment: |
Write 1 to clear the last trigger status register. Auto-resets to zero.
x-hdl:
type: wire
- reg:
name: sta
address: 0x00000004
width: 32
access: ro
description: Status register
children:
- field:
name: fsm
range: 2-0
description: State machine status
comment: |
States:
0: illegal
1: IDLE
2: PRE_TRIG
3: WAIT_TRIG
4: POST_TRIG
5: TRIG_TAG
6: DECR_SHOT
7: illegal
- field:
name: serdes_pll
range: 3
description: SerDes PLL status
comment: |
Sampling clock recovery PLL.
0: not locked
1: locked
- field:
name: serdes_synced
range: 4
description: SerDes synchronization status
comment: |
0: bitslip in progress
1: serdes synchronized
- field:
name: acq_cfg
range: 5
description: Acquisition configuration status
comment: |
0: Unauthorised acquisition configuration (will prevent acquisition to start)
1: Valid acquisition configuration
- Shot number > 0
- Post-trigger sample > 0
- reg:
name: trig_stat
address: 0x00000008
width: 32
access: ro
description: Trigger status
comment: |
Shows the source(s) of the last received trigger.
children:
- field:
name: ext
range: 0
description: External trigger input
comment: |
0: not triggered
1: triggered
- field:
name: sw
range: 1
description: Software trigger
comment: |
0: not triggered
1: triggered
- field:
name: time
range: 4
description: Timetag trigger
comment: |
0: not triggered
1: triggered
- field:
name: ch1
range: 8
description: Channel 1 internal threshold trigger
comment: |
0: not triggered
1: triggered
- field:
name: ch2
range: 9
description: Channel 2 internal threshold trigger
comment: |
0: not triggered
1: triggered
- field:
name: ch3
range: 10
description: Channel 3 internal threshold trigger
comment: |
0: not triggered
1: triggered
- field:
name: ch4
range: 11
description: Channel 4 internal threshold trigger
comment: |
0: not triggered
1: triggered
- reg:
name: trig_en
address: 0x0000000c
width: 32
access: rw
description: Trigger enable
children:
- field:
name: ext
range: 0
description: External trigger input
comment: |
0: disable
1: enable
- field:
name: sw
range: 1
description: Software trigger
comment: |
0: disable
1: enable
- field:
name: time
range: 4
description: Timetag trigger
comment: |
0: disable
1: enable
- field:
name: alt_time
range: 5
description: Alternate timetag trigger
comment: |
0: disable
1: enable
- field:
name: ch1
range: 8
description: Channel 1 internal threshold trigger
comment: |
0: disable
1: enable
- field:
name: ch2
range: 9
description: Channel 2 internal threshold trigger
comment: |
0: disable
1: enable
- field:
name: ch3
range: 10
description: Channel 3 internal threshold trigger
comment: |
0: disable
1: enable
- field:
name: ch4
range: 11
description: Channel 4 internal threshold trigger
comment: |
0: disable
1: enable
- field:
name: fwd_ext
range: 16
description: Forward external trigger to trigger out
comment: |
0: disable
1: enable
- field:
name: fwd_ch1
range: 24
description: Forward channel 1 internal threshold trigger to trigger out
comment: |
0: disable
1: enable
- field:
name: fwd_ch2
range: 25
description: Forward channel 2 internal threshold trigger to trigger out
comment: |
0: disable
1: enable
- field:
name: fwd_ch3
range: 26
description: Forward channel 3 internal threshold trigger to trigger out
comment: |
0: disable
1: enable
- field:
name: fwd_ch4
range: 27
description: Forward channel 4 internal threshold trigger to trigger out
comment: |
0: disable
1: enable
- reg:
name: trig_pol
address: 0x00000010
width: 32
access: rw
description: Trigger polarity
children:
- field:
name: ext
range: 0
description: External trigger input
comment: |
0: positive edge/slope
1: negative edge/slope
- field:
name: ch1
range: 8
description: Channel 1 internal threshold trigger
comment: |
0: positive edge/slope
1: negative edge/slope
- field:
name: ch2
range: 9
description: Channel 2 internal threshold trigger
comment: |
0: positive edge/slope
1: negative edge/slope
- field:
name: ch3
range: 10
description: Channel 3 internal threshold trigger
comment: |
0: positive edge/slope
1: negative edge/slope
- field:
name: ch4
range: 11
description: Channel 4 internal threshold trigger
comment: |
0: positive edge/slope
1: negative edge/slope
- reg:
name: ext_trig_dly
address: 0x00000014
width: 32
access: rw
description: External trigger delay
comment: |
Delay to apply on the trigger in sampling clock period.
The default clock frequency is 100MHz (period = 10ns).
- reg:
name: sw_trig
address: 0x00000018
width: 32
access: wo
description: Software trigger
comment: |
Writing (anything) to this register generates a software trigger.
x-hdl:
type: wire
write-strobe: True
- reg:
name: shots
address: 0x0000001c
width: 32
access: rw
description: Number of shots
children:
- field:
name: nbr
range: 15-0
description: Number of shots
comment: |
Number of shots required in multi-shot mode, set to one for single-shot mode.
- field:
name: remain
range: 31-16
description: Remaining shots counter
comment: |
Counts the number of remaining shots to acquire.
x-hdl:
type: wire
- reg:
name: multi_depth
address: 0x00000020
width: 32
access: ro
description: Multi-shot sample depth register
comment: |
Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag
- reg:
name: trig_pos
address: 0x00000024
width: 32
access: ro
description: Trigger address register
comment: |
Trigger address in DDR memory.
Only used in single-shot mode.
- reg:
name: fs_freq
address: 0x00000028
width: 32
access: ro
description: Sampling clock frequency
comment: |
ADC sampling clock frequency in Hz
- reg:
name: undersample
address: 0x0000002c
width: 32
access: rw
description: Undersampling ratio
comment: |
Undersampling ratio. Takes one sample every N samples and discards the others (N = undersampling ratio)
- reg:
name: pre_samples
address: 0x00000030
width: 32
access: rw
description: Pre-trigger samples
comment: |
Number of requested pre-trigger samples (>1).
- reg:
name: post_samples
address: 0x00000034
width: 32
access: rw
description: Post-trigger samples
comment: |
Number of requested post-trigger samples (>1).
- reg:
name: samples_cnt
address: 0x00000038
width: 32
access: ro
description: Samples counter
comment: |
Counts the number of samples.
It is reset on START and then counts the number of pre-trigger + post-trigger samples
- reg:
name: ch1_ctl
address: 0x00000080
width: 32
access: rw
description: Channel 1 control register
children:
- field:
name: ssr
range: 6-0
description: Solid state relays control for channel 1
comment: |
Controls input voltage range, termination and DC offset error calibration
0x23: 100mV range
0x11: 1V range
0x45: 10V range
0x00: Open input
0x42: 100mV range calibration
0x40: 1V range calibration
0x44: 10V range calibration
Bit3 is indepandant of the others and enables the 50ohms termination.
- reg:
name: ch1_sta
address: 0x00000084
width: 32
access: ro
description: Channel 1 status register
children:
- field:
name: val
range: 15-0
description: Channel 1 current ADC value
comment: |
Current ADC raw value. The format is binary two\'s complement.
- reg:
name: ch1_calib
address: 0x00000088
width: 32
access: rw
description: Channel 1 calibration register
children:
- field:
name: gain
range: 15-0
description: Gain calibration for channel 1
comment: |
Gain applied to all data coming from the ADC.
Fixed point format:
Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
- field:
name: offset
range: 31-16
description: Offset calibration for channel 1
comment: |
Offset applied to all data coming from the ADC. The format is binary two\'s complement.
- reg:
name: ch1_sat
address: 0x0000008c
width: 32
access: rw
description: Channel 1 saturation register
children:
- field:
name: val
range: 14-0
description: Saturation value for channel 1
comment: |
Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
- reg:
name: ch1_trig_thres
address: 0x00000090
width: 32
access: rw
description: Channel 1 trigger threshold configuration register
children:
- field:
name: val
range: 15-0
description: Threshold for internal trigger
comment: |
Treated as binary two\'s complement and compared to raw ADC data.
- field:
name: hyst
range: 31-16
description: Internal trigger threshold hysteresis
comment: |
Configures the internal trigger threshold hysteresis.
The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
- reg:
name: ch1_trig_dly
address: 0x00000094
width: 32
access: rw
description: Channel 1 trigger delay
comment: |
Delay to apply on the trigger in sampling clock period.
The default clock frequency is 100MHz (period = 10ns).
- reg:
name: ch2_ctl
address: 0x000000c0
width: 32
access: rw
description: Channel 2 control register
children:
- field:
name: ssr
range: 6-0
description: Solid state relays control for channel 2
comment: |
Controls input voltage range, termination and DC offset error calibration
0x23: 100mV range
0x11: 1V range
0x45: 10V range
0x00: Open input
0x42: 100mV range calibration
0x40: 1V range calibration
0x44: 10V range calibration
Bit3 is indepandant of the others and enables the 50ohms termination.
- reg:
name: ch2_sta
address: 0x000000c4
width: 32
access: ro
description: Channel 2 status register
children:
- field:
name: val
range: 15-0
description: Channel 2 current ACD value
comment: |
Current ADC raw value. The format is binary two\'s complement.
- reg:
name: ch2_calib
address: 0x000000c8
width: 32
access: rw
description: Channel 2 calibration register
children:
- field:
name: gain
range: 15-0
description: Gain calibration for channel 2
comment: |
Gain applied to all data coming from the ADC.
Fixed point format:
Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
- field:
name: offset
range: 31-16
description: Offset calibration for channel 2
comment: |
Offset applied to all data coming from the ADC. The format is binary two\'s complement.
- reg:
name: ch2_sat
address: 0x000000cc
width: 32
access: rw
description: Channel 2 saturation register
children:
- field:
name: val
range: 14-0
description: Saturation value for channel 2
comment: |
Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
- reg:
name: ch2_trig_thres
address: 0x000000d0
width: 32
access: rw
description: Channel 2 trigger threshold configuration register
children:
- field:
name: val
range: 15-0
description: Threshold for internal trigger
comment: |
Treated as binary two\'s complement and compared to raw ADC data.
- field:
name: hyst
range: 31-16
description: Internal trigger threshold hysteresis
comment: |
Configures the internal trigger threshold hysteresis.
The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
- reg:
name: ch2_trig_dly
address: 0x000000d4
width: 32
access: rw
description: Channel 2 trigger delay
comment: |
Delay to apply on the trigger in sampling clock period.
The default clock frequency is 100MHz (period = 10ns).
- reg:
name: ch3_ctl
address: 0x00000100
width: 32
access: rw
description: Channel 3 control register
children:
- field:
name: ssr
range: 6-0
description: Solid state relays control for channel 3
comment: |
Controls input voltage range, termination and DC offset error calibration
0x23: 100mV range
0x11: 1V range
0x45: 10V range
0x00: Open input
0x42: 100mV range calibration
0x40: 1V range calibration
0x44: 10V range calibration
Bit3 is indepandant of the others and enables the 50ohms termination.
- reg:
name: ch3_sta
address: 0x00000104
width: 32
access: ro
description: Channel 3 status register
children:
- field:
name: val
range: 15-0
description: Channel 3 current ADC value
comment: |
Current ADC raw value. The format is binary two\'s complement.
- reg:
name: ch3_calib
address: 0x00000108
width: 32
access: rw
description: Channel 3 calibration register
children:
- field:
name: gain
range: 15-0
description: Gain calibration for channel 3
comment: |
Gain applied to all data coming from the ADC.
Fixed point format:
Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
- field:
name: offset
range: 31-16
description: Offset calibration for channel 3
comment: |
Offset applied to all data coming from the ADC. The format is binary two\'s complement.
- reg:
name: ch3_sat
address: 0x0000010c
width: 32
access: rw
description: Channel 3 saturation register
children:
- field:
name: val
range: 14-0
description: Saturation value for channel 3
comment: |
Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
- reg:
name: ch3_trig_thres
address: 0x00000110
width: 32
access: rw
description: Channel 3 trigger threshold configuration register
children:
- field:
name: val
range: 15-0
description: Threshold for internal trigger
comment: |
Treated as binary two\'s complement and compared to raw ADC data.
- field:
name: hyst
range: 31-16
description: Internal trigger threshold hysteresis
comment: |
Configures the internal trigger threshold hysteresis.
The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
- reg:
name: ch3_trig_dly
address: 0x00000114
width: 32
access: rw
description: Channel 3 trigger delay
comment: |
Delay to apply on the trigger in sampling clock period.
The default clock frequency is 100MHz (period = 10ns).
- reg:
name: ch4_ctl
address: 0x00000140
width: 32
access: rw
description: Channel 4 control register
children:
- field:
name: ssr
range: 6-0
description: Solid state relays control for channel 4
comment: |
Controls input voltage range, termination and DC offset error calibration
0x23: 100mV range
0x11: 1V range
0x45: 10V range
0x00: Open input
0x42: 100mV range calibration
0x40: 1V range calibration
0x44: 10V range calibration
Bit3 is indepandant of the others and enables the 50ohms termination.
- reg:
name: ch4_sta
address: 0x00000144
width: 32
access: ro
description: Channel 4 status register
children:
- field:
name: val
range: 15-0
description: Channel 4 current ADC value
comment: |
Current ADC raw value. The format is binary two\'s complement.
- reg:
name: ch4_calib
address: 0x00000148
width: 32
access: rw
description: Channel 4 gain calibration register
children:
- field:
name: gain
range: 15-0
description: Gain calibration for channel 4
comment: |
Gain applied to all data coming from the ADC.
Fixed point format:
Bit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)
- field:
name: offset
range: 31-16
description: Offset calibration for channel 4
comment: |
Offset applied to all data coming from the ADC. The format is binary two\'s complement.
- reg:
name: ch4_sat
address: 0x0000014c
width: 32
access: rw
description: Channel 4 saturation register
children:
- field:
name: val
range: 14-0
description: Saturation value for channel 4
comment: |
Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.
- reg:
name: ch4_trig_thres
address: 0x00000150
width: 32
access: rw
description: Channel 4 trigger threshold configuration register
children:
- field:
name: val
range: 15-0
description: Threshold for internal trigger
comment: |
Treated as binary two\'s complement and compared to raw ADC data.
- field:
name: hyst
range: 31-16
description: Internal trigger threshold hysteresis
comment: |
Configures the internal trigger threshold hysteresis.
The value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.
- reg:
name: ch4_trig_dly
address: 0x00000154
width: 32
access: rw
description: Channel 4 trigger delay
comment: |
Delay to apply on the trigger in sampling clock period.
The default clock frequency is 100MHz (period = 10ns).
hdl/rtl/fmc_adc_100Ms_csr.vhd
View file @ e084c507
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd deleted 100644 → 0
View file @ 9685afca
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC ADC 100MS/s core registers
---------------------------------------------------------------------------------------
-- File : ../fmc_adc_100Ms_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Thu Mar 21 13:57:25 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package fmc_adc_100ms_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_fmc_adc_100ms_csr_in_registers is record
sta_fsm_i : std_logic_vector(2 downto 0);
sta_serdes_pll_i : std_logic;
sta_serdes_synced_i : std_logic;
sta_acq_cfg_i : std_logic;
trig_stat_ext_i : std_logic;
trig_stat_sw_i : std_logic;
trig_stat_time_i : std_logic;
trig_stat_ch1_i : std_logic;
trig_stat_ch2_i : std_logic;
trig_stat_ch3_i : std_logic;
trig_stat_ch4_i : std_logic;
multi_depth_i : std_logic_vector(31 downto 0);
shots_cnt_val_i : std_logic_vector(15 downto 0);
trig_pos_i : std_logic_vector(31 downto 0);
fs_freq_i : std_logic_vector(31 downto 0);
samples_cnt_i : std_logic_vector(31 downto 0);
ch1_sta_val_i : std_logic_vector(15 downto 0);
ch2_sta_val_i : std_logic_vector(15 downto 0);
ch3_sta_val_i : std_logic_vector(15 downto 0);
ch4_sta_val_i : std_logic_vector(15 downto 0);
end record;
constant c_fmc_adc_100ms_csr_in_registers_init_value: t_fmc_adc_100ms_csr_in_registers := (
sta_fsm_i => (others => '0'),
sta_serdes_pll_i => '0',
sta_serdes_synced_i => '0',
sta_acq_cfg_i => '0',
trig_stat_ext_i => '0',
trig_stat_sw_i => '0',
trig_stat_time_i => '0',
trig_stat_ch1_i => '0',
trig_stat_ch2_i => '0',
trig_stat_ch3_i => '0',
trig_stat_ch4_i => '0',
multi_depth_i => (others => '0'),
shots_cnt_val_i => (others => '0'),
trig_pos_i => (others => '0'),
fs_freq_i => (others => '0'),
samples_cnt_i => (others => '0'),
ch1_sta_val_i => (others => '0'),
ch2_sta_val_i => (others => '0'),
ch3_sta_val_i => (others => '0'),
ch4_sta_val_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_fmc_adc_100ms_csr_out_registers is record
ctl_fsm_cmd_o : std_logic_vector(1 downto 0);
ctl_fsm_cmd_wr_o : std_logic;
ctl_fmc_clk_oe_o : std_logic;
ctl_offset_dac_clr_n_o : std_logic;
ctl_man_bitslip_o : std_logic;
ctl_test_data_en_o : std_logic;
ctl_trig_led_o : std_logic;
ctl_acq_led_o : std_logic;
ctl_clear_trig_stat_o : std_logic;
trig_en_ext_o : std_logic;
trig_en_sw_o : std_logic;
trig_en_time_o : std_logic;
trig_en_alt_time_o : std_logic;
trig_en_ch1_o : std_logic;
trig_en_ch2_o : std_logic;
trig_en_ch3_o : std_logic;
trig_en_ch4_o : std_logic;
trig_en_fwd_ext_o : std_logic;
trig_en_fwd_ch1_o : std_logic;
trig_en_fwd_ch2_o : std_logic;
trig_en_fwd_ch3_o : std_logic;
trig_en_fwd_ch4_o : std_logic;
trig_pol_ext_o : std_logic;
trig_pol_ch1_o : std_logic;
trig_pol_ch2_o : std_logic;
trig_pol_ch3_o : std_logic;
trig_pol_ch4_o : std_logic;
ext_trig_dly_o : std_logic_vector(31 downto 0);
sw_trig_o : std_logic_vector(31 downto 0);
sw_trig_wr_o : std_logic;
shots_nb_o : std_logic_vector(15 downto 0);
sr_undersample_o : std_logic_vector(31 downto 0);
pre_samples_o : std_logic_vector(31 downto 0);
post_samples_o : std_logic_vector(31 downto 0);
ch1_ctl_ssr_o : std_logic_vector(6 downto 0);
ch1_gain_val_o : std_logic_vector(15 downto 0);
ch1_offset_val_o : std_logic_vector(15 downto 0);
ch1_sat_val_o : std_logic_vector(14 downto 0);
ch1_trig_thres_val_o : std_logic_vector(15 downto 0);
ch1_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch1_trig_dly_o : std_logic_vector(31 downto 0);
ch2_ctl_ssr_o : std_logic_vector(6 downto 0);
ch2_gain_val_o : std_logic_vector(15 downto 0);
ch2_offset_val_o : std_logic_vector(15 downto 0);
ch2_sat_val_o : std_logic_vector(14 downto 0);
ch2_trig_thres_val_o : std_logic_vector(15 downto 0);
ch2_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch2_trig_dly_o : std_logic_vector(31 downto 0);
ch3_ctl_ssr_o : std_logic_vector(6 downto 0);
ch3_gain_val_o : std_logic_vector(15 downto 0);
ch3_offset_val_o : std_logic_vector(15 downto 0);
ch3_sat_val_o : std_logic_vector(14 downto 0);
ch3_trig_thres_val_o : std_logic_vector(15 downto 0);
ch3_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch3_trig_dly_o : std_logic_vector(31 downto 0);
ch4_ctl_ssr_o : std_logic_vector(6 downto 0);
ch4_gain_val_o : std_logic_vector(15 downto 0);
ch4_offset_val_o : std_logic_vector(15 downto 0);
ch4_sat_val_o : std_logic_vector(14 downto 0);
ch4_trig_thres_val_o : std_logic_vector(15 downto 0);
ch4_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch4_trig_dly_o : std_logic_vector(31 downto 0);
end record;
constant c_fmc_adc_100ms_csr_out_registers_init_value: t_fmc_adc_100ms_csr_out_registers := (
ctl_fsm_cmd_o => (others => '0'),
ctl_fsm_cmd_wr_o => '0',
ctl_fmc_clk_oe_o => '0',
ctl_offset_dac_clr_n_o => '0',
ctl_man_bitslip_o => '0',
ctl_test_data_en_o => '0',
ctl_trig_led_o => '0',
ctl_acq_led_o => '0',
ctl_clear_trig_stat_o => '0',
trig_en_ext_o => '0',
trig_en_sw_o => '0',
trig_en_time_o => '0',
trig_en_alt_time_o => '0',
trig_en_ch1_o => '0',
trig_en_ch2_o => '0',
trig_en_ch3_o => '0',
trig_en_ch4_o => '0',
trig_en_fwd_ext_o => '0',
trig_en_fwd_ch1_o => '0',
trig_en_fwd_ch2_o => '0',
trig_en_fwd_ch3_o => '0',
trig_en_fwd_ch4_o => '0',
trig_pol_ext_o => '0',
trig_pol_ch1_o => '0',
trig_pol_ch2_o => '0',
trig_pol_ch3_o => '0',
trig_pol_ch4_o => '0',
ext_trig_dly_o => (others => '0'),
sw_trig_o => (others => '0'),
sw_trig_wr_o => '0',
shots_nb_o => (others => '0'),
sr_undersample_o => (others => '0'),
pre_samples_o => (others => '0'),
post_samples_o => (others => '0'),
ch1_ctl_ssr_o => (others => '0'),
ch1_gain_val_o => (others => '0'),
ch1_offset_val_o => (others => '0'),
ch1_sat_val_o => (others => '0'),
ch1_trig_thres_val_o => (others => '0'),
ch1_trig_thres_hyst_o => (others => '0'),
ch1_trig_dly_o => (others => '0'),
ch2_ctl_ssr_o => (others => '0'),
ch2_gain_val_o => (others => '0'),
ch2_offset_val_o => (others => '0'),
ch2_sat_val_o => (others => '0'),
ch2_trig_thres_val_o => (others => '0'),
ch2_trig_thres_hyst_o => (others => '0'),
ch2_trig_dly_o => (others => '0'),
ch3_ctl_ssr_o => (others => '0'),
ch3_gain_val_o => (others => '0'),
ch3_offset_val_o => (others => '0'),
ch3_sat_val_o => (others => '0'),
ch3_trig_thres_val_o => (others => '0'),
ch3_trig_thres_hyst_o => (others => '0'),
ch3_trig_dly_o => (others => '0'),
ch4_ctl_ssr_o => (others => '0'),
ch4_gain_val_o => (others => '0'),
ch4_offset_val_o => (others => '0'),
ch4_sat_val_o => (others => '0'),
ch4_trig_thres_val_o => (others => '0'),
ch4_trig_thres_hyst_o => (others => '0'),
ch4_trig_dly_o => (others => '0')
);
function "or" (left, right: t_fmc_adc_100ms_csr_in_registers) return t_fmc_adc_100ms_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body fmc_adc_100ms_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = '1') then
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fmc_adc_100ms_csr_in_registers) return t_fmc_adc_100ms_csr_in_registers is
variable tmp: t_fmc_adc_100ms_csr_in_registers;
begin
tmp.sta_fsm_i := f_x_to_zero(left.sta_fsm_i) or f_x_to_zero(right.sta_fsm_i);
tmp.sta_serdes_pll_i := f_x_to_zero(left.sta_serdes_pll_i) or f_x_to_zero(right.sta_serdes_pll_i);
tmp.sta_serdes_synced_i := f_x_to_zero(left.sta_serdes_synced_i) or f_x_to_zero(right.sta_serdes_synced_i);
tmp.sta_acq_cfg_i := f_x_to_zero(left.sta_acq_cfg_i) or f_x_to_zero(right.sta_acq_cfg_i);
tmp.trig_stat_ext_i := f_x_to_zero(left.trig_stat_ext_i) or f_x_to_zero(right.trig_stat_ext_i);
tmp.trig_stat_sw_i := f_x_to_zero(left.trig_stat_sw_i) or f_x_to_zero(right.trig_stat_sw_i);
tmp.trig_stat_time_i := f_x_to_zero(left.trig_stat_time_i) or f_x_to_zero(right.trig_stat_time_i);
tmp.trig_stat_ch1_i := f_x_to_zero(left.trig_stat_ch1_i) or f_x_to_zero(right.trig_stat_ch1_i);
tmp.trig_stat_ch2_i := f_x_to_zero(left.trig_stat_ch2_i) or f_x_to_zero(right.trig_stat_ch2_i);
tmp.trig_stat_ch3_i := f_x_to_zero(left.trig_stat_ch3_i) or f_x_to_zero(right.trig_stat_ch3_i);
tmp.trig_stat_ch4_i := f_x_to_zero(left.trig_stat_ch4_i) or f_x_to_zero(right.trig_stat_ch4_i);
tmp.multi_depth_i := f_x_to_zero(left.multi_depth_i) or f_x_to_zero(right.multi_depth_i);
tmp.shots_cnt_val_i := f_x_to_zero(left.shots_cnt_val_i) or f_x_to_zero(right.shots_cnt_val_i);
tmp.trig_pos_i := f_x_to_zero(left.trig_pos_i) or f_x_to_zero(right.trig_pos_i);
tmp.fs_freq_i := f_x_to_zero(left.fs_freq_i) or f_x_to_zero(right.fs_freq_i);
tmp.samples_cnt_i := f_x_to_zero(left.samples_cnt_i) or f_x_to_zero(right.samples_cnt_i);
tmp.ch1_sta_val_i := f_x_to_zero(left.ch1_sta_val_i) or f_x_to_zero(right.ch1_sta_val_i);
tmp.ch2_sta_val_i := f_x_to_zero(left.ch2_sta_val_i) or f_x_to_zero(right.ch2_sta_val_i);
tmp.ch3_sta_val_i := f_x_to_zero(left.ch3_sta_val_i) or f_x_to_zero(right.ch3_sta_val_i);
tmp.ch4_sta_val_i := f_x_to_zero(left.ch4_sta_val_i) or f_x_to_zero(right.ch4_sta_val_i);
return tmp;
end function;
end package body;
hdl/rtl/wb_gen/fmc_adc_alt_trigin.cheby → hdl/rtl/fmc_adc_alt_trigin.cheby
View file @ e084c507
memory-map:
bus: wb-32-be
name: alt_trigin
description: FMC ADC alt trigger out registers
x-hdl:
busgroup: True
children:
......
hdl/rtl/fmc_adc_alt_trigin.vhd
View file @ e084c507
-- Do not edit; this file was generated by Cheby using these options:
-- -i fmc_adc_alt_trigin.cheby --gen-hdl=fmc_adc_alt_trigin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......@@ -12,8 +15,6 @@ entity alt_trigin is
-- Enable trigger, cleared when triggered
ctrl_enable_i : in std_logic;
-- Enable trigger, cleared when triggered
ctrl_enable_o : out std_logic;
ctrl_wr_o : out std_logic;
......@@ -26,23 +27,45 @@ entity alt_trigin is
end alt_trigin;
architecture syn of alt_trigin is
signal wb_en : std_logic;
signal rd_int : std_logic;
signal wr_int : std_logic;
signal ack_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal seconds_reg : std_logic_vector(63 downto 0);
signal cycles_reg : std_logic_vector(31 downto 0);
signal wr_ack_done_int : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
rd_int <= wb_en and not wb_i.we;
wr_int <= wb_en and wb_i.we;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
......@@ -54,71 +77,72 @@ begin
cycles_o <= cycles_reg;
-- Process for write requests.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wr_ack_int <= '0';
wr_ack_done_int <= '0';
ctrl_wr_o <= '0';
seconds_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
seconds_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
cycles_reg <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
ctrl_wr_o <= '0';
if wr_int = '1' then
-- Write in progress
wr_ack_done_int <= wr_ack_int or wr_ack_done_int;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
ctrl_wr_o <= '0';
seconds_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
cycles_reg <= "00000000000000000000000000000000";
else
wr_ack_int <= '0';
ctrl_wr_o <= '0';
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register version
wr_ack_int <= not wr_ack_done_int;
when "1" =>
-- Register ctrl
ctrl_wr_o <= '1';
ctrl_enable_o <= wb_i.dat(0);
wr_ack_int <= not wr_ack_done_int;
ctrl_wr_o <= wr_int;
if wr_int = '1' then
ctrl_enable_o <= wb_i.dat(0);
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register seconds
seconds_reg(63 downto 32) <= wb_i.dat;
wr_ack_int <= not wr_ack_done_int;
if wr_int = '1' then
seconds_reg(63 downto 32) <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when "1" =>
-- Register seconds
seconds_reg(31 downto 0) <= wb_i.dat;
wr_ack_int <= not wr_ack_done_int;
if wr_int = '1' then
seconds_reg(31 downto 0) <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
wr_ack_int <= wr_int;
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register cycles
cycles_reg <= wb_i.dat;
wr_ack_int <= not wr_ack_done_int;
if wr_int = '1' then
cycles_reg <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
wr_ack_int <= wr_int;
end case;
when others =>
wr_ack_int <= wr_int;
end case;
else
wr_ack_int <= '0';
wr_ack_done_int <= '0';
end if;
end if;
end process;
-- Process for registers read.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
rd_ack1_int <= '0';
reg_rdat_int <= (others => 'X');
elsif rising_edge(clk_i) then
if rd_int = '1' and rd_ack1_int = '0' then
rd_ack1_int <= '1';
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(4 downto 3) is
when "00" =>
......@@ -126,32 +150,43 @@ begin
when "0" =>
-- version
reg_rdat_int <= "10101101110000010000000000000001";
rd_ack1_int <= rd_int;
when "1" =>
-- ctrl
reg_rdat_int(0) <= ctrl_enable_i;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- seconds
reg_rdat_int <= seconds_reg(63 downto 32);
rd_ack1_int <= rd_int;
when "1" =>
-- seconds
reg_rdat_int <= seconds_reg(31 downto 0);
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- cycles
reg_rdat_int <= cycles_reg;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
else
rd_ack1_int <= '0';
end if;
end if;
end process;
......@@ -160,7 +195,6 @@ begin
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
rd_ack_int <= '1';
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
......@@ -173,6 +207,7 @@ begin
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
......@@ -185,6 +220,7 @@ begin
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
......@@ -193,8 +229,10 @@ begin
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
hdl/rtl/wb_gen/fmc_adc_alt_trigout.cheby → hdl/rtl/fmc_adc_alt_trigout.cheby
View file @ e084c507
memory-map:
bus: wb-32-be
name: alt_trigout
description: FMC ADC alt trigger out registers
x-hdl:
busgroup: True
reg_prefix: False
......
hdl/rtl/fmc_adc_alt_trigout.vhd
View file @ e084c507
-- Do not edit; this file was generated by Cheby using these options:
-- -i fmc_adc_alt_trigout.cheby --gen-hdl=fmc_adc_alt_trigout.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......@@ -47,21 +50,43 @@ entity alt_trigout is
end alt_trigout;
architecture syn of alt_trigout is
signal wb_en : std_logic;
signal rd_int : std_logic;
signal wr_int : std_logic;
signal ack_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wr_ack_done_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
rd_int <= wb_en and not wb_i.we;
wr_int <= wb_en and wb_i.we;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
......@@ -71,61 +96,51 @@ begin
-- Assign outputs
-- Process for write requests.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wr_ack_int <= '0';
wr_ack_done_int <= '0';
elsif rising_edge(clk_i) then
if wr_int = '1' then
-- Write in progress
wr_ack_done_int <= wr_ack_int or wr_ack_done_int;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
else
wr_ack_int <= '0';
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register status
wr_ack_int <= not wr_ack_done_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
wr_ack_int <= wr_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register ts_mask_sec
wr_ack_int <= not wr_ack_done_int;
when "1" =>
-- Register ts_mask_sec
wr_ack_int <= not wr_ack_done_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
wr_ack_int <= wr_int;
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register ts_cycles
wr_ack_int <= not wr_ack_done_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
wr_ack_int <= wr_int;
end case;
when others =>
wr_ack_int <= wr_int;
end case;
else
wr_ack_int <= '0';
wr_ack_done_int <= '0';
end if;
end if;
end process;
-- Process for registers read.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
rd_ack1_int <= '0';
reg_rdat_int <= (others => 'X');
ts_cycles_rd_o <= '0';
elsif rising_edge(clk_i) then
ts_cycles_rd_o <= '0';
if rd_int = '1' and rd_ack1_int = '0' then
rd_ack1_int <= '1';
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
ts_cycles_rd_o <= '0';
else
ts_cycles_rd_o <= '0';
reg_rdat_int <= (others => '0');
case wb_i.adr(4 downto 3) is
when "00" =>
......@@ -136,7 +151,10 @@ begin
reg_rdat_int(1) <= wr_link_i;
reg_rdat_int(2) <= wr_valid_i;
reg_rdat_int(8) <= ts_present_i;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
......@@ -148,23 +166,30 @@ begin
reg_rdat_int(18) <= ch3_mask_i;
reg_rdat_int(19) <= ch4_mask_i;
reg_rdat_int(24) <= ext_mask_i;
rd_ack1_int <= rd_int;
when "1" =>
-- ts_mask_sec
reg_rdat_int <= ts_sec_i(31 downto 0);
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- ts_cycles
reg_rdat_int(27 downto 0) <= cycles_i;
ts_cycles_rd_o <= '1';
ts_cycles_rd_o <= rd_int;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
else
rd_ack1_int <= '0';
end if;
end if;
end process;
......@@ -173,7 +198,6 @@ begin
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
rd_ack_int <= '1';
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
......@@ -182,6 +206,7 @@ begin
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
......@@ -194,6 +219,7 @@ begin
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
......@@ -202,8 +228,10 @@ begin
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ e084c507
......@@ -163,12 +163,12 @@ architecture rtl of fmc_adc_mezzanine is
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000003FF",
addr_last => x"00000000000001FF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000608",
version => x"00000001",
date => x"20121116",
version => x"00000002",
date => x"20190730",
name => "WB-FMC-ADC-Core ")));
constant c_wb_timetag_sdb : t_sdb_device := (
......
hdl/rtl/wb_gen/Makefile
View file @ e084c507
WBGEN2=$(shell which wbgen2)
CHEBY=cheby
RTL=../
SIM=../../testbench/include/
TEX=../../../doc/manual/
all: fmc_adc_100Ms_csr fmc_adc_eic fmc_adc_alt_trigin fmc_adc_alt_trigout
fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h -K $(SIM)$@.v $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
all: fmc_adc_eic
fmc_adc_eic:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
fmc_adc_alt_trigin:
$(CHEBY) --gen-hdl=$(RTL)/$@.vhd --gen-doc=$@.html --gen-c=$@.h --gen-consts=$(SIM)/$@.v -i $@.cheby
fmc_adc_alt_trigout:
$(CHEBY) --gen-hdl=$(RTL)/$@.vhd --gen-doc=$@.html --gen-c=$@.h --gen-consts=$(SIM)/$@.v -i $@.cheby
hdl/rtl/wb_gen/fmc_adc_100Ms_csr.h deleted 100644 → 0
View file @ 9685afca
/*
Register definitions for slave core: FMC ADC 100MS/s core registers
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Thu Mar 21 13:57:25 2019
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_FMC_ADC_100MS_CSR_WB
#define __WBGEN2_REGDEFS_FMC_ADC_100MS_CSR_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control register */
/* definitions for field: State machine commands (ignore on read) in reg: Control register */
#define FMC_ADC_100MS_CSR_CTL_FSM_CMD_MASK WBGEN2_GEN_MASK(0, 2)
#define FMC_ADC_100MS_CSR_CTL_FSM_CMD_SHIFT 0
#define FMC_ADC_100MS_CSR_CTL_FSM_CMD_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define FMC_ADC_100MS_CSR_CTL_FSM_CMD_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: FMC Si750 output enable in reg: Control register */
#define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Offset DACs clear (active low) in reg: Control register */
#define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Manual serdes bitslip (ignore on read) in reg: Control register */
#define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Enable test data in reg: Control register */
#define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Manual TRIG LED in reg: Control register */
#define FMC_ADC_100MS_CSR_CTL_TRIG_LED WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Manual ACQ LED in reg: Control register */
#define FMC_ADC_100MS_CSR_CTL_ACQ_LED WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Clear trigger status in reg: Control register */
#define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT WBGEN2_GEN_MASK(8, 1)
/* definitions for register: Status register */
/* definitions for field: State machine status in reg: Status register */
#define FMC_ADC_100MS_CSR_STA_FSM_MASK WBGEN2_GEN_MASK(0, 3)
#define FMC_ADC_100MS_CSR_STA_FSM_SHIFT 0
#define FMC_ADC_100MS_CSR_STA_FSM_W(value) WBGEN2_GEN_WRITE(value, 0, 3)
#define FMC_ADC_100MS_CSR_STA_FSM_R(reg) WBGEN2_GEN_READ(reg, 0, 3)
/* definitions for field: SerDes PLL status in reg: Status register */
#define FMC_ADC_100MS_CSR_STA_SERDES_PLL WBGEN2_GEN_MASK(3, 1)
/* definitions for field: SerDes synchronization status in reg: Status register */
#define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Acquisition configuration status in reg: Status register */
#define FMC_ADC_100MS_CSR_STA_ACQ_CFG WBGEN2_GEN_MASK(5, 1)
/* definitions for register: Trigger status */
/* definitions for field: External trigger input in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_EXT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Software trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_SW WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timetag trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_TIME WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Channel 1 internal threshold trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH1 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Channel 2 internal threshold trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH2 WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Channel 3 internal threshold trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH3 WBGEN2_GEN_MASK(10, 1)
/* definitions for field: Channel 4 internal threshold trigger in reg: Trigger status */
#define FMC_ADC_100MS_CSR_TRIG_STAT_CH4 WBGEN2_GEN_MASK(11, 1)
/* definitions for register: Trigger enable */
/* definitions for field: External trigger input in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_EXT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Software trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_SW WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timetag trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_TIME WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Alternate timetag trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Channel 1 internal threshold trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_CH1 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Channel 2 internal threshold trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_CH2 WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Channel 3 internal threshold trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_CH3 WBGEN2_GEN_MASK(10, 1)
/* definitions for field: Channel 4 internal threshold trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_CH4 WBGEN2_GEN_MASK(11, 1)
/* definitions for field: Forward external trigger to trigger out in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT WBGEN2_GEN_MASK(16, 1)
/* definitions for field: Forward channel 1 internal threshold trigger to trigger out in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1 WBGEN2_GEN_MASK(24, 1)
/* definitions for field: Forward channel 2 internal threshold trigger to trigger out in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2 WBGEN2_GEN_MASK(25, 1)
/* definitions for field: Forward channel 3 internal threshold trigger to trigger out in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3 WBGEN2_GEN_MASK(26, 1)
/* definitions for field: Forward channel 4 internal threshold trigger to trigger out in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4 WBGEN2_GEN_MASK(27, 1)
/* definitions for register: Trigger polarity */
/* definitions for field: External trigger input in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_EXT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Channel 1 internal threshold trigger in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_CH1 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Channel 2 internal threshold trigger in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_CH2 WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Channel 3 internal threshold trigger in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_CH3 WBGEN2_GEN_MASK(10, 1)
/* definitions for field: Channel 4 internal threshold trigger in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_CH4 WBGEN2_GEN_MASK(11, 1)
/* definitions for register: External trigger delay */
/* definitions for register: Software trigger */
/* definitions for register: Number of shots */
/* definitions for field: Number of shots in reg: Number of shots */
#define FMC_ADC_100MS_CSR_SHOTS_NB_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_SHOTS_NB_SHIFT 0
#define FMC_ADC_100MS_CSR_SHOTS_NB_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_SHOTS_NB_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Multi-shot sample depth register */
/* definitions for register: Remaining shots counter */
/* definitions for field: Remaining shots counter in reg: Remaining shots counter */
#define FMC_ADC_100MS_CSR_SHOTS_CNT_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_SHOTS_CNT_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_SHOTS_CNT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_SHOTS_CNT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Trigger address register */
/* definitions for register: Sampling clock frequency */
/* definitions for register: Sample rate */
/* definitions for field: Undersampling ratio in reg: Sample rate */
#define FMC_ADC_100MS_CSR_SR_UNDERSAMPLE_MASK WBGEN2_GEN_MASK(0, 32)
#define FMC_ADC_100MS_CSR_SR_UNDERSAMPLE_SHIFT 0
#define FMC_ADC_100MS_CSR_SR_UNDERSAMPLE_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define FMC_ADC_100MS_CSR_SR_UNDERSAMPLE_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Pre-trigger samples */
/* definitions for register: Post-trigger samples */
/* definitions for register: Samples counter */
/* definitions for register: Channel 1 control register */
/* definitions for field: Solid state relays control for channel 1 in reg: Channel 1 control register */
#define FMC_ADC_100MS_CSR_CH1_CTL_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_100MS_CSR_CH1_CTL_SSR_SHIFT 0
#define FMC_ADC_100MS_CSR_CH1_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_100MS_CSR_CH1_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for register: Channel 1 status register */
/* definitions for field: Channel 1 current ADC value in reg: Channel 1 status register */
#define FMC_ADC_100MS_CSR_CH1_STA_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH1_STA_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH1_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH1_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 1 gain calibration register */
/* definitions for field: Gain calibration for channel 1 in reg: Channel 1 gain calibration register */
#define FMC_ADC_100MS_CSR_CH1_GAIN_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH1_GAIN_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH1_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH1_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 1 offset calibration register */
/* definitions for field: Offset calibration for channel 1 in reg: Channel 1 offset calibration register */
#define FMC_ADC_100MS_CSR_CH1_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH1_OFFSET_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH1_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH1_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 1 saturation register */
/* definitions for field: Saturation value for channel 1 in reg: Channel 1 saturation register */
#define FMC_ADC_100MS_CSR_CH1_SAT_VAL_MASK WBGEN2_GEN_MASK(0, 15)
#define FMC_ADC_100MS_CSR_CH1_SAT_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH1_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH1_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 1 trigger threshold configuration register */
/* definitions for field: Threshold for internal trigger in reg: Channel 1 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Internal trigger threshold hysteresis in reg: Channel 1 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_SHIFT 16
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 1 trigger delay */
/* definitions for register: Channel 2 control register */
/* definitions for field: Solid state relays control for channel 2 in reg: Channel 2 control register */
#define FMC_ADC_100MS_CSR_CH2_CTL_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_100MS_CSR_CH2_CTL_SSR_SHIFT 0
#define FMC_ADC_100MS_CSR_CH2_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_100MS_CSR_CH2_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for register: Channel 2 status register */
/* definitions for field: Channel 2 current ACD value in reg: Channel 2 status register */
#define FMC_ADC_100MS_CSR_CH2_STA_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH2_STA_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH2_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH2_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 2 gain calibration register */
/* definitions for field: Gain calibration for channel 2 in reg: Channel 2 gain calibration register */
#define FMC_ADC_100MS_CSR_CH2_GAIN_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH2_GAIN_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH2_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH2_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 2 offset calibration register */
/* definitions for field: Offset calibration for channel 2 in reg: Channel 2 offset calibration register */
#define FMC_ADC_100MS_CSR_CH2_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH2_OFFSET_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH2_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH2_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 2 saturation register */
/* definitions for field: Saturation value for channel 2 in reg: Channel 2 saturation register */
#define FMC_ADC_100MS_CSR_CH2_SAT_VAL_MASK WBGEN2_GEN_MASK(0, 15)
#define FMC_ADC_100MS_CSR_CH2_SAT_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH2_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH2_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 2 trigger threshold configuration register */
/* definitions for field: Threshold for internal trigger in reg: Channel 2 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Internal trigger threshold hysteresis in reg: Channel 2 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_SHIFT 16
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 trigger delay */
/* definitions for register: Channel 3 control register */
/* definitions for field: Solid state relays control for channel 3 in reg: Channel 3 control register */
#define FMC_ADC_100MS_CSR_CH3_CTL_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_100MS_CSR_CH3_CTL_SSR_SHIFT 0
#define FMC_ADC_100MS_CSR_CH3_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_100MS_CSR_CH3_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for register: Channel 3 status register */
/* definitions for field: Channel 3 current ADC value in reg: Channel 3 status register */
#define FMC_ADC_100MS_CSR_CH3_STA_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH3_STA_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH3_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH3_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 3 gain calibration register */
/* definitions for field: Gain calibration for channel 3 in reg: Channel 3 gain calibration register */
#define FMC_ADC_100MS_CSR_CH3_GAIN_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH3_GAIN_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH3_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH3_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 3 offset calibration register */
/* definitions for field: Offset calibration for channel 3 in reg: Channel 3 offset calibration register */
#define FMC_ADC_100MS_CSR_CH3_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH3_OFFSET_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH3_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH3_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 3 saturation register */
/* definitions for field: Saturation value for channel 3 in reg: Channel 3 saturation register */
#define FMC_ADC_100MS_CSR_CH3_SAT_VAL_MASK WBGEN2_GEN_MASK(0, 15)
#define FMC_ADC_100MS_CSR_CH3_SAT_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH3_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH3_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 3 trigger threshold configuration register */
/* definitions for field: Threshold for internal trigger in reg: Channel 3 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Internal trigger threshold hysteresis in reg: Channel 3 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_SHIFT 16
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 trigger delay */
/* definitions for register: Channel 4 control register */
/* definitions for field: Solid state relays control for channel 4 in reg: Channel 4 control register */
#define FMC_ADC_100MS_CSR_CH4_CTL_SSR_MASK WBGEN2_GEN_MASK(0, 7)
#define FMC_ADC_100MS_CSR_CH4_CTL_SSR_SHIFT 0
#define FMC_ADC_100MS_CSR_CH4_CTL_SSR_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define FMC_ADC_100MS_CSR_CH4_CTL_SSR_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for register: Channel 4 status register */
/* definitions for field: Channel 4 current ADC value in reg: Channel 4 status register */
#define FMC_ADC_100MS_CSR_CH4_STA_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH4_STA_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH4_STA_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH4_STA_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 4 gain calibration register */
/* definitions for field: Gain calibration for channel 4 in reg: Channel 4 gain calibration register */
#define FMC_ADC_100MS_CSR_CH4_GAIN_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH4_GAIN_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH4_GAIN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH4_GAIN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 4 offset calibration register */
/* definitions for field: Offset calibration for channel 4 in reg: Channel 4 offset calibration register */
#define FMC_ADC_100MS_CSR_CH4_OFFSET_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH4_OFFSET_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH4_OFFSET_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH4_OFFSET_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Channel 4 saturation register */
/* definitions for field: Saturation value for channel 4 in reg: Channel 4 saturation register */
#define FMC_ADC_100MS_CSR_CH4_SAT_VAL_MASK WBGEN2_GEN_MASK(0, 15)
#define FMC_ADC_100MS_CSR_CH4_SAT_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH4_SAT_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 15)
#define FMC_ADC_100MS_CSR_CH4_SAT_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 15)
/* definitions for register: Channel 4 trigger threshold configuration register */
/* definitions for field: Threshold for internal trigger in reg: Channel 4 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_SHIFT 0
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Internal trigger threshold hysteresis in reg: Channel 4 trigger threshold configuration register */
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_MASK WBGEN2_GEN_MASK(16, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_SHIFT 16
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 trigger delay */
PACKED struct FMC_ADC_100MS_CSR_WB {
/* [0x0]: REG Control register */
uint32_t CTL;
/* [0x4]: REG Status register */
uint32_t STA;
/* [0x8]: REG Trigger status */
uint32_t TRIG_STAT;
/* [0xc]: REG Trigger enable */
uint32_t TRIG_EN;
/* [0x10]: REG Trigger polarity */
uint32_t TRIG_POL;
/* [0x14]: REG External trigger delay */
uint32_t EXT_TRIG_DLY;
/* [0x18]: REG Software trigger */
uint32_t SW_TRIG;
/* [0x1c]: REG Number of shots */
uint32_t SHOTS;
/* [0x20]: REG Multi-shot sample depth register */
uint32_t MULTI_DEPTH;
/* [0x24]: REG Remaining shots counter */
uint32_t SHOTS_CNT;
/* [0x28]: REG Trigger address register */
uint32_t TRIG_POS;
/* [0x2c]: REG Sampling clock frequency */
uint32_t FS_FREQ;
/* [0x30]: REG Sample rate */
uint32_t SR;
/* [0x34]: REG Pre-trigger samples */
uint32_t PRE_SAMPLES;
/* [0x38]: REG Post-trigger samples */
uint32_t POST_SAMPLES;
/* [0x3c]: REG Samples counter */
uint32_t SAMPLES_CNT;
/* padding to: 32 words */
uint32_t __padding_0[16];
/* [0x80]: REG Channel 1 control register */
uint32_t CH1_CTL;
/* [0x84]: REG Channel 1 status register */
uint32_t CH1_STA;
/* [0x88]: REG Channel 1 gain calibration register */
uint32_t CH1_GAIN;
/* [0x8c]: REG Channel 1 offset calibration register */
uint32_t CH1_OFFSET;
/* [0x90]: REG Channel 1 saturation register */
uint32_t CH1_SAT;
/* [0x94]: REG Channel 1 trigger threshold configuration register */
uint32_t CH1_TRIG_THRES;
/* [0x98]: REG Channel 1 trigger delay */
uint32_t CH1_TRIG_DLY;
/* padding to: 64 words */
uint32_t __padding_1[25];
/* [0x100]: REG Channel 2 control register */
uint32_t CH2_CTL;
/* [0x104]: REG Channel 2 status register */
uint32_t CH2_STA;
/* [0x108]: REG Channel 2 gain calibration register */
uint32_t CH2_GAIN;
/* [0x10c]: REG Channel 2 offset calibration register */
uint32_t CH2_OFFSET;
/* [0x110]: REG Channel 2 saturation register */
uint32_t CH2_SAT;
/* [0x114]: REG Channel 2 trigger threshold configuration register */
uint32_t CH2_TRIG_THRES;
/* [0x118]: REG Channel 2 trigger delay */
uint32_t CH2_TRIG_DLY;
/* padding to: 96 words */
uint32_t __padding_2[25];
/* [0x180]: REG Channel 3 control register */
uint32_t CH3_CTL;
/* [0x184]: REG Channel 3 status register */
uint32_t CH3_STA;
/* [0x188]: REG Channel 3 gain calibration register */
uint32_t CH3_GAIN;
/* [0x18c]: REG Channel 3 offset calibration register */
uint32_t CH3_OFFSET;
/* [0x190]: REG Channel 3 saturation register */
uint32_t CH3_SAT;
/* [0x194]: REG Channel 3 trigger threshold configuration register */
uint32_t CH3_TRIG_THRES;
/* [0x198]: REG Channel 3 trigger delay */
uint32_t CH3_TRIG_DLY;
/* padding to: 128 words */
uint32_t __padding_3[25];
/* [0x200]: REG Channel 4 control register */
uint32_t CH4_CTL;
/* [0x204]: REG Channel 4 status register */
uint32_t CH4_STA;
/* [0x208]: REG Channel 4 gain calibration register */
uint32_t CH4_GAIN;
/* [0x20c]: REG Channel 4 offset calibration register */
uint32_t CH4_OFFSET;
/* [0x210]: REG Channel 4 saturation register */
uint32_t CH4_SAT;
/* [0x214]: REG Channel 4 trigger threshold configuration register */
uint32_t CH4_TRIG_THRES;
/* [0x218]: REG Channel 4 trigger delay */
uint32_t CH4_TRIG_DLY;
};
#endif
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peripheral {
name = "FMC ADC 100MS/s core registers";
description = "Wishbone slave for FMC ADC 100MS/s core";
hdl_entity = "fmc_adc_100ms_csr";
prefix = "fmc_adc_100ms_csr";
reg {
name = "Control register";
prefix = "ctl";
field {
name = "State machine commands (ignore on read)";
description = "1: ACQ_START (start acquisition, only when FSM is idle)\n2: ACQ_STOP (stop acquisition, anytime)";
prefix = "fsm_cmd";
type = PASS_THROUGH;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "FMC Si750 output enable";
prefix = "fmc_clk_oe";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Offset DACs clear (active low)";
prefix = "offset_dac_clr_n";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Manual serdes bitslip (ignore on read)";
prefix = "man_bitslip";
type = MONOSTABLE;
clock = "fs_clk_i"
};
field {
name = "Enable test data";
description = "Write the DDR RAM address counter value instead of ADC data to DDR.\nNote that no timetags are appended at the end of test data.";
prefix = "test_data_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Manual TRIG LED";
description = "Manual control of the front panel TRIG LED";
prefix = "trig_led";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Manual ACQ LED";
description = "Manual control of the front panel ACQ LED";
prefix = "acq_led";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Clear trigger status";
description = "Write 1 to clear the last trigger status register. Auto-resets to zero.";
prefix = "clear_trig_stat";
type = MONOSTABLE;
};
};
reg {
name = "Status register";
prefix = "sta";
field {
name = "State machine status";
description = "States:\n0: illegal\n1: IDLE\n2: PRE_TRIG\n3: WAIT_TRIG\n4: POST_TRIG\n5: TRIG_TAG\n6: DECR_SHOT\n7: illegal";
prefix = "fsm";
type = SLV;
size = 3;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SerDes PLL status";
description = "Sampling clock recovery PLL.\n0: not locked\n1: locked";
prefix = "serdes_pll";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SerDes synchronization status";
description = "0: bitslip in progress\n1: serdes synchronized";
prefix = "serdes_synced";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Acquisition configuration status";
description = "0: Unauthorised acquisition configuration (will prevent acquisition to start)\n1: Valid acquisition configuration\n- Shot number > 0\n- Post-trigger sample > 0";
prefix = "acq_cfg";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger status";
prefix = "trig_stat";
description = "Shows the source(s) of the last received trigger.";
field {
name = "External trigger input";
description = "0: not triggered\n1: triggered";
prefix = "ext";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Software trigger";
description = "0: not triggered\n1: triggered";
prefix = "sw";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
align = 4;
name = "Timetag trigger";
description = "0: not triggered\n1: triggered";
prefix = "time";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
align = 8;
name = "Channel 1 internal threshold trigger";
description = "0: not triggered\n1: triggered";
prefix = "ch1";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Channel 2 internal threshold trigger";
description = "0: not triggered\n1: triggered";
prefix = "ch2";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Channel 3 internal threshold trigger";
description = "0: not triggered\n1: triggered";
prefix = "ch3";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Channel 4 internal threshold trigger";
description = "0: not triggered\n1: triggered";
prefix = "ch4";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger enable";
prefix = "trig_en";
field {
name = "External trigger input";
description = "0: disable\n1: enable";
prefix = "ext";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Software trigger";
description = "0: disable\n1: enable";
prefix = "sw";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
align = 4;
name = "Timetag trigger";
description = "0: disable\n1: enable";
prefix = "time";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Alternate timetag trigger";
description = "0: disable\n1: enable";
prefix = "alt_time";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
align = 8;
name = "Channel 1 internal threshold trigger";
description = "0: disable\n1: enable";
prefix = "ch1";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Channel 2 internal threshold trigger";
description = "0: disable\n1: enable";
prefix = "ch2";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Channel 3 internal threshold trigger";
description = "0: disable\n1: enable";
prefix = "ch3";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Channel 4 internal threshold trigger";
description = "0: disable\n1: enable";
prefix = "ch4";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
align = 16;
name = "Forward external trigger to trigger out";
description = "0: disable\n1: enable";
prefix = "fwd_ext";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
align = 8;
name = "Forward channel 1 internal threshold trigger to trigger out";
description = "0: disable\n1: enable";
prefix = "fwd_ch1";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Forward channel 2 internal threshold trigger to trigger out";
description = "0: disable\n1: enable";
prefix = "fwd_ch2";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Forward channel 3 internal threshold trigger to trigger out";
description = "0: disable\n1: enable";
prefix = "fwd_ch3";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Forward channel 4 internal threshold trigger to trigger out";
description = "0: disable\n1: enable";
prefix = "fwd_ch4";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Trigger polarity";
prefix = "trig_pol";
field {
name = "External trigger input";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ext";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
-- Note: does not make sense to have polarity on soft trigger
-- field {
-- name = "Software trigger";
-- description = "0: positive edge/slope\n1: negative edge/slope";
-- prefix = "sw";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- clock = "fs_clk_i";
-- };
-- Note: does not make sense to have polarity on time trigger
-- field {
-- align = 4;
-- name = "Timetag trigger";
-- description = "0: positive edge/slope\n1: negative edge/slope";
-- prefix = "time";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- clock = "fs_clk_i";
-- };
field {
align = 8;
name = "Channel 1 internal threshold trigger";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ch1";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Channel 2 internal threshold trigger";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ch2";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Channel 3 internal threshold trigger";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ch3";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
name = "Channel 4 internal threshold trigger";
description = "0: positive edge/slope\n1: negative edge/slope";
prefix = "ch4";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "External trigger delay";
prefix = "ext_trig_dly";
field {
name = "External trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Software trigger";
description = "Writing (anything) to this register generates a software trigger.";
prefix = "sw_trig";
field {
name = "Software trigger (ignore on read)";
type = PASS_THROUGH;
size = 32;
clock = "fs_clk_i";
};
};
reg {
name = "Number of shots";
prefix = "shots";
field {
name = "Number of shots";
description = "Number of shots required in multi-shot mode, set to one for single-shot mode.";
prefix = "nb";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Multi-shot sample depth register";
prefix = "multi_depth";
field {
name = "Multi-shot sample depth";
description = "Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Remaining shots counter";
prefix = "shots_cnt";
field {
name = "Remaining shots counter";
description = "Counts the number of remaining shots to acquire.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger address register";
prefix = "trig_pos";
field {
name = "Trigger address";
description = "Trigger address in DDR memory.\nOnly used in single-shot mode.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Sampling clock frequency";
prefix = "fs_freq";
field {
name = "Sampling clock frequency";
description = "ADC sampling clock frequency in Hz";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Sample rate";
prefix = "sr";
field {
name = "Undersampling ratio";
description = "Undersampling ratio. Takes one sample every N samples and discards the others (N = undersampling ratio).";
prefix = "undersample";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Pre-trigger samples";
prefix = "pre_samples";
field {
name = "Pre-trigger samples";
description = "Number of requested pre-trigger samples (>1).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Post-trigger samples";
prefix = "post_samples";
field {
name = "Post-trigger samples";
description = "Number of requested post-trigger samples (>1).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Samples counter";
prefix = "samples_cnt";
field {
name = "Samples counter";
description = "Counts the number of samples.\n It is reset on START and then counts the number of pre-trigger + post-trigger samples";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Channel 1 control register";
prefix = "ch1_ctl";
align = 0x20;
field {
name = "Solid state relays control for channel 1";
description = "Controls input voltage range, termination and DC offset error calibration\n0x23: 100mV range\n0x11: 1V range\n0x45: 10V range\n0x00: Open input\n0x42: 100mV range calibration\n0x40: 1V range calibration\n0x44: 10V range calibration\nBit3 is indepandant of the others and enables the 50ohms termination.";
prefix = "ssr";
type = SLV;
size = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 1 status register";
prefix = "ch1_sta";
field {
name = "Channel 1 current ADC value";
description = "Current ADC raw value. The format is binary two's complement.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 1 gain calibration register";
prefix = "ch1_gain";
field {
name = "Gain calibration for channel 1";
description = "Gain applied to all data coming from the ADC.\nFixed point format:\nBit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 1 offset calibration register";
prefix = "ch1_offset";
field {
name = "Offset calibration for channel 1";
description = "Offset applied to all data coming from the ADC. The format is binary two's complement.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 1 saturation register";
prefix = "ch1_sat";
field {
name = "Saturation value for channel 1";
description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
prefix = "val";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 1 trigger threshold configuration register";
prefix = "ch1_trig_thres";
field {
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
align = 16;
name = "Internal trigger threshold hysteresis";
description = "Configures the internal trigger threshold hysteresis.\nThe value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.";
prefix = "hyst";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 1 trigger delay";
prefix = "ch1_trig_dly";
field {
name = "Channel 1 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 control register";
prefix = "ch2_ctl";
align = 0x20;
field {
name = "Solid state relays control for channel 2";
description = "Controls input voltage range, termination and DC offset error calibration\n0x23: 100mV range\n0x11: 1V range\n0x45: 10V range\n0x00: Open input\n0x42: 100mV range calibration\n0x40: 1V range calibration\n0x44: 10V range calibration\nBit3 is indepandant of the others and enables the 50ohms termination.";
prefix = "ssr";
type = SLV;
size = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 status register";
prefix = "ch2_sta";
field {
name = "Channel 2 current ACD value";
description = "Current ADC raw value. The format is binary two's complement.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 2 gain calibration register";
prefix = "ch2_gain";
field {
name = "Gain calibration for channel 2";
description = "Gain applied to all data coming from the ADC.\nFixed point format:\nBit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 offset calibration register";
prefix = "ch2_offset";
field {
name = "Offset calibration for channel 2";
description = "Offset applied to all data coming from the ADC. The format is binary two's complement.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 saturation register";
prefix = "ch2_sat";
field {
name = "Saturation value for channel 2";
description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
prefix = "val";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 trigger threshold configuration register";
prefix = "ch2_trig_thres";
field {
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
align = 16;
name = "Internal trigger threshold hysteresis";
description = "Configures the internal trigger threshold hysteresis.\nThe value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.";
prefix = "hyst";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 2 trigger delay";
prefix = "ch2_trig_dly";
field {
name = "Channel 2 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 control register";
prefix = "ch3_ctl";
align = 0x20;
field {
name = "Solid state relays control for channel 3";
description = "Controls input voltage range, termination and DC offset error calibration\n0x23: 100mV range\n0x11: 1V range\n0x45: 10V range\n0x00: Open input\n0x42: 100mV range calibration\n0x40: 1V range calibration\n0x44: 10V range calibration\nBit3 is indepandant of the others and enables the 50ohms termination.";
prefix = "ssr";
type = SLV;
size = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 status register";
prefix = "ch3_sta";
field {
name = "Channel 3 current ADC value";
description = "Current ADC raw value. The format is binary two's complement.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 3 gain calibration register";
prefix = "ch3_gain";
field {
name = "Gain calibration for channel 3";
description = "Gain applied to all data coming from the ADC.\nFixed point format:\nBit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 offset calibration register";
prefix = "ch3_offset";
field {
name = "Offset calibration for channel 3";
description = "Offset applied to all data coming from the ADC. The format is binary two's complement.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 saturation register";
prefix = "ch3_sat";
field {
name = "Saturation value for channel 3";
description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
prefix = "val";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 trigger threshold configuration register";
prefix = "ch3_trig_thres";
field {
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
align = 16;
name = "Internal trigger threshold hysteresis";
description = "Configures the internal trigger threshold hysteresis.\nThe value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.";
prefix = "hyst";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 3 trigger delay";
prefix = "ch3_trig_dly";
field {
name = "Channel 3 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 control register";
prefix = "ch4_ctl";
align = 0x20;
field {
name = "Solid state relays control for channel 4";
description = "Controls input voltage range, termination and DC offset error calibration\n0x23: 100mV range\n0x11: 1V range\n0x45: 10V range\n0x00: Open input\n0x42: 100mV range calibration\n0x40: 1V range calibration\n0x44: 10V range calibration\nBit3 is indepandant of the others and enables the 50ohms termination.";
prefix = "ssr";
type = SLV;
size = 7;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 status register";
prefix = "ch4_sta";
field {
name = "Channel 4 current ADC value";
description = "Current ADC raw value. The format is binary two's complement.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 4 gain calibration register";
prefix = "ch4_gain";
field {
name = "Gain calibration for channel 4";
description = "Gain applied to all data coming from the ADC.\nFixed point format:\nBit 15 = 2^0, bit 14 = 2^(-1), bit 13 = 2^(-2), ... , bit 1 = 2^(-14), bit 0 = 2^(-15)";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 offset calibration register";
prefix = "ch4_offset";
field {
name = "Offset calibration for channel 4";
description = "Offset applied to all data coming from the ADC. The format is binary two's complement.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 saturation register";
prefix = "ch4_sat";
field {
name = "Saturation value for channel 4";
description = "Saturation applied to all data coming from the offset/gain correction block. The format is 15-bit unsigned.";
prefix = "val";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 trigger threshold configuration register";
prefix = "ch4_trig_thres";
field {
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data.";
prefix = "val";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
field {
align = 16;
name = "Internal trigger threshold hysteresis";
description = "Configures the internal trigger threshold hysteresis.\nThe value is always unsigned, and the gateware will subtract/add it based on the configured trigger polarity.";
prefix = "hyst";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
};
};
reg {
name = "Channel 4 trigger delay";
prefix = "ch4_trig_dly";
field {
name = "Channel 4 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
hdl/rtl/wb_gen/fmc_adc_alt_trigin.h deleted 100644 → 0
View file @ 9685afca
#ifndef __CHEBY__ALT_TRIGIN__H__
#define __CHEBY__ALT_TRIGIN__H__
/* Core version */
#define ALT_TRIGIN_VERSION 0x0UL
#define ALT_TRIGIN_VERSION_PRESET 0xadc10001UL
/* Control register */
#define ALT_TRIGIN_CTRL 0x4UL
#define ALT_TRIGIN_CTRL_ENABLE 0x1UL
/* Time (seconds) to trigger */
#define ALT_TRIGIN_SECONDS 0x8UL
/* Time (cycles) to trigger */
#define ALT_TRIGIN_CYCLES 0x10UL
struct alt_trigin {
/* [0x0]: REG (ro) Core version */
uint32_t version;
/* [0x4]: REG (rw) Control register */
uint32_t ctrl;
/* [0x8]: REG (rw) Time (seconds) to trigger */
uint64_t seconds;
/* [0x10]: REG (rw) Time (cycles) to trigger */
uint32_t cycles;
};
#endif /* __CHEBY__ALT_TRIGIN__H__ */
hdl/rtl/wb_gen/fmc_adc_alt_trigin.html deleted 100644 → 0
View file @ 9685afca
<HTML>
<HEAD>
<TITLE>alt_trigin</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
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h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22;
color:#404040; }
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background: #e0e0f0;
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font-size:10; width: 70px;
font-family:Courier New,Courier; padding: 3px;
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border: solid 1px black; }
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padding:3px; }
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-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">alt_trigin</h1>
<h3>None</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>H/W Address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#version">version</a></td>
<td class="td_code">version</td>
<td class="td_code">version</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x04</td>
<td>REG</td>
<td><A href="#ctrl">ctrl</a></td>
<td class="td_code">ctrl</td>
<td class="td_code">ctrl</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#seconds">seconds</a></td>
<td class="td_code">seconds</td>
<td class="td_code">seconds</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#cycles">cycles</a></td>
<td class="td_code">cycles</td>
<td class="td_code">cycles</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="version"></a>
<h3><a name="sect_3_1">2.1. version</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigin_version</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">version</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Core version
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">version[7:0]</td>
</tr>
</table>
<ul>
<li><b>
version
</b>[<i>ro</i>]: Core version
</ul>
<a name="ctrl"></a>
<h3><a name="sect_3_2">2.2. ctrl</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigin_ctrl</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">ctrl</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Control register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">enable</td>
</tr>
</table>
<ul>
<li><b>
enable
</b>[<i>rw</i>]: Enable trigger, cleared when triggered
</ul>
<a name="seconds"></a>
<h3><a name="sect_3_3">2.3. seconds</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigin_seconds</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">seconds</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) to trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">63</td>
<td class="td_bit" colspan="1">62</td>
<td class="td_bit" colspan="1">61</td>
<td class="td_bit" colspan="1">60</td>
<td class="td_bit" colspan="1">59</td>
<td class="td_bit" colspan="1">58</td>
<td class="td_bit" colspan="1">57</td>
<td class="td_bit" colspan="1">56</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[63:56]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">55</td>
<td class="td_bit" colspan="1">54</td>
<td class="td_bit" colspan="1">53</td>
<td class="td_bit" colspan="1">52</td>
<td class="td_bit" colspan="1">51</td>
<td class="td_bit" colspan="1">50</td>
<td class="td_bit" colspan="1">49</td>
<td class="td_bit" colspan="1">48</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[55:48]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">47</td>
<td class="td_bit" colspan="1">46</td>
<td class="td_bit" colspan="1">45</td>
<td class="td_bit" colspan="1">44</td>
<td class="td_bit" colspan="1">43</td>
<td class="td_bit" colspan="1">42</td>
<td class="td_bit" colspan="1">41</td>
<td class="td_bit" colspan="1">40</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[47:40]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">39</td>
<td class="td_bit" colspan="1">38</td>
<td class="td_bit" colspan="1">37</td>
<td class="td_bit" colspan="1">36</td>
<td class="td_bit" colspan="1">35</td>
<td class="td_bit" colspan="1">34</td>
<td class="td_bit" colspan="1">33</td>
<td class="td_bit" colspan="1">32</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[39:32]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">seconds[7:0]</td>
</tr>
</table>
<ul>
<li><b>
seconds
</b>[<i>rw</i>]: Time (seconds) to trigger
</ul>
<a name="cycles"></a>
<h3><a name="sect_3_4">2.4. cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigin_cycles</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">cycles</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Time (cycles) to trigger
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[7:0]</td>
</tr>
</table>
<ul>
<li><b>
cycles
</b>[<i>rw</i>]: Time (cycles) to trigger
</ul>
</BODY>
</HTML>
hdl/rtl/wb_gen/fmc_adc_alt_trigout.h deleted 100644 → 0
View file @ 9685afca
#ifndef __CHEBY__ALT_TRIGOUT__H__
#define __CHEBY__ALT_TRIGOUT__H__
/* Status register */
#define ALT_TRIGOUT_STATUS 0x0UL
#define ALT_TRIGOUT_WR_ENABLE 0x1UL
#define ALT_TRIGOUT_WR_LINK 0x2UL
#define ALT_TRIGOUT_WR_VALID 0x4UL
#define ALT_TRIGOUT_TS_PRESENT 0x100UL
/* Time (seconds) of the last event */
#define ALT_TRIGOUT_TS_MASK_SEC 0x8UL
#define ALT_TRIGOUT_TS_SEC_MASK 0xffffffffffULL
#define ALT_TRIGOUT_TS_SEC_SHIFT 0
#define ALT_TRIGOUT_CH1_MASK 0x1000000000000ULL
#define ALT_TRIGOUT_CH2_MASK 0x2000000000000ULL
#define ALT_TRIGOUT_CH3_MASK 0x4000000000000ULL
#define ALT_TRIGOUT_CH4_MASK 0x8000000000000ULL
#define ALT_TRIGOUT_EXT_MASK 0x100000000000000ULL
/* Cycles part of timestamp fifo. */
#define ALT_TRIGOUT_TS_CYCLES 0x10UL
#define ALT_TRIGOUT_CYCLES_MASK 0xfffffffUL
#define ALT_TRIGOUT_CYCLES_SHIFT 0
struct alt_trigout {
/* [0x0]: REG (ro) Status register */
uint32_t status;
/* padding to: 2 words */
uint32_t __padding_0[1];
/* [0x8]: REG (ro) Time (seconds) of the last event */
uint64_t ts_mask_sec;
/* [0x10]: REG (ro) Cycles part of timestamp fifo. */
uint32_t ts_cycles;
};
#endif /* __CHEBY__ALT_TRIGOUT__H__ */
hdl/rtl/wb_gen/fmc_adc_alt_trigout.html deleted 100644 → 0
View file @ 9685afca
<HTML>
<HEAD>
<TITLE>alt_trigout</TITLE>
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</STYLE>
</HEAD>
<BODY>
<h1 class="heading">alt_trigout</h1>
<h3>None</h3>
<p></p>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=2 cellspacing=0 border=0>
<tr>
<th>H/W Address</th>
<th>Type</th>
<th>Name</th>
<th>HDL prefix</th>
<th>C prefix</th>
</tr>
<tr class="tr_odd">
<td class="td_code">0x00</td>
<td>REG</td>
<td><A href="#status">status</a></td>
<td class="td_code">status</td>
<td class="td_code">status</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#ts_mask_sec">ts_mask_sec</a></td>
<td class="td_code">ts_mask_sec</td>
<td class="td_code">ts_mask_sec</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#ts_cycles">ts_cycles</a></td>
<td class="td_code">ts_cycles</td>
<td class="td_code">ts_cycles</td>
</tr>
</table>
<h3><a name="sect_3_0">2. Register description</a></h3>
<a name="status"></a>
<h3><a name="sect_3_1">2.1. status</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigout_status</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x0</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">status</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x0</td></tr>
</table>
<p>
Status register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ts_present</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">wr_valid</td>
<td class="td_field" colspan="1">wr_link</td>
<td class="td_field" colspan="1">wr_enable</td>
</tr>
</table>
<ul>
<li><b>
wr_enable
</b>[<i>ro</i>]: Set when WR is enabled
<li><b>
wr_link
</b>[<i>ro</i>]: WR link status
<li><b>
wr_valid
</b>[<i>ro</i>]: Set when WR time is valid
<li><b>
ts_present
</b>[<i>ro</i>]: Set when the timestamp fifo is not empty
</ul>
<a name="ts_mask_sec"></a>
<h3><a name="sect_3_2">2.2. ts_mask_sec</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigout_ts_mask_sec</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x8</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">ts_mask_sec</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x8</td></tr>
</table>
<p>
Time (seconds) of the last event
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">63</td>
<td class="td_bit" colspan="1">62</td>
<td class="td_bit" colspan="1">61</td>
<td class="td_bit" colspan="1">60</td>
<td class="td_bit" colspan="1">59</td>
<td class="td_bit" colspan="1">58</td>
<td class="td_bit" colspan="1">57</td>
<td class="td_bit" colspan="1">56</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ext_mask</td>
</tr>
<tr>
<td class="td_bit" colspan="1">55</td>
<td class="td_bit" colspan="1">54</td>
<td class="td_bit" colspan="1">53</td>
<td class="td_bit" colspan="1">52</td>
<td class="td_bit" colspan="1">51</td>
<td class="td_bit" colspan="1">50</td>
<td class="td_bit" colspan="1">49</td>
<td class="td_bit" colspan="1">48</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ch4_mask</td>
<td class="td_field" colspan="1">ch3_mask</td>
<td class="td_field" colspan="1">ch2_mask</td>
<td class="td_field" colspan="1">ch1_mask</td>
</tr>
<tr>
<td class="td_bit" colspan="1">47</td>
<td class="td_bit" colspan="1">46</td>
<td class="td_bit" colspan="1">45</td>
<td class="td_bit" colspan="1">44</td>
<td class="td_bit" colspan="1">43</td>
<td class="td_bit" colspan="1">42</td>
<td class="td_bit" colspan="1">41</td>
<td class="td_bit" colspan="1">40</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">39</td>
<td class="td_bit" colspan="1">38</td>
<td class="td_bit" colspan="1">37</td>
<td class="td_bit" colspan="1">36</td>
<td class="td_bit" colspan="1">35</td>
<td class="td_bit" colspan="1">34</td>
<td class="td_bit" colspan="1">33</td>
<td class="td_bit" colspan="1">32</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[39:32]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">ts_sec[7:0]</td>
</tr>
</table>
<ul>
<li><b>
ts_sec
</b>[<i>ro</i>]: Seconds part of the timestamp
<li><b>
ch1_mask
</b>[<i>ro</i>]: Set if channel 1 triggered
<li><b>
ch2_mask
</b>[<i>ro</i>]: Set if channel 2 triggered
<li><b>
ch3_mask
</b>[<i>ro</i>]: Set if channel 3 triggered
<li><b>
ch4_mask
</b>[<i>ro</i>]: Set if channel 4 triggered
<li><b>
ext_mask
</b>[<i>ro</i>]: Set if external trigger
</ul>
<a name="ts_cycles"></a>
<h3><a name="sect_3_3">2.3. ts_cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigout_ts_cycles</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x10</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">ts_cycles</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x10</td></tr>
</table>
<p>
Cycles part of timestamp fifo.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="4">cycles[27:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">cycles[7:0]</td>
</tr>
</table>
<ul>
<li><b>
cycles
</b>[<i>ro</i>]: Cycles
</ul>
</BODY>
</HTML>
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @ e084c507
......@@ -201,14 +201,14 @@ module main;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000001);
// FMC-ADC core channel configuration
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h00007fff);
// FMC-ADC core trigger configuration
val = (16'h100 << `FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET) |
......
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ e084c507
`define ADDR_FMC_ADC_100MS_CSR_CTL 10'h0
`define FMC_ADC_100MS_CSR_SIZE 344
`define ADDR_FMC_ADC_100MS_CSR_CTL 'h0
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD_OFFSET 0
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD 32'h00000003
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD 'h3
`define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE_OFFSET 2
`define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE 32'h00000004
`define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE 'h4
`define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N_OFFSET 3
`define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 32'h00000008
`define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 'h8
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP_OFFSET 4
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 32'h00000010
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 'h10
`define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN_OFFSET 5
`define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN 32'h00000020
`define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN 'h20
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED_OFFSET 6
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED 32'h00000040
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED 'h40
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED_OFFSET 7
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED 32'h00000080
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED 'h80
`define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT_OFFSET 8
`define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT 32'h00000100
`define ADDR_FMC_ADC_100MS_CSR_STA 10'h4
`define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT 'h100
`define ADDR_FMC_ADC_100MS_CSR_STA 'h4
`define FMC_ADC_100MS_CSR_STA_FSM_OFFSET 0
`define FMC_ADC_100MS_CSR_STA_FSM 32'h00000007
`define FMC_ADC_100MS_CSR_STA_FSM 'h7
`define FMC_ADC_100MS_CSR_STA_SERDES_PLL_OFFSET 3
`define FMC_ADC_100MS_CSR_STA_SERDES_PLL 32'h00000008
`define FMC_ADC_100MS_CSR_STA_SERDES_PLL 'h8
`define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED_OFFSET 4
`define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED 32'h00000010
`define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED 'h10
`define FMC_ADC_100MS_CSR_STA_ACQ_CFG_OFFSET 5
`define FMC_ADC_100MS_CSR_STA_ACQ_CFG 32'h00000020
`define ADDR_FMC_ADC_100MS_CSR_TRIG_STAT 10'h8
`define FMC_ADC_100MS_CSR_STA_ACQ_CFG 'h20
`define ADDR_FMC_ADC_100MS_CSR_TRIG_STAT 'h8
`define FMC_ADC_100MS_CSR_TRIG_STAT_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_STAT_EXT 32'h00000001
`define FMC_ADC_100MS_CSR_TRIG_STAT_EXT 'h1
`define FMC_ADC_100MS_CSR_TRIG_STAT_SW_OFFSET 1
`define FMC_ADC_100MS_CSR_TRIG_STAT_SW 32'h00000002
`define FMC_ADC_100MS_CSR_TRIG_STAT_SW 'h2
`define FMC_ADC_100MS_CSR_TRIG_STAT_TIME_OFFSET 4
`define FMC_ADC_100MS_CSR_TRIG_STAT_TIME 32'h00000010
`define FMC_ADC_100MS_CSR_TRIG_STAT_TIME 'h10
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH1 32'h00000100
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH1 'h100
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH2_OFFSET 9
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH2 32'h00000200
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH2 'h200
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH3_OFFSET 10
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH3 'h400
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH4 32'h00000800
`define ADDR_FMC_ADC_100MS_CSR_TRIG_EN 10'hc
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH4 'h800
`define ADDR_FMC_ADC_100MS_CSR_TRIG_EN 'hc
`define FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_EN_EXT 32'h00000001
`define FMC_ADC_100MS_CSR_TRIG_EN_EXT 'h1
`define FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET 1
`define FMC_ADC_100MS_CSR_TRIG_EN_SW 32'h00000002
`define FMC_ADC_100MS_CSR_TRIG_EN_SW 'h2
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET 4
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME 32'h00000010
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME 'h10
`define FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME_OFFSET 5
`define FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME 32'h00000020
`define FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME 'h20
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1 32'h00000100
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1 'h100
`define FMC_ADC_100MS_CSR_TRIG_EN_CH2_OFFSET 9
`define FMC_ADC_100MS_CSR_TRIG_EN_CH2 32'h00000200
`define FMC_ADC_100MS_CSR_TRIG_EN_CH2 'h200
`define FMC_ADC_100MS_CSR_TRIG_EN_CH3_OFFSET 10
`define FMC_ADC_100MS_CSR_TRIG_EN_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_EN_CH3 'h400
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4 32'h00000800
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4 'h800
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT_OFFSET 16
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT 32'h00010000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT 'h10000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1_OFFSET 24
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1 32'h01000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1 'h1000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2_OFFSET 25
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2 32'h02000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2 'h2000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3_OFFSET 26
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3 32'h04000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3 'h4000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4_OFFSET 27
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4 32'h08000000
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POL 10'h10
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4 'h8000000
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POL 'h10
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT 32'h00000001
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT 'h1
`define FMC_ADC_100MS_CSR_TRIG_POL_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_POL_CH1 32'h00000100
`define FMC_ADC_100MS_CSR_TRIG_POL_CH1 'h100
`define FMC_ADC_100MS_CSR_TRIG_POL_CH2_OFFSET 9
`define FMC_ADC_100MS_CSR_TRIG_POL_CH2 32'h00000200
`define FMC_ADC_100MS_CSR_TRIG_POL_CH2 'h200
`define FMC_ADC_100MS_CSR_TRIG_POL_CH3_OFFSET 10
`define FMC_ADC_100MS_CSR_TRIG_POL_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_POL_CH3 'h400
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4 32'h00000800
`define ADDR_FMC_ADC_100MS_CSR_EXT_TRIG_DLY 10'h14
`define ADDR_FMC_ADC_100MS_CSR_SW_TRIG 10'h18
`define ADDR_FMC_ADC_100MS_CSR_SHOTS 10'h1c
`define FMC_ADC_100MS_CSR_SHOTS_NB_OFFSET 0
`define FMC_ADC_100MS_CSR_SHOTS_NB 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_MULTI_DEPTH 10'h20
`define ADDR_FMC_ADC_100MS_CSR_SHOTS_CNT 10'h24
`define FMC_ADC_100MS_CSR_SHOTS_CNT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_SHOTS_CNT_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POS 10'h28
`define ADDR_FMC_ADC_100MS_CSR_FS_FREQ 10'h2c
`define ADDR_FMC_ADC_100MS_CSR_SR 10'h30
`define FMC_ADC_100MS_CSR_SR_UNDERSAMPLE_OFFSET 0
`define FMC_ADC_100MS_CSR_SR_UNDERSAMPLE 32'hffffffff
`define ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES 10'h34
`define ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES 10'h38
`define ADDR_FMC_ADC_100MS_CSR_SAMPLES_CNT 10'h3c
`define ADDR_FMC_ADC_100MS_CSR_CH1_CTL 10'h80
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4 'h800
`define ADDR_FMC_ADC_100MS_CSR_EXT_TRIG_DLY 'h14
`define ADDR_FMC_ADC_100MS_CSR_SW_TRIG 'h18
`define ADDR_FMC_ADC_100MS_CSR_SHOTS 'h1c
`define FMC_ADC_100MS_CSR_SHOTS_NBR_OFFSET 0
`define FMC_ADC_100MS_CSR_SHOTS_NBR 'hffff
`define FMC_ADC_100MS_CSR_SHOTS_REMAIN_OFFSET 16
`define FMC_ADC_100MS_CSR_SHOTS_REMAIN 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_MULTI_DEPTH 'h20
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POS 'h24
`define ADDR_FMC_ADC_100MS_CSR_FS_FREQ 'h28
`define ADDR_FMC_ADC_100MS_CSR_UNDERSAMPLE 'h2c
`define ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES 'h30
`define ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES 'h34
`define ADDR_FMC_ADC_100MS_CSR_SAMPLES_CNT 'h38
`define ADDR_FMC_ADC_100MS_CSR_CH1_CTL 'h80
`define FMC_ADC_100MS_CSR_CH1_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH1_STA 10'h84
`define FMC_ADC_100MS_CSR_CH1_CTL_SSR 'h7f
`define ADDR_FMC_ADC_100MS_CSR_CH1_STA 'h84
`define FMC_ADC_100MS_CSR_CH1_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_GAIN 10'h88
`define FMC_ADC_100MS_CSR_CH1_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_OFFSET 10'h8c
`define FMC_ADC_100MS_CSR_CH1_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_SAT 10'h90
`define FMC_ADC_100MS_CSR_CH1_STA_VAL 'hffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_CALIB 'h88
`define FMC_ADC_100MS_CSR_CH1_CALIB_GAIN_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_CALIB_GAIN 'hffff
`define FMC_ADC_100MS_CSR_CH1_CALIB_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CSR_CH1_CALIB_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH1_SAT 'h8c
`define FMC_ADC_100MS_CSR_CH1_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_THRES 10'h94
`define FMC_ADC_100MS_CSR_CH1_SAT_VAL 'h7fff
`define ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_THRES 'h90
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL 'hffff
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_DLY 10'h98
`define ADDR_FMC_ADC_100MS_CSR_CH2_CTL 10'h100
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_DLY 'h94
`define ADDR_FMC_ADC_100MS_CSR_CH2_CTL 'hc0
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH2_STA 10'h104
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR 'h7f
`define ADDR_FMC_ADC_100MS_CSR_CH2_STA 'hc4
`define FMC_ADC_100MS_CSR_CH2_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_GAIN 10'h108
`define FMC_ADC_100MS_CSR_CH2_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_OFFSET 10'h10c
`define FMC_ADC_100MS_CSR_CH2_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_SAT 10'h110
`define FMC_ADC_100MS_CSR_CH2_STA_VAL 'hffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_CALIB 'hc8
`define FMC_ADC_100MS_CSR_CH2_CALIB_GAIN_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_CALIB_GAIN 'hffff
`define FMC_ADC_100MS_CSR_CH2_CALIB_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CSR_CH2_CALIB_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH2_SAT 'hcc
`define FMC_ADC_100MS_CSR_CH2_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES 10'h114
`define FMC_ADC_100MS_CSR_CH2_SAT_VAL 'h7fff
`define ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES 'hd0
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL 'hffff
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_DLY 10'h118
`define ADDR_FMC_ADC_100MS_CSR_CH3_CTL 10'h180
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_DLY 'hd4
`define ADDR_FMC_ADC_100MS_CSR_CH3_CTL 'h100
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH3_STA 10'h184
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR 'h7f
`define ADDR_FMC_ADC_100MS_CSR_CH3_STA 'h104
`define FMC_ADC_100MS_CSR_CH3_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_GAIN 10'h188
`define FMC_ADC_100MS_CSR_CH3_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_OFFSET 10'h18c
`define FMC_ADC_100MS_CSR_CH3_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_SAT 10'h190
`define FMC_ADC_100MS_CSR_CH3_STA_VAL 'hffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_CALIB 'h108
`define FMC_ADC_100MS_CSR_CH3_CALIB_GAIN_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_CALIB_GAIN 'hffff
`define FMC_ADC_100MS_CSR_CH3_CALIB_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CSR_CH3_CALIB_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH3_SAT 'h10c
`define FMC_ADC_100MS_CSR_CH3_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES 10'h194
`define FMC_ADC_100MS_CSR_CH3_SAT_VAL 'h7fff
`define ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES 'h110
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL 'hffff
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_DLY 10'h198
`define ADDR_FMC_ADC_100MS_CSR_CH4_CTL 10'h200
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_DLY 'h114
`define ADDR_FMC_ADC_100MS_CSR_CH4_CTL 'h140
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH4_STA 10'h204
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR 'h7f
`define ADDR_FMC_ADC_100MS_CSR_CH4_STA 'h144
`define FMC_ADC_100MS_CSR_CH4_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_GAIN 10'h208
`define FMC_ADC_100MS_CSR_CH4_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_OFFSET 10'h20c
`define FMC_ADC_100MS_CSR_CH4_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_SAT 10'h210
`define FMC_ADC_100MS_CSR_CH4_STA_VAL 'hffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_CALIB 'h148
`define FMC_ADC_100MS_CSR_CH4_CALIB_GAIN_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_CALIB_GAIN 'hffff
`define FMC_ADC_100MS_CSR_CH4_CALIB_OFFSET_OFFSET 16
`define FMC_ADC_100MS_CSR_CH4_CALIB_OFFSET 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH4_SAT 'h14c
`define FMC_ADC_100MS_CSR_CH4_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES 10'h214
`define FMC_ADC_100MS_CSR_CH4_SAT_VAL 'h7fff
`define ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES 'h150
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL 'hffff
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_DLY 10'h218
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST 'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_DLY 'h154
hdl/testbench/svec_ref_design/main.sv
View file @ e084c507
......@@ -288,14 +288,14 @@ module main;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000001);
// FMC-ADC core channel configuration
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h00007fff);
// FMC-ADC core trigger configuration
val = (16'h100 << `FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET) |
......
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