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FMC ADC 100M 14b 4cha - Gateware
Commit f48f3593 authored by Matthieu Cattin's avatar Matthieu Cattin
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syn: spec-fmc-adc firmware release 3.0

parent 3c4e2201
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Showing with 3170 additions and 6455 deletions
hdl/spec/rtl/sdb_meta_pkg.vhd
View file @ f48f3593
......@@ -54,13 +54,13 @@ package sdb_meta_pkg is
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "dce448c21e7f9426dd5b39d1ef1d0496",
syn_commit_id => "697546304b7a1890aba8d6effd935a0f",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130729",
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date => x"20140116",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
......@@ -70,7 +70,7 @@ package sdb_meta_pkg is
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00030000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20131203", -- yyyymmdd
date => x"20140116", -- yyyymmdd
name => "spec_fmcadc100m14b "));
......
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ f48f3593
......@@ -353,754 +353,455 @@
<file xil_pn:name="../../ip_cores/wb_ddr_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/adc_serdes.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/monostable/monostable_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/utils/utils_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/sdb_meta_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/timetag_core/rtl/timetag_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../rtl/spec_top_fmc_adc_100Ms.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="222"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
</files>
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
View file @ f48f3593
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Mon Jul 29 11:02:53 2013
pcbe15575:: Thu Jan 16 18:02:06 2014
par -w -intstyle ise -ol high -mt off spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
......@@ -22,16 +22,16 @@ Device speed data version: "PRODUCTION 1.20 2011-10-03".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 6,876 out of 54,576 12%
Number used as Flip Flops: 6,876
Number of Slice Registers: 6,698 out of 54,576 12%
Number used as Flip Flops: 6,698
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,566 out of 27,288 20%
Number used as logic: 5,147 out of 27,288 18%
Number using O6 output only: 3,316
Number using O5 output only: 286
Number using O5 and O6: 1,545
Number of Slice LUTs: 5,758 out of 27,288 21%
Number used as logic: 5,404 out of 27,288 19%
Number using O6 output only: 3,644
Number using O5 output only: 368
Number using O5 and O6: 1,392
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -40,18 +40,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 417
Number with same-slice register load: 404
Number with same-slice carry load: 13
Number used exclusively as route-thrus: 352
Number with same-slice register load: 328
Number with same-slice carry load: 24
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,422 out of 6,822 35%
Nummber of MUXCYs used: 1,464 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,669
Number with an unused Flip Flop: 1,694 out of 7,669 22%
Number with an unused LUT: 2,103 out of 7,669 27%
Number of fully used LUT-FF pairs: 3,872 out of 7,669 50%
Number of occupied Slices: 2,468 out of 6,822 36%
Nummber of MUXCYs used: 1,440 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,910
Number with an unused Flip Flop: 1,939 out of 7,910 24%
Number with an unused LUT: 2,152 out of 7,910 27%
Number of fully used LUT-FF pairs: 3,819 out of 7,910 48%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -66,8 +66,8 @@ IO Utilization:
Number of LOCed IOBs: 188 out of 188 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 27 out of 116 23%
Number of RAMB8BWERs: 2 out of 232 1%
Number of RAMB16BWERs: 26 out of 116 22%
Number of RAMB8BWERs: 4 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
......@@ -109,41 +109,41 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 17 secs
Finished initial Timing Analysis. REAL time: 17 secs
Starting initial Timing Analysis. REAL time: 24 secs
Finished initial Timing Analysis. REAL time: 24 secs
WARNING:Par:288 - The signal aux_buttons_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal aux_buttons_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal aux_buttons_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal aux_buttons_i<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 39136 unrouted; REAL time: 19 secs
Phase 1 : 40071 unrouted; REAL time: 26 secs
Phase 2 : 32980 unrouted; REAL time: 23 secs
Phase 2 : 34430 unrouted; REAL time: 30 secs
Phase 3 : 13250 unrouted; REAL time: 46 secs
Phase 3 : 13949 unrouted; REAL time: 54 secs
Phase 4 : 13258 unrouted; (Setup:0, Hold:5649, Component Switching Limit:0) REAL time: 49 secs
Phase 4 : 13983 unrouted; (Setup:0, Hold:7686, Component Switching Limit:0) REAL time: 1 mins
Updating file: spec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:5649, Component Switching Limit:0) REAL time: 1 mins 17 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:7456, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:5649, Component Switching Limit:0) REAL time: 1 mins 17 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:7456, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:5649, Component Switching Limit:0) REAL time: 1 mins 17 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7456, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:5649, Component Switching Limit:0) REAL time: 1 mins 17 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7456, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 18 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 21 secs
Total REAL time to Router completion: 1 mins 21 secs
Total CPU time to Router completion: 1 mins 20 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 32 secs
Total REAL time to Router completion: 1 mins 32 secs
Total CPU time to Router completion: 1 mins 25 secs
Partition Implementation Status
-------------------------------
......@@ -161,20 +161,20 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X3Y13| No | 1234 | 0.067 | 1.278 |
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y2| No | 162 | 0.238 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y12| No | 650 | 0.185 | 1.398 |
| clk | BUFGMUX_X2Y12| No | 641 | 0.187 | 1.398 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X3Y13| No | 1251 | 0.069 | 1.280 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_mcb_d | | | | | |
| rp_clk | BUFGMUX_X2Y3| No | 81 | 0.052 | 1.285 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_mezzanin | | | | | |
|e_0/cmp_fmc_adc_100M | | | | | |
| s_core/fs_clk | BUFGMUX_X2Y2| No | 160 | 0.237 | 1.473 |
| rp_clk | BUFGMUX_X2Y3| No | 82 | 0.072 | 1.285 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
......@@ -290,28 +290,21 @@ Asterisk (*) preceding a constraint indicates it was not met.
_ddr3_ctrl_memc3_infrastructure_inst_clk_ | | | | |
2x_0" TS_SYS_CLK5 / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.034ns| 7.966ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.261ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.039ns| 4.961ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.084ns| | 0| 0
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.027ns| 4.973ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.136ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.073ns| 7.927ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.275ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
0Ms_core_dco_clk = PERIOD TIMEGRP | | | | |
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_100 | | | | |
Ms_core_dco_clk" TS_adc_dco_n_i H | | | | |
IGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | SETUP | 0.399ns| 7.601ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.381ns| | 0| 0
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_ | | | | |
100Ms_core_fs_clk_buf" TS_cmp_fmc | | | | |
_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_SYS_CLK5 = PERIOD TIMEGRP "SYS_CLK5" 3 | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
ns HIGH 50% | | | | |
......@@ -319,6 +312,13 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_ddr_clk_buf = PERIOD TIMEGRP "ddr_clk_ | MINLOWPULSE | 0.428ns| 2.572ns| 0| 0
buf" TS_clk20_vcxo_i / 16.6666667 | | | | |
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_10 | SETUP | 0.806ns| 7.194ns| 0| 0
0Ms_core_fs_clk_buf = PERIOD TIMEGRP | HOLD | 0.393ns| | 0| 0
"cmp_fmc_adc_mezzanine_0_cmp_fmc_adc_ | | | | |
100Ms_core_fs_clk_buf" TS_cmp_fmc | | | | |
_adc_mezzanine_0_cmp_fmc_adc_100Ms_core_d | | | | |
co_clk / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_adc_dco_n_i = PERIOD TIMEGRP "adc_dco_ | MINPERIOD | 1.075ns| 0.925ns| 0| 0
n_i" 2 ns HIGH 50% | | | | |
......@@ -348,8 +348,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 4.744ns| 7.255ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.380ns| | 0| 0
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 4.451ns| 7.548ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.393ns| | 0| 0
nfrastructure_inst_mcb_drp_clk_bufg_in_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr | | | | |
_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank | | | | |
......@@ -412,12 +412,12 @@ Derived Constraints for TS_p2l_clkn
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.961ns| 0| 0| 0| 29035|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.961ns| 0| 0| 0| 29035|
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.973ns| 0| 0| 0| 30234|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.973ns| 0| 0| 0| 30234|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.961ns| N/A| 0| 0| 29035| 0|
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.973ns| N/A| 0| 0| 30234| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -427,10 +427,10 @@ Derived Constraints for TS_clk20_vcxo_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 418806|
| TS_sys_clk_125_buf | 8.000ns| 7.966ns| N/A| 0| 0| 408406| 0|
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 410728|
| TS_sys_clk_125_buf | 8.000ns| 7.927ns| N/A| 0| 0| 400328| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 10400|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 7.255ns| N/A| 0| 0| 10400| 0|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 7.548ns| N/A| 0| 0| 10400| 0|
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_mcb_drp_clk_buf| | | | | | | |
......@@ -472,10 +472,10 @@ Derived Constraints for TS_adc_dco_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc_dco_n_i | 2.000ns| 0.925ns| 1.900ns| 0| 0| 0| 16183|
| TS_cmp_fmc_adc_mezzanine_0_cmp| 2.000ns| 1.636ns| 1.900ns| 0| 0| 0| 16183|
|TS_adc_dco_n_i | 2.000ns| 0.925ns| 1.798ns| 0| 0| 0| 47928|
| TS_cmp_fmc_adc_mezzanine_0_cmp| 2.000ns| 1.636ns| 1.798ns| 0| 0| 0| 47928|
| _fmc_adc_100Ms_core_dco_clk | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 8.000ns| 7.601ns| N/A| 0| 0| 16183| 0|
| TS_cmp_fmc_adc_mezzanine_0_cm| 8.000ns| 7.194ns| N/A| 0| 0| 47928| 0|
| p_fmc_adc_100Ms_core_fs_clk_b| | | | | | | |
| uf | | | | | | | |
| TS_cmp_fmc_adc_mezzanine_0_cm| 1.000ns| N/A| N/A| 0| 0| 0| 0|
......@@ -497,10 +497,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 24 secs
Total CPU time to PAR completion: 1 mins 24 secs
Total REAL time to PAR completion: 1 mins 35 secs
Total CPU time to PAR completion: 1 mins 28 secs
Peak Memory Usage: 332 MB
Peak Memory Usage: 335 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
View file @ f48f3593
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
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This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
View file @ f48f3593
......@@ -11,23 +11,23 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jul 29 10:58:04 2013
Mapped Date : Thu Jan 16 17:57:07 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,876 out of 54,576 12%
Number used as Flip Flops: 6,876
Number of Slice Registers: 6,698 out of 54,576 12%
Number used as Flip Flops: 6,698
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,566 out of 27,288 20%
Number used as logic: 5,147 out of 27,288 18%
Number using O6 output only: 3,316
Number using O5 output only: 286
Number using O5 and O6: 1,545
Number of Slice LUTs: 5,758 out of 27,288 21%
Number used as logic: 5,404 out of 27,288 19%
Number using O6 output only: 3,644
Number using O5 output only: 368
Number using O5 and O6: 1,392
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -36,21 +36,21 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 417
Number with same-slice register load: 404
Number with same-slice carry load: 13
Number used exclusively as route-thrus: 352
Number with same-slice register load: 328
Number with same-slice carry load: 24
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,422 out of 6,822 35%
Nummber of MUXCYs used: 1,464 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,669
Number with an unused Flip Flop: 1,694 out of 7,669 22%
Number with an unused LUT: 2,103 out of 7,669 27%
Number of fully used LUT-FF pairs: 3,872 out of 7,669 50%
Number of unique control sets: 265
Number of occupied Slices: 2,468 out of 6,822 36%
Nummber of MUXCYs used: 1,440 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,910
Number with an unused Flip Flop: 1,939 out of 7,910 24%
Number with an unused LUT: 2,152 out of 7,910 27%
Number of fully used LUT-FF pairs: 3,819 out of 7,910 48%
Number of unique control sets: 237
Number of slice register sites lost
to control set restrictions: 682 out of 54,576 1%
to control set restrictions: 548 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -63,8 +63,8 @@ IO Utilization:
Number of LOCed IOBs: 188 out of 188 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 27 out of 116 23%
Number of RAMB8BWERs: 2 out of 232 1%
Number of RAMB16BWERs: 26 out of 116 22%
Number of RAMB8BWERs: 4 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.76
Average Fanout of Non-Clock Nets: 3.80
Peak Memory Usage: 411 MB
Total REAL time to MAP completion: 4 mins 42 secs
Total CPU time to MAP completion (all processors): 4 mins 42 secs
Peak Memory Usage: 409 MB
Total REAL time to MAP completion: 4 mins 52 secs
Total CPU time to MAP completion (all processors): 4 mins 43 secs
Table of Contents
-----------------
......@@ -164,8 +164,8 @@ INFO:LIT:243 - Logical network
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown):
N862,
N864,
N798,
N800,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......
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