Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC ADC 100M 14b 4cha - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
8
Issues
8
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC ADC 100M 14b 4cha - Gateware
Commits
f61a80f5
Commit
f61a80f5
authored
Jul 23, 2013
by
Matthieu Cattin
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
hdl: Update wbgen2 and re-generate cores.
parent
5f189f2c
Show whitespace changes
Inline
Side-by-side
Showing
9 changed files
with
61 additions
and
90 deletions
+61
-90
carrier_csr.tex
documentation/manuals/firmware/carrier_csr.tex
+4
-4
fmc_adc_100Ms_csr.tex
documentation/manuals/firmware/fmc_adc_100Ms_csr.tex
+47
-50
irq_controller_regs.tex
documentation/manuals/firmware/irq_controller_regs.tex
+4
-30
fmc_adc_100Ms_csr.vhd
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
+1
-1
fmc_adc_100Ms_csr.h
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
+1
-1
carrier_csr.vhd
hdl/spec/rtl/carrier_csr.vhd
+1
-1
irq_controller_regs.vhd
hdl/spec/rtl/irq_controller_regs.vhd
+1
-1
carrier_csr.h
hdl/spec/wb_gen/carrier_csr.h
+1
-1
irq_controller_regs.h
hdl/spec/wb_gen/irq_controller_regs.h
+1
-1
No files found.
documentation/manuals/firmware/carrier_csr.tex
View file @
f61a80f5
...
@@ -82,22 +82,22 @@ Reserved
...
@@ -82,22 +82,22 @@ Reserved
@item @code
{
0
}
@item @code
{
0
}
@tab R/W @tab
@tab R/W @tab
@code
{
LED
_
GREEN
}
@code
{
LED
_
GREEN
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Green LED
Green LED
@item @code
{
1
}
@item @code
{
1
}
@tab R/W @tab
@tab R/W @tab
@code
{
LED
_
RED
}
@code
{
LED
_
RED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Red LED
Red LED
@item @code
{
2
}
@item @code
{
2
}
@tab R/W @tab
@tab R/W @tab
@code
{
DAC
_
CLR
_
N
}
@code
{
DAC
_
CLR
_
N
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
DAC clear
DAC clear
@item @code
{
31...3
}
@item @code
{
31...3
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
...
documentation/manuals/firmware/fmc_adc_100Ms_csr.tex
View file @
f61a80f5
...
@@ -116,42 +116,42 @@ Channel 4 offset calibration register
...
@@ -116,42 +116,42 @@ Channel 4 offset calibration register
@item @code
{
1...0
}
@item @code
{
1...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
FSM
_
CMD
}
@code
{
FSM
_
CMD
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
State machine commands (ignore on read)
State machine commands (ignore on read)
@item @code
{
2
}
@item @code
{
2
}
@tab R/W @tab
@tab R/W @tab
@code
{
FMC
_
CLK
_
OE
}
@code
{
FMC
_
CLK
_
OE
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
FMC Si750 output enable
FMC Si750 output enable
@item @code
{
3
}
@item @code
{
3
}
@tab R/W @tab
@tab R/W @tab
@code
{
OFFSET
_
DAC
_
CLR
_
N
}
@code
{
OFFSET
_
DAC
_
CLR
_
N
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Offset DACs clear (active low)
Offset DACs clear (active low)
@item @code
{
4
}
@item @code
{
4
}
@tab W/O @tab
@tab W/O @tab
@code
{
MAN
_
BITSLIP
}
@code
{
MAN
_
BITSLIP
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Manual serdes bitslip (ignore on read)
Manual serdes bitslip (ignore on read)
@item @code
{
5
}
@item @code
{
5
}
@tab R/W @tab
@tab R/W @tab
@code
{
TEST
_
DATA
_
EN
}
@code
{
TEST
_
DATA
_
EN
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Enable test data
Enable test data
@item @code
{
6
}
@item @code
{
6
}
@tab R/W @tab
@tab R/W @tab
@code
{
TRIG
_
LED
}
@code
{
TRIG
_
LED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Manual TRIG LED
Manual TRIG LED
@item @code
{
7
}
@item @code
{
7
}
@tab R/W @tab
@tab R/W @tab
@code
{
ACQ
_
LED
}
@code
{
ACQ
_
LED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Manual ACQ LED
Manual ACQ LED
@item @code
{
31...8
}
@item @code
{
31...8
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -199,37 +199,37 @@ Reserved
...
@@ -199,37 +199,37 @@ Reserved
@item @code
{
0
}
@item @code
{
0
}
@tab R/W @tab
@tab R/W @tab
@code
{
HW
_
TRIG
_
SEL
}
@code
{
HW
_
TRIG
_
SEL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Hardware trigger selection
Hardware trigger selection
@item @code
{
1
}
@item @code
{
1
}
@tab R/W @tab
@tab R/W @tab
@code
{
HW
_
TRIG
_
POL
}
@code
{
HW
_
TRIG
_
POL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Hardware trigger polarity
Hardware trigger polarity
@item @code
{
2
}
@item @code
{
2
}
@tab R/W @tab
@tab R/W @tab
@code
{
HW
_
TRIG
_
EN
}
@code
{
HW
_
TRIG
_
EN
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Hardware trigger enable
Hardware trigger enable
@item @code
{
3
}
@item @code
{
3
}
@tab R/W @tab
@tab R/W @tab
@code
{
SW
_
TRIG
_
EN
}
@code
{
SW
_
TRIG
_
EN
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Software trigger enable
Software trigger enable
@item @code
{
5...4
}
@item @code
{
5...4
}
@tab R/W @tab
@tab R/W @tab
@code
{
INT
_
TRIG
_
SEL
}
@code
{
INT
_
TRIG
_
SEL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Channel selection for internal trigger
Channel selection for internal trigger
@item @code
{
15...6
}
@item @code
{
15...6
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
INT
_
TRIG
_
THRES
}
@code
{
INT
_
TRIG
_
THRES
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Threshold for internal trigger
Threshold for internal trigger
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -248,7 +248,7 @@ Threshold for internal trigger
...
@@ -248,7 +248,7 @@ Threshold for internal trigger
@item @code
{
31...0
}
@item @code
{
31...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
TRIG
_
DLY
}
@code
{
TRIG
_
DLY
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Trigger delay value
Trigger delay value
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -262,24 +262,21 @@ Writing (anything) to this register generates a software trigger.
...
@@ -262,24 +262,21 @@ Writing (anything) to this register generates a software trigger.
@item @code
{
31...0
}
@item @code
{
31...0
}
@tab W/O @tab
@tab W/O @tab
@code
{
SW
_
TRIG
}
@code
{
SW
_
TRIG
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Software trigger (ignore on read)
Software trigger (ignore on read)
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code
{
shots
}
- Number of shots
@regsection @code
{
shots
}
- Number of shots
@multitable @columnfractions .10 .10 .15 .10 .55
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
15...0
}
@item @code
{
15...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
NB
}
@code
{
NB
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Number of shots
Number of shots
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -306,12 +303,12 @@ Trigger address
...
@@ -306,12 +303,12 @@ Trigger address
@item @code
{
15...0
}
@item @code
{
15...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
DECI
}
@code
{
DECI
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Sample rate decimation
Sample rate decimation
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -325,7 +322,7 @@ Reserved
...
@@ -325,7 +322,7 @@ Reserved
@item @code
{
31...0
}
@item @code
{
31...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
PRE
_
SAMPLES
}
@code
{
PRE
_
SAMPLES
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Pre-trigger samples
Pre-trigger samples
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -338,7 +335,7 @@ Pre-trigger samples
...
@@ -338,7 +335,7 @@ Pre-trigger samples
@item @code
{
31...0
}
@item @code
{
31...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
POST
_
SAMPLES
}
@code
{
POST
_
SAMPLES
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Post-trigger samples
Post-trigger samples
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -364,12 +361,12 @@ Samples counter
...
@@ -364,12 +361,12 @@ Samples counter
@item @code
{
6...0
}
@item @code
{
6...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
SSR
}
@code
{
SSR
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Solid state relays control for channel 1
Solid state relays control for channel 1
@item @code
{
31...7
}
@item @code
{
31...7
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -402,12 +399,12 @@ Reserved
...
@@ -402,12 +399,12 @@ Reserved
@item @code
{
15...0
}
@item @code
{
15...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
VAL
}
@code
{
VAL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Gain calibration for channel 1
Gain calibration for channel 1
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -421,12 +418,12 @@ Reserved
...
@@ -421,12 +418,12 @@ Reserved
@item @code
{
15...0
}
@item @code
{
15...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
VAL
}
@code
{
VAL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Offset calibration for channel 1
Offset calibration for channel 1
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -440,12 +437,12 @@ Reserved
...
@@ -440,12 +437,12 @@ Reserved
@item @code
{
6...0
}
@item @code
{
6...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
SSR
}
@code
{
SSR
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Solid state relays control for channel 2
Solid state relays control for channel 2
@item @code
{
31...7
}
@item @code
{
31...7
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -478,12 +475,12 @@ Reserved
...
@@ -478,12 +475,12 @@ Reserved
@item @code
{
15...0
}
@item @code
{
15...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
VAL
}
@code
{
VAL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Gain calibration for channel 2
Gain calibration for channel 2
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -497,12 +494,12 @@ Reserved
...
@@ -497,12 +494,12 @@ Reserved
@item @code
{
15...0
}
@item @code
{
15...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
VAL
}
@code
{
VAL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Offset calibration for channel 2
Offset calibration for channel 2
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -516,12 +513,12 @@ Reserved
...
@@ -516,12 +513,12 @@ Reserved
@item @code
{
6...0
}
@item @code
{
6...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
SSR
}
@code
{
SSR
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Solid state relays control for channel 3
Solid state relays control for channel 3
@item @code
{
31...7
}
@item @code
{
31...7
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -554,12 +551,12 @@ Reserved
...
@@ -554,12 +551,12 @@ Reserved
@item @code
{
15...0
}
@item @code
{
15...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
VAL
}
@code
{
VAL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Gain calibration for channel 3
Gain calibration for channel 3
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -573,12 +570,12 @@ Reserved
...
@@ -573,12 +570,12 @@ Reserved
@item @code
{
15...0
}
@item @code
{
15...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
VAL
}
@code
{
VAL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Offset calibration for channel 3
Offset calibration for channel 3
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -592,12 +589,12 @@ Reserved
...
@@ -592,12 +589,12 @@ Reserved
@item @code
{
6...0
}
@item @code
{
6...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
SSR
}
@code
{
SSR
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Solid state relays control for channel 4
Solid state relays control for channel 4
@item @code
{
31...7
}
@item @code
{
31...7
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -630,12 +627,12 @@ Reserved
...
@@ -630,12 +627,12 @@ Reserved
@item @code
{
15...0
}
@item @code
{
15...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
VAL
}
@code
{
VAL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Gain calibration for channel 4
Gain calibration for channel 4
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
@@ -649,12 +646,12 @@ Reserved
...
@@ -649,12 +646,12 @@ Reserved
@item @code
{
15...0
}
@item @code
{
15...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
VAL
}
@code
{
VAL
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Offset calibration for channel 4
Offset calibration for channel 4
@item @code
{
31...16
}
@item @code
{
31...16
}
@tab R/W @tab
@tab R/W @tab
@code
{
RESERVED
}
@code
{
RESERVED
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Reserved
Reserved
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@multitable @columnfractions 0.15 0.85
...
...
documentation/manuals/firmware/irq_controller_regs.tex
View file @
f61a80f5
...
@@ -15,13 +15,7 @@ REG @tab
...
@@ -15,13 +15,7 @@ REG @tab
Interrupt enable mask register
Interrupt enable mask register
@end multitable
@end multitable
@regsection @code
{
multi
_
irq
}
- Multiple interrupt register
@regsection @code
{
multi
_
irq
}
- Multiple interrupt register
Multiple interrupts occurs before irq source is read.
Multiple interrupts occurs before irq source is read.@*Write '1' to clear a bit.@*@*Bit 0: DMA done.@*Bit 1: DMA error.@*Bit 2: Trigger.@*Bit 3: Acquisition end.
Write '1' to clear a bit.
Bit 0: DMA done.
Bit 1: DMA error.
Bit 2: Trigger.
Bit 3: Acquisition end.
@multitable @columnfractions .10 .10 .15 .10 .55
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
31...0
}
@item @code
{
31...0
}
...
@@ -30,17 +24,8 @@ Bit 3: Acquisition end.
...
@@ -30,17 +24,8 @@ Bit 3: Acquisition end.
@tab @code
{
X
}
@tab
@tab @code
{
X
}
@tab
Multiple interrupt
Multiple interrupt
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code
{
src
}
- Interrupt sources register
@regsection @code
{
src
}
- Interrupt sources register
Indicates the interrupt source.
Indicates the interrupt source.@*Write '1' to clear a bit.@*@*Bit 0: DMA done.@*Bit 1: DMA error.@*Bit 2: Trigger.@*Bit 3: Acquisition end.
Write '1' to clear a bit.
Bit 0: DMA done.
Bit 1: DMA error.
Bit 2: Trigger.
Bit 3: Acquisition end.
@multitable @columnfractions .10 .10 .15 .10 .55
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
31...0
}
@item @code
{
31...0
}
...
@@ -49,24 +34,13 @@ Bit 3: Acquisition end.
...
@@ -49,24 +34,13 @@ Bit 3: Acquisition end.
@tab @code
{
X
}
@tab
@tab @code
{
X
}
@tab
Interrupt sources
Interrupt sources
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
@regsection @code
{
en
_
mask
}
- Interrupt enable mask register
@regsection @code
{
en
_
mask
}
- Interrupt enable mask register
Bit mask to independently enable interrupt sources.
Bit mask to independently enable interrupt sources.@*@*Bit 0: DMA done.@*Bit 1: DMA error.@*Bit 2: Trigger.@*Bit 3: Acquisition end.
Bit 0: DMA done.
Bit 1: DMA error.
Bit 2: Trigger.
Bit 3: Acquisition end.
@multitable @columnfractions .10 .10 .15 .10 .55
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code
{
31...0
}
@item @code
{
31...0
}
@tab R/W @tab
@tab R/W @tab
@code
{
EN
_
MASK
}
@code
{
EN
_
MASK
}
@tab @code
{
X
}
@tab
@tab @code
{
0
}
@tab
Interrupt enable mask
Interrupt enable mask
@end multitable
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@end multitable
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @
f61a80f5
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created :
Fri May 3 10:49:1
8 2013
-- Created :
Tue Jul 23 14:30:3
8 2013
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
...
...
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @
f61a80f5
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created :
Fri May 3 10:49:1
8 2013
* Created :
Tue Jul 23 14:30:3
8 2013
* Standard : ANSI C
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
...
...
hdl/spec/rtl/carrier_csr.vhd
View file @
f61a80f5
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Tue
May 7 14:56:42
2013
-- Created : Tue
Jul 23 14:34:24
2013
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
...
hdl/spec/rtl/irq_controller_regs.vhd
View file @
f61a80f5
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ../rtl/irq_controller_regs.vhd
-- File : ../rtl/irq_controller_regs.vhd
-- Author : auto-generated by wbgen2 from irq_controller_regs.wb
-- Author : auto-generated by wbgen2 from irq_controller_regs.wb
-- Created : Tue
May 7 14:57:57
2013
-- Created : Tue
Jul 23 14:34:24
2013
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
...
...
hdl/spec/wb_gen/carrier_csr.h
View file @
f61a80f5
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
* File : carrier_csr.h
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Tue
May 7 14:56:42
2013
* Created : Tue
Jul 23 14:34:24
2013
* Standard : ANSI C
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
...
hdl/spec/wb_gen/irq_controller_regs.h
View file @
f61a80f5
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
* File : irq_controller_regs.h
* File : irq_controller_regs.h
* Author : auto-generated by wbgen2 from irq_controller_regs.wb
* Author : auto-generated by wbgen2 from irq_controller_regs.wb
* Created : Tue
May 7 14:57:57
2013
* Created : Tue
Jul 23 14:34:24
2013
* Standard : ANSI C
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment
