-
mcattin authored
Bug fix in pre/post trigger counters, was counting even if no valid data out of sync fifo. Clear of WB cyc when FSm is IDLE git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@55 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
1d3e6836
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
_xmsgs | ||
iseconfig | ||
ddr3_ctrl_summary.html | ||
spec_fmc_adc_100Ms.gise | ||
spec_fmc_adc_100Ms.xise | ||
spec_top_summary.html |