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FMC ADC 100M 14b 4cha - Software
Commit 5c8560e1 authored by Federico Vaga's avatar Federico Vaga
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Update to new gateware 4.0

parents a554f0f6 c1d5a8ac
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kernel/fa-core.c
View file @ 5c8560e1
......@@ -29,6 +29,9 @@ MODULE_PARM_DESC(show_sdb, "Print a dump of the gateware's SDB tree.");
static int fa_enable_test_data = 0;
module_param_named(enable_test_data, fa_enable_test_data, int, 0444);
static int fa_internal_trig_test = 0;
module_param_named(internal_trig_test, fa_internal_trig_test, int, 0444);
static const int zfad_hw_range[] = {
[ZFA_RANGE_10V] = 0x45,
[ZFA_RANGE_1V] = 0x11,
......@@ -129,6 +132,20 @@ void zfad_reset_offset(struct fa_dev *fa)
zfad_apply_user_offset(fa, &fa->zdev->cset->chan[i], 0);
}
/*
* zfad_init_saturation
* @fa: the fmc-adc descriptor
*
* Initialize all saturation registers to the maximum value
*/
void zfad_init_saturation(struct fa_dev *fa)
{
int idx, i;
for (i = 0, idx = ZFA_CH1_SAT; i < FA_NCHAN; ++i, idx += ZFA_CHx_MULT)
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[idx], 0x7fff);
}
/*
* zfad_set_range
* @fa: the fmc-adc descriptor
......@@ -339,6 +356,10 @@ static int __fa_init(struct fa_dev *fa)
/* Set test data register */
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFA_CTL_TEST_DATA_EN],
fa_enable_test_data);
/* Set internal trigger test mode */
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_TEST_EN],
fa_internal_trig_test);
/* Set to single shot mode by default */
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_SHOTS_NB], 1);
if (zdev->cset->ti->cset->trig == &zfat_type) {
......@@ -359,6 +380,9 @@ static int __fa_init(struct fa_dev *fa)
zfad_reset_offset(fa);
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFA_CTL_DAC_CLR_N], 1);
/* Initialize channel saturation values */
zfad_init_saturation(fa);
/* Set UTC seconds from the kernel seconds */
fa_writel(fa, fa->fa_utc_base, &zfad_regs[ZFA_UTC_SECONDS],
get_seconds());
......
kernel/fa-irq.c
View file @ 5c8560e1
......@@ -171,7 +171,7 @@ void zfad_dma_done(struct zio_cset *cset)
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_HW_EN],
(ti->flags & ZIO_STATUS ? 0 : 1));
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SW_EN],
ti->zattr_set.ext_zattr[5].value);
ti->zattr_set.ext_zattr[6].value);
} else {
dev_dbg(&fa->fmc->dev, "Software acquisition over\n");
fa_writel(fa, fa->fa_adc_csr_base, &zfad_regs[ZFAT_CFG_SW_EN],
......@@ -212,24 +212,28 @@ void zfat_irq_acq_end(struct zio_cset *cset)
struct fa_dev *fa = cset->zdev->priv_d;
dev_dbg(&fa->fmc->dev, "Acquisition done\n");
/*FIXME: because the driver doesn't listen anymore trig-event
/*
* because the driver doesn't listen anymore trig-event
* we agreed that the HW will provide a dedicated register
* to check the real number of shots in order to compare it
* with the requested one.
* This ultimate check is not crucial because the HW implements
* a solid state machine and acq-end can happens only after
* the execution of the n requested shots.
*
* FIXME (v4.0) this work only for multi-shot acquisition
*/
/*
fa->n_fires = fa_readl(fa, fa->fa_adc_csr_base, &zfad_regs[ZFA_NSHOTS...);
if (fa->n_fires != fa->n_shots) {
dev_err(&fa->fmc->dev,
"Expected %i trigger fires, but %i occurs\n",
fa->n_shots, fa->n_fires);
}
*/
/* for the time being let assume n_shots have been executed */
fa->n_fires = fa->n_shots;
if (fa->n_shots > 1) {
fa->n_fires -= fa_readl(fa, fa->fa_adc_csr_base,
&zfad_regs[ZFAT_SHOTS_REM]);
if (fa->n_fires != fa->n_shots) {
dev_err(&fa->fmc->dev,
"Expected %i trigger fires, but %i occurs\n",
fa->n_shots, fa->n_fires);
}
}
}
/*
......
kernel/fa-regtable.c
View file @ 5c8560e1
......@@ -26,7 +26,9 @@ const struct zfa_field_desc zfad_regs[] = {
[ZFAT_CFG_HW_POL] = {0x08, 0x00000002, 1},
[ZFAT_CFG_HW_EN] = {0x08, 0x00000004, 1},
[ZFAT_CFG_SW_EN] = {0x08, 0x00000008, 1},
[ZFAT_CFG_INT_SEL] = {0x08, 0x00000070, 1},
[ZFAT_CFG_INT_SEL] = {0x08, 0x00000030, 1},
[ZFAT_CFG_TEST_EN] = {0x08, 0x00000040, 1},
[ZFAT_CFG_THRES_FILT] = {0x08, 0x0000FF00, 1},
[ZFAT_CFG_THRES] = {0x08, 0xFFFF0000, 1},
/* Delay */
[ZFAT_DLY] = {0x0C, 0xFFFFFFFF, 0},
......@@ -34,40 +36,48 @@ const struct zfa_field_desc zfad_regs[] = {
[ZFAT_SW] = {0x10, 0xFFFFFFFF, 0},
/* Number of shots */
[ZFAT_SHOTS_NB] = {0x14, 0x0000FFFF, 0},
/* Remaining shots counter */
[ZFAT_SHOTS_REM] = {0x18, 0x0000FFFF, 0},
/* Sampling clock frequency */
[ZFAT_SAMPLING_HZ] = {0x20, 0xFFFFFFFF, 0},
/* Sample rate */
[ZFAT_SR_DECI] = {0x1C, 0xFFFFFFFF, 0},
[ZFAT_SR_DECI] = {0x24, 0xFFFFFFFF, 0},
/* Position address */
[ZFAT_POS] = {0x18, 0xFFFFFFFF, 0},
[ZFAT_POS] = {0x1C, 0xFFFFFFFF, 0},
/* Pre-sample */
[ZFAT_PRE] = {0x20, 0xFFFFFFFF, 0},
[ZFAT_PRE] = {0x28, 0xFFFFFFFF, 0},
/* Post-sample */
[ZFAT_POST] = {0x24, 0xFFFFFFFF, 0},
[ZFAT_POST] = {0x2C, 0xFFFFFFFF, 0},
/* Sample counter */
[ZFAT_CNT] = {0x28, 0xFFFFFFFF, 0},
[ZFAT_CNT] = {0x30, 0xFFFFFFFF, 0},
/* Channel 1 */
[ZFA_CH1_CTL_RANGE] = {0x2C, 0x00000077, 1},
[ZFA_CH1_CTL_TERM] = {0x2C, 0x00000008, 1},
[ZFA_CH1_STA] = {0x30, 0x0000FFFF, 0},
[ZFA_CH1_GAIN] = {0x34, 0x0000FFFF, 0},
[ZFA_CH1_OFFSET] = {0x38, 0x0000FFFF, 0},
[ZFA_CH1_CTL_RANGE] = {0x34, 0x00000077, 1},
[ZFA_CH1_CTL_TERM] = {0x34, 0x00000008, 1},
[ZFA_CH1_STA] = {0x38, 0x0000FFFF, 0},
[ZFA_CH1_GAIN] = {0x3C, 0x0000FFFF, 0},
[ZFA_CH1_OFFSET] = {0x40, 0x0000FFFF, 0},
[ZFA_CH1_SAT] = {0x44, 0x00007FFF, 0},
/* Channel 2 */
[ZFA_CH2_CTL_RANGE] = {0x3C, 0x00000077, 1},
[ZFA_CH2_CTL_TERM] = {0x3C, 0x00000008, 1},
[ZFA_CH2_STA] = {0x40, 0x0000FFFF, 0},
[ZFA_CH2_GAIN] = {0x44, 0x0000FFFF, 0},
[ZFA_CH2_OFFSET] = {0x48, 0x0000FFFF, 0},
[ZFA_CH2_CTL_RANGE] = {0x48, 0x00000077, 1},
[ZFA_CH2_CTL_TERM] = {0x48, 0x00000008, 1},
[ZFA_CH2_STA] = {0x4C, 0x0000FFFF, 0},
[ZFA_CH2_GAIN] = {0x50, 0x0000FFFF, 0},
[ZFA_CH2_OFFSET] = {0x54, 0x0000FFFF, 0},
[ZFA_CH2_SAT] = {0x58, 0x00007FFF, 0},
/* Channel 3 */
[ZFA_CH3_CTL_RANGE] = {0x4C, 0x00000077, 1},
[ZFA_CH3_CTL_TERM] = {0x4C, 0x00000008, 1},
[ZFA_CH3_STA] = {0x50, 0x0000FFFF, 0},
[ZFA_CH3_GAIN] = {0x54, 0x0000FFFF, 0},
[ZFA_CH3_OFFSET] = {0x58, 0x0000FFFF, 0},
[ZFA_CH3_CTL_RANGE] = {0x5C, 0x00000077, 1},
[ZFA_CH3_CTL_TERM] = {0x5C, 0x00000008, 1},
[ZFA_CH3_STA] = {0x60, 0x0000FFFF, 0},
[ZFA_CH3_GAIN] = {0x64, 0x0000FFFF, 0},
[ZFA_CH3_OFFSET] = {0x68, 0x0000FFFF, 0},
[ZFA_CH3_SAT] = {0x6C, 0x00007FFF, 0},
/* Channel 4 */
[ZFA_CH4_CTL_RANGE] = {0x5C, 0x00000077, 1},
[ZFA_CH4_CTL_TERM] = {0x5C, 0x00000008, 1},
[ZFA_CH4_STA] = {0x60, 0x0000FFFF, 0},
[ZFA_CH4_GAIN] = {0x64, 0x0000FFFF, 0},
[ZFA_CH4_OFFSET] = {0x68, 0x0000FFFF, 0},
[ZFA_CH4_CTL_RANGE] = {0x70, 0x00000077, 1},
[ZFA_CH4_CTL_TERM] = {0x70, 0x00000008, 1},
[ZFA_CH4_STA] = {0x74, 0x0000FFFF, 0},
[ZFA_CH4_GAIN] = {0x78, 0x0000FFFF, 0},
[ZFA_CH4_OFFSET] = {0x7C, 0x0000FFFF, 0},
[ZFA_CH4_SAT] = {0x80, 0x00007FFF, 0},
/* IRQ */
[ZFA_IRQ_ADC_DISABLE_MASK] = {0x00, 0x00000003, 0},
[ZFA_IRQ_ADC_ENABLE_MASK] = {0x04, 0x00000003, 0},
......
kernel/fa-zio-drv.c
View file @ 5c8560e1
......@@ -56,6 +56,11 @@ static struct zio_attribute zfad_cset_ext_zattr[] = {
ZIO_ATTR_EXT("ch2-vref", ZIO_RW_PERM, ZFA_CH3_CTL_RANGE, 0),
ZIO_ATTR_EXT("ch3-vref", ZIO_RW_PERM, ZFA_CH4_CTL_RANGE, 0),
ZIO_ATTR_EXT("ch0-saturation", ZIO_RW_PERM, ZFA_CH1_SAT, 0),
ZIO_ATTR_EXT("ch1-saturation", ZIO_RW_PERM, ZFA_CH2_SAT, 0),
ZIO_ATTR_EXT("ch2-saturation", ZIO_RW_PERM, ZFA_CH3_SAT, 0),
ZIO_ATTR_EXT("ch3-saturation", ZIO_RW_PERM, ZFA_CH4_SAT, 0),
ZIO_ATTR_EXT("ch0-50ohm-term", ZIO_RW_PERM, ZFA_CH1_CTL_TERM, 0),
ZIO_ATTR_EXT("ch1-50ohm-term", ZIO_RW_PERM, ZFA_CH2_CTL_TERM, 0),
ZIO_ATTR_EXT("ch2-50ohm-term", ZIO_RW_PERM, ZFA_CH3_CTL_TERM, 0),
......@@ -110,7 +115,7 @@ static struct zio_attribute zfad_cset_ext_zattr[] = {
/* Reset all channel offset */
ZIO_PARAM_EXT("rst-ch-offset", ZIO_WO_PERM, ZFA_CTL_DAC_CLR_N, 1),
ZIO_PARAM_EXT("sample-frequency", ZIO_RO_PERM, ZFAT_SAMPLING_HZ, 0),
};
#if 0 /* FIXME Unused until TLV control will be available */
......@@ -129,6 +134,9 @@ static ZIO_ATTR_DEFINE_STD(ZIO_DEV, zfad_chan_std_zattr) = {
#endif
static struct zio_attribute zfad_chan_ext_zattr[] = {
#if 0 /* FIXME Unused until TLV control will be available */
ZIO_ATTR("saturation", ZIO_RW_PERM, ZFA_CHx_SAT, 0),
#endif
/*ZIO_ATTR(zdev, "50ohm-termination", ZIO_RW_PERM, ZFA_CHx_CTL_TERM, 0x11),*/
ZIO_PARAM_EXT("current-value", ZIO_RO_PERM, ZFA_CHx_STA, 0),
};
......@@ -284,6 +292,7 @@ static int zfad_info_get(struct device *dev, struct zio_attribute *zattr,
*usr_val = fa_read_temp(fa, 0);
*usr_val = (*usr_val * 1000 + 8) / 16;
return 0;
case ZFA_CHx_SAT:
case ZFA_CHx_CTL_TERM:
case ZFA_CHx_CTL_RANGE:
reg_index = zfad_get_chx_index(zattr->id, to_zio_chan(dev));
......
kernel/fa-zio-trg.c
View file @ 5c8560e1
......@@ -64,6 +64,9 @@ static struct zio_attribute zfat_ext_zattr[] = {
*/
[ZFAT_ATTR_DELAY] = ZIO_ATTR_EXT("delay", ZIO_RW_PERM, ZFAT_DLY, 0),
/* setup the maximum glith length to filter */
ZIO_ATTR_EXT("int-threshold-filter", ZIO_RW_PERM, ZFAT_CFG_THRES_FILT,
0),
/* Software Trigger */
/* Enable (1) or disable (0) software trigger */
[ZFAT_ATTR_SW_EN] = ZIO_PARAM_EXT("sw-trg-enable", ZIO_RW_PERM, ZFAT_CFG_SW_EN, 0),
......
kernel/fmc-adc.h
View file @ 5c8560e1
......@@ -134,14 +134,20 @@ enum zfadc_dregs_enum {
ZFAT_CFG_SW_EN,
ZFAT_CFG_INT_SEL,
ZFAT_CFG_THRES,
ZFAT_CFG_TEST_EN,
ZFAT_CFG_THRES_FILT,
/* Delay*/
ZFAT_DLY,
/* Software */
ZFAT_SW,
/* Number of shots */
ZFAT_SHOTS_NB,
/* Remaining shots counter */
ZFAT_SHOTS_REM,
/* Sample rate */
ZFAT_SR_DECI,
/* Sampling clock frequency */
ZFAT_SAMPLING_HZ,
/* Position address */
ZFAT_POS,
/* Pre-sample */
......@@ -157,24 +163,28 @@ enum zfadc_dregs_enum {
ZFA_CH1_STA,
ZFA_CH1_GAIN,
ZFA_CH1_OFFSET,
ZFA_CH1_SAT,
/* Channel 2 */
ZFA_CH2_CTL_RANGE,
ZFA_CH2_CTL_TERM,
ZFA_CH2_STA,
ZFA_CH2_GAIN,
ZFA_CH2_OFFSET,
ZFA_CH2_SAT,
/* Channel 3 */
ZFA_CH3_CTL_RANGE,
ZFA_CH3_CTL_TERM,
ZFA_CH3_STA,
ZFA_CH3_GAIN,
ZFA_CH3_OFFSET,
ZFA_CH3_SAT,
/* Channel 4 */
ZFA_CH4_CTL_RANGE,
ZFA_CH4_CTL_TERM,
ZFA_CH4_STA,
ZFA_CH4_GAIN,
ZFA_CH4_OFFSET,
ZFA_CH4_SAT,
/*
* CHx__ are specifc ids used by some internal arithmetic
* Be carefull: the arithmetic expects
......@@ -187,6 +197,7 @@ enum zfadc_dregs_enum {
ZFA_CHx_STA,
ZFA_CHx_GAIN,
ZFA_CHx_OFFSET,
ZFA_CHx_SAT,
/* end:declaration block requiring some order */
/* two wishbone core for IRQ: VIC, ADC */
ZFA_IRQ_ADC_DISABLE_MASK,
......@@ -297,7 +308,7 @@ enum fa_sw_param_id {
* ZFA_CHx_MULT : the trick which requires channel regs id grouped and ordered
* address offset between two registers of the same type on consecutive channel
*/
#define ZFA_CHx_MULT 5
#define ZFA_CHx_MULT 6
/* ADC DDR memory */
#define FA_MAX_ACQ_BYTE 0x10000000 /* 256MB */
......
lib/config-zio.c
View file @ 5c8560e1
......@@ -202,6 +202,14 @@ static int fmcadc_zio_config_trg(struct __fmcadc_dev_zio *fa,
return fa_zio_sysfs_get(fa, "cset0/trigger/delay",
value);
break;
case FMCADC_CONF_TRG_THRESHOLD_FILTER:
if (direction)
return fa_zio_sysfs_set(fa, "cset0/trigger/int-threshold-filter",
value);
else
return fa_zio_sysfs_get(fa, "cset0/trigger/int-threshold-filter",
value);
break;
default:
errno = FMCADC_ENOCAP;
return -1;
......@@ -293,6 +301,13 @@ static int fmcadc_zio_config_chn(struct __fmcadc_dev_zio *fa, unsigned int ch,
else
return fa_zio_sysfs_get(fa, path, value);
break;
case FMCADC_CONF_CHN_SATURATION:
sprintf(path, "cset%d/ch%d-saturation", fa->cset, ch);
if (direction)
return fa_zio_sysfs_set(fa, path, value);
else
return fa_zio_sysfs_get(fa, path, value);
break;
default:
errno = FMCADC_ENOCAP;
return -1;
......
lib/fmcadc-lib.h
View file @ 5c8560e1
......@@ -58,6 +58,7 @@ enum fmcadc_configuration_trigger {
FMCADC_CONF_TRG_THRESHOLD,
FMCADC_CONF_TRG_POLARITY,
FMCADC_CONF_TRG_DELAY,
FMCADC_CONF_TRG_THRESHOLD_FILTER,
__FMCADC_CONF_TRG_ATTRIBUTE_LAST_INDEX,
};
enum fmcadc_configuration_acquisition {
......@@ -73,6 +74,7 @@ enum fmcadc_configuration_channel {
FMCADC_CONF_CHN_RANGE = 0,
FMCADC_CONF_CHN_TERMINATION,
FMCADC_CONF_CHN_OFFSET,
FMCADC_CONF_CHN_SATURATION,
__FMCADC_CONF_CHN_ATTRIBUTE_LAST_INDEX,
};
enum fmcadc_board_status {
......
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