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FMC ADC 100M 14b 4cha - Software
Commit 6842d676 authored by Federico Vaga's avatar Federico Vaga
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adc: simplify zfa_common_{info_get|conf_set} functions 

Signed-off-by: 's avatarFederico Vaga <federico.vaga@gmail.com>
parent 27bb1c03
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Showing with 72 additions and 74 deletions
kernel/fa-zio-drv.c
View file @ 6842d676
......@@ -226,14 +226,14 @@ int zfad_fsm_command(struct fa_dev *fa, uint32_t command)
/* If START, check if we can start */
if (command == ZFA_START) {
/* Verify that SerDes PLL is lockes */
zfa_common_info_get(fa, &zfad_regs[ZFA_STA_SERDES_PLL], &val);
zfa_common_info_get(fa, ZFA_STA_SERDES_PLL, &val);
if (!val) {
dev_err(fa->fmc->hwdev,
"Cannot start acquisition: SerDes PLL not locked\n");
return -EBUSY;
}
/* Verify that SerDes is synched */
zfa_common_info_get(fa, &zfad_regs[ZFA_STA_SERDES_SYNCED], &val);
zfa_common_info_get(fa, ZFA_STA_SERDES_SYNCED, &val);
if (!val) {
dev_err(fa->fmc->hwdev,
"Cannot start acquisition: SerDes not synchronized\n");
......@@ -253,15 +253,15 @@ int zfad_fsm_command(struct fa_dev *fa, uint32_t command)
zio_trigger_abort(fa->zdev->cset);
if (command == ZFA_START) {
dev_dbg(fa->fmc->hwdev, "Enable interrupts\n");
zfa_common_conf_set(fa, &zfad_regs[ZFA_IRQ_MASK], ZFAT_ALL);
zfa_common_conf_set(fa, ZFA_IRQ_MASK, ZFAT_ALL);
}
return 0;
}
static void zfad_reset_offset(struct fa_dev *fa)
{
zfa_common_conf_set(fa, &zfad_regs[ZFA_CTL_DAC_CLR_N], 0);
zfa_common_conf_set(fa, ZFA_CTL_DAC_CLR_N, 0);
udelay(20);
zfa_common_conf_set(fa, &zfad_regs[ZFA_CTL_DAC_CLR_N], 1);
zfa_common_conf_set(fa, ZFA_CTL_DAC_CLR_N, 1);
/*
* FIXME update the value with the default value for the selected range
......@@ -305,12 +305,12 @@ static int zfad_calibration(struct fa_dev *fa, struct zio_channel *chan,
i = zfad_get_chx_index(ZFA_CHx_OFFSET, chan);
cal_val = fa->adc_cal_data[range].offset[chan->index];
dev_dbg(&chan->head.dev, "offset calibration value 0x%x\n", cal_val);
zfa_common_conf_set(fa, &zfad_regs[i], cal_val);
zfa_common_conf_set(fa, i, cal_val);
/* Apply the ADC calibration value for the gain */
i = zfad_get_chx_index(ZFA_CHx_GAIN, chan);
cal_val = fa->adc_cal_data[range].gain[chan->index];
dev_dbg(&chan->head.dev, "gain calibration value 0x%x\n", cal_val);
zfa_common_conf_set(fa, &zfad_regs[i], cal_val);
zfa_common_conf_set(fa, i, cal_val);
return 0;
}
......@@ -357,7 +357,7 @@ static int zfad_conf_set(struct device *dev, struct zio_attribute *zattr,
{
struct fa_dev *fa = get_zfadc(dev);
const struct zio_field_desc *reg;
int i, err;
int i, err, reg_index;
i = fa->zdev->cset->n_chan -1 ; /* -1 because of interleaved channel */
switch (zattr->id) {
......@@ -412,7 +412,7 @@ static int zfad_conf_set(struct device *dev, struct zio_attribute *zattr,
return err;
case ZFA_CHx_STA:
i = zfad_get_chx_index(zattr->id, to_zio_chan(dev));
reg = &zfad_regs[i];
reg_index = i;
break;
case ZFA_CTL_FMS_CMD:
err = zfad_fsm_command(fa, usr_val);
......@@ -420,9 +420,10 @@ static int zfad_conf_set(struct device *dev, struct zio_attribute *zattr,
return err;
default:
reg = &zfad_regs[zattr->id];
reg_index = zattr->id;
}
return zfa_common_conf_set(fa, reg, usr_val);
return zfa_common_conf_set(fa, reg_index, usr_val);
}
/* get the value of a FMC-ADC register */
static int zfad_info_get(struct device *dev, struct zio_attribute *zattr,
......@@ -430,7 +431,7 @@ static int zfad_info_get(struct device *dev, struct zio_attribute *zattr,
{
const struct zio_field_desc *reg;
struct fa_dev *fa = get_zfadc(dev);
int i;
int i, reg_index;
switch (zattr->id) {
/* FIXME temporary until TLV control */
......@@ -449,14 +450,13 @@ static int zfad_info_get(struct device *dev, struct zio_attribute *zattr,
return 0;
case ZFA_CHx_CTL_RANGE:
case ZFA_CHx_STA:
i = zfad_get_chx_index(zattr->id, to_zio_chan(dev));
reg = &zfad_regs[i];
reg_index = zfad_get_chx_index(zattr->id, to_zio_chan(dev));
break;
default:
reg = &zfad_regs[zattr->id];
reg_index = zattr->id;
}
zfa_common_info_get(fa, reg, usr_val);
zfa_common_info_get(fa, reg_index, usr_val);
return 0;
}
......@@ -490,7 +490,7 @@ static int zfad_input_cset(struct zio_cset *cset)
return err;
/* Start DMA transefer */
zfa_common_conf_set(fa, &zfad_regs[ZFA_DMA_CTL_START], 1);
zfa_common_conf_set(fa, ZFA_DMA_CTL_START, 1);
dev_dbg(&cset->head.dev, "Start DMA transfer\n");
return -EAGAIN; /* data_done on DMA_DONE interrupt */
......@@ -518,7 +518,6 @@ static int zfad_zio_probe(struct zio_device *zdev)
static int zfad_init_cset(struct zio_cset *cset)
{
const struct zio_field_desc *reg;
struct fa_dev *fa = cset->zdev->priv_d;
int i;
......@@ -527,36 +526,36 @@ static int zfad_init_cset(struct zio_cset *cset)
zfa_common_conf_set(fa, &zfad_regs[ZFA_CTL_FMS_CMD], ZFA_STOP);
/* Initialize channels gain to 1 and range to 1V */
for (i = 0; i < 4; ++i) {
reg = &zfad_regs[ZFA_CH1_GAIN + (i * ZFA_CHx_MULT)];
zfa_common_conf_set(fa, reg, 0x8000);
reg = &zfad_regs[ZFA_CH1_CTL_RANGE + (i * ZFA_CHx_MULT)];
zfa_common_conf_set(fa, reg, 0x11);
zfa_common_conf_set(fa, ZFA_CH1_GAIN + (i * ZFA_CHx_MULT),
0x8000);
zfa_common_conf_set(fa, ZFA_CH1_CTL_RANGE + (i * ZFA_CHx_MULT),
0x0011);
}
/* Enable mezzanine clock */
zfa_common_conf_set(fa, &zfad_regs[ZFA_CTL_CLK_EN], 1);
zfa_common_conf_set(fa, ZFA_CTL_CLK_EN, 1);
/* Reset channel offset to mid-scale */
zfad_reset_offset(fa);
/* Set DMA to transfer data from device to host */
zfa_common_conf_set(fa, &zfad_regs[ZFA_DMA_BR_DIR], 0);
zfa_common_conf_set(fa, ZFA_DMA_BR_DIR, 0);
/* Set decimation to minimum */
zfa_common_conf_set(fa, &zfad_regs[ZFAT_SR_DECI], 1);
zfa_common_conf_set(fa, ZFAT_SR_DECI, 1);
/* Set test data register */
zfa_common_conf_set(fa, &zfad_regs[ZFA_CTL_TEST_DATA_EN],
zfa_common_conf_set(fa, ZFA_CTL_TEST_DATA_EN,
enable_test_data);
/* Trigger registers */
/* Set to single shot mode by default */
zfa_common_conf_set(fa, &zfad_regs[ZFAT_SHOTS_NB], 1);
zfa_common_conf_set(fa, ZFAT_SHOTS_NB, 1);
cset->ti->zattr_set.std_zattr[ZIO_ATTR_TRIG_REENABLE].value = 0;
/* Disable Software trigger*/
zfa_common_conf_set(fa, &zfad_regs[ZFAT_CFG_SW_EN], 0);
zfa_common_conf_set(fa, ZFAT_CFG_SW_EN, 0);
/* Enable Hardware trigger*/
zfa_common_conf_set(fa, &zfad_regs[ZFAT_CFG_HW_EN], 1);
zfa_common_conf_set(fa, ZFAT_CFG_HW_EN, 1);
/* Select external trigger (index 0) */
zfa_common_conf_set(fa, &zfad_regs[ZFAT_CFG_HW_SEL], 1);
zfa_common_conf_set(fa, ZFAT_CFG_HW_SEL, 1);
cset->ti->zattr_set.ext_zattr[0].value = 1;
/* Set UTC seconds from the kernel seconds */
zfa_common_conf_set(fa, &zfad_regs[ZFA_UTC_SECONDS], get_seconds());
zfa_common_conf_set(fa, ZFA_UTC_SECONDS, get_seconds());
return 0;
}
......@@ -656,13 +655,13 @@ int fa_zio_init(struct fa_dev *fa)
return -ENODEV;
}
/* Verify that system PLL is locked (1 is calibrated) */
zfa_common_info_get(fa, &zfad_regs[ZFA_CAR_SYS_PLL], &val);
zfa_common_info_get(fa, ZFA_CAR_SYS_PLL, &val);
if (!val) {
dev_err(hwdev, "System PLL not locked\n");
return -ENODEV;
}
/* Verify that DDR3 calibration is done (1 is calibrated) */
zfa_common_info_get(fa, &zfad_regs[ZFA_CAR_DDR_CAL], &val);
zfa_common_info_get(fa, ZFA_CAR_DDR_CAL, &val);
if (!val) {
dev_err(hwdev, "DDR3 Calibration not done\n");
return -ENODEV;
......
kernel/fa-zio-trg.c
View file @ 6842d676
......@@ -41,9 +41,9 @@ struct zfat_block {
/* zio trigger attributes */
static ZIO_ATTR_DEFINE_STD(ZIO_TRG, zfat_std_zattr) = {
/* Number of shots */
ZIO_ATTR(trig, ZIO_ATTR_TRIG_REENABLE, S_IRUGO | S_IWUGO, ZFAT_SHOTS_NB, 0),
ZIO_ATTR(trig, ZIO_ATTR_TRIG_PRE_SAMP, S_IRUGO | S_IWUGO, ZFAT_PRE, 0),
ZIO_ATTR(trig, ZIO_ATTR_TRIG_POST_SAMP, S_IRUGO | S_IWUGO, ZFAT_POST, 0),
ZIO_ATTR(trig, ZIO_ATTR_TRIG_REENABLE, ZIO_RW_PERM, ZFAT_SHOTS_NB, 0),
ZIO_ATTR(trig, ZIO_ATTR_TRIG_PRE_SAMP, ZIO_RW_PERM, ZFAT_PRE, 0),
ZIO_ATTR(trig, ZIO_ATTR_TRIG_POST_SAMP, ZIO_RW_PERM, ZFAT_POST, 0),
};
static struct zio_attribute zfat_ext_zattr[] = {
/* Config register */
......@@ -51,35 +51,35 @@ static struct zio_attribute zfat_ext_zattr[] = {
* 0: internal (data threshold)
* 1: external (front panel trigger input)
*/
ZIO_ATTR_EXT("external", S_IRUGO | S_IWUGO, ZFAT_CFG_HW_SEL, 0),
ZIO_ATTR_EXT("external", ZIO_RW_PERM, ZFAT_CFG_HW_SEL, 0),
/*
* Internal Hardware trigger polarity
* 0: positive edge/slope
* 1: negative edge/slope
*/
ZIO_ATTR_EXT("polarity", S_IRUGO | S_IWUGO, ZFAT_CFG_HW_POL, 0),
ZIO_ATTR_EXT("polarity", ZIO_RW_PERM, ZFAT_CFG_HW_POL, 0),
/*
* Channel selection for internal trigger
* 0: channel 1, 1: channel 2, 2: channel 3, 3: channel 4
*/
ZIO_ATTR_EXT("int-channel", S_IRUGO | S_IWUGO, ZFAT_CFG_INT_SEL, 0),
ZIO_ATTR_EXT("int-channel", ZIO_RW_PERM, ZFAT_CFG_INT_SEL, 0),
/* Internal trigger threshold value is 2 complement format */
ZIO_ATTR_EXT("int-threshold", S_IRUGO | S_IWUGO, ZFAT_CFG_THRES, 0),
ZIO_ATTR_EXT("int-threshold", ZIO_RW_PERM, ZFAT_CFG_THRES, 0),
/*
* Delay to apply on the trigger in sampling clock period. The default
* clock frequency is 100MHz (period = 10ns)
*/
ZIO_ATTR_EXT("delay", S_IRUGO | S_IWUGO, ZFAT_DLY, 0),
ZIO_ATTR_EXT("delay", ZIO_RW_PERM, ZFAT_DLY, 0),
/* Software Trigger */
/* Enable (1) or disable (0) software trigger */
ZIO_PARAM_EXT("sw-trg-enable", S_IRUGO | S_IWUGO, ZFAT_CFG_SW_EN, 0),
ZIO_PARAM_EXT("sw-trg-enable", ZIO_RW_PERM, ZFAT_CFG_SW_EN, 0),
ZIO_PARAM_EXT("sw-trg-fire", S_IWUGO, ZFAT_SW, 0),
/* last trigger time stamp */
ZIO_PARAM_EXT("tstamp-trg-lst-s", S_IRUGO, ZFA_UTC_TRIG_SECONDS, 0),
ZIO_PARAM_EXT("tstamp-trg-lst-t", S_IRUGO, ZFA_UTC_TRIG_COARSE, 0),
ZIO_PARAM_EXT("tstamp-trg-lst-b", S_IRUGO, ZFA_UTC_TRIG_FINE, 0),
ZIO_PARAM_EXT("tstamp-trg-lst-s", ZIO_RO_PERM, ZFA_UTC_TRIG_SECONDS, 0),
ZIO_PARAM_EXT("tstamp-trg-lst-t", ZIO_RO_PERM, ZFA_UTC_TRIG_COARSE, 0),
ZIO_PARAM_EXT("tstamp-trg-lst-b", ZIO_RO_PERM, ZFA_UTC_TRIG_FINE, 0),
};
static int zfat_overflow_detection(struct zio_ti *ti, unsigned int addr,
......@@ -192,15 +192,15 @@ static void zfat_start_next_dma(struct zio_ti *ti)
* of the trigger. Software trigger depends on the previous
* status taken form zio attributes (index 5 of extended one)
*/
zfa_common_conf_set(fa, &zfad_regs[ZFAT_CFG_HW_EN],
zfa_common_conf_set(fa, ZFAT_CFG_HW_EN,
(ti->flags & ZIO_STATUS ? 0 : 1));
zfa_common_conf_set(fa, &zfad_regs[ZFAT_CFG_SW_EN],
zfa_common_conf_set(fa, ZFAT_CFG_SW_EN,
ti->zattr_set.ext_zattr[5].value);
/* Automatic start next acquisition */
if (enable_auto_start) {
dev_dbg(&ti->head.dev, "Automatic start\n");
zfad_fsm_command(fa, ZFA_START);
zfa_common_conf_set(fa, &zfad_regs[ZFA_CTL_FMS_CMD],
zfa_common_conf_set(fa, ZFA_CTL_FMS_CMD,
ZFA_START);
}
return;
......@@ -237,13 +237,13 @@ static void zfat_get_irq_status(struct zfat_instance *zfat,
struct fa_dev *fa = zfat->ti.cset->zdev->priv_d;
/* Get current interrupts status */
zfa_common_info_get(fa, &zfad_regs[ZFA_IRQ_SRC], irq_status);
zfa_common_info_get(fa, &zfad_regs[ZFA_IRQ_MULTI], irq_multi);
zfa_common_info_get(fa, ZFA_IRQ_SRC, irq_status);
zfa_common_info_get(fa, ZFA_IRQ_MULTI, irq_multi);
dev_dbg(&zfat->ti.head.dev, "irq status = 0x%x multi = 0x%x\n",
*irq_status, *irq_multi);
/* Clear current interrupts status */
zfa_common_conf_set(fa, &zfad_regs[ZFA_IRQ_SRC], *irq_status);
zfa_common_conf_set(fa, &zfad_regs[ZFA_IRQ_MULTI], *irq_multi);
zfa_common_conf_set(fa, ZFA_IRQ_SRC, *irq_status);
zfa_common_conf_set(fa, ZFA_IRQ_MULTI, *irq_multi);
/* ack the irq */
zfat->fa->fmc->op->irq_ack(zfat->fa->fmc);
}
......@@ -277,12 +277,9 @@ static void zfat_irq_dma_done(struct fmc_device *fmc,
/* Get the last trigger time-stamp from device */
static void zfat_get_time_stamp(struct fa_dev *fa, struct zio_timestamp *ts)
{
zfa_common_info_get(fa, &zfad_regs[ZFA_UTC_TRIG_SECONDS],
(uint32_t *)&ts->secs);
zfa_common_info_get(fa, &zfad_regs[ZFA_UTC_TRIG_COARSE],
(uint32_t *)&ts->ticks);
zfa_common_info_get(fa, &zfad_regs[ZFA_UTC_TRIG_FINE],
(uint32_t *)&ts->bins);
zfa_common_info_get(fa, ZFA_UTC_TRIG_SECONDS, (uint32_t *)&ts->secs);
zfa_common_info_get(fa, ZFA_UTC_TRIG_COARSE, (uint32_t *)&ts->ticks);
zfa_common_info_get(fa, ZFA_UTC_TRIG_FINE, (uint32_t *)&ts->bins);
}
/*
* Trigger fires, but ZIO allow only one trigger at time, and the ADC in
......@@ -363,14 +360,14 @@ static void zfat_irq_acq_end(struct zfat_instance *zfat)
* All programmed triggers fire, so the acquisition is ended.
* If the state machine is _idle_ we can start the DMA transfer.
*/
zfa_common_info_get(fa, &zfad_regs[ZFA_STA_FSM],&val);
zfa_common_info_get(fa, ZFA_STA_FSM, &val);
if (val == ZFA_STATE_IDLE) {
/*
* Disable all triggers to prevent fires between
* different DMA transfers required for multi-shots
*/
zfa_common_conf_set(fa, &zfad_regs[ZFAT_CFG_HW_EN], 0);
zfa_common_conf_set(fa, &zfad_regs[ZFAT_CFG_SW_EN], 0);
zfa_common_conf_set(fa, ZFAT_CFG_HW_EN, 0);
zfa_common_conf_set(fa, ZFAT_CFG_SW_EN, 0);
dev_dbg(&zfat->ti.head.dev, "Start DMA from device\n");
zio_fire_trigger(&zfat->ti);
} else {
......@@ -471,7 +468,7 @@ static void zfat_destroy(struct zio_ti *ti)
struct zfat_instance *zfat = to_zfat_instance(ti);
/* Disable all interrupt */
zfa_common_conf_set(fa, &zfad_regs[ZFA_IRQ_MASK], ZFAT_NONE);
zfa_common_conf_set(fa, ZFA_IRQ_MASK, ZFAT_NONE);
fa->fmc->op->irq_free(fa->fmc);
kfree(zfat);
}
......@@ -485,7 +482,7 @@ static void zfat_change_status(struct zio_ti *ti, unsigned int status)
{
struct fa_dev *fa = ti->cset->zdev->priv_d;
zfa_common_conf_set(fa, &zfad_regs[ZFAT_CFG_HW_EN], !status);
zfa_common_conf_set(fa, ZFAT_CFG_HW_EN, !status);
}
/*
......@@ -526,7 +523,7 @@ static void zfat_abort(struct zio_cset *cset)
* any interrupt
*/
dev_dbg(zfat->fa->fmc->hwdev, "Disable interrupts\n");
zfa_common_conf_set(zfat->fa, &zfad_regs[ZFA_IRQ_MASK], ZFAT_NONE);
zfa_common_conf_set(zfat->fa, ZFA_IRQ_MASK, ZFAT_NONE);
spin_lock_irqsave(&zfat->lock, flags);
list_for_each_entry_safe(zfat_block, node, &zfat->list_block, list) {
bi->b_op->free_block(bi, zfat_block->block);
......
kernel/fmc-adc.h
View file @ 6842d676
......@@ -9,6 +9,7 @@
#define _fa_dev_H_
#include <linux/zio.h>
#include <linux/zio-utils.h>
#include "spec.h"
#define FA_GATEWARE_DEFAULT_NAME "fmc/fmc-adc.bin"
......@@ -221,6 +222,9 @@ enum zfadc_dregs_enum {
ZFA_SW_R_NOADDRES_TEMP,
ZFA_SW_R_NOADDERS_AUTO,
};
/* Registers lists used in fd-zio-drv.c */
extern const struct zio_field_desc zfad_regs[];
/*
* ZFA_CHx_MULT
* address offset between two registers of the same type on consecutive channel
......@@ -287,39 +291,37 @@ static inline struct spec_dev *get_spec(struct device *dev)
}
static inline int zfa_common_conf_set(struct fa_dev *fa,
const struct zio_field_desc *fld,
enum zfadc_dregs_enum index,
uint32_t usr_val)
{
uint32_t cur, val;
if ((usr_val & (~fld->mask))) {
if ((usr_val & (~zfad_regs[index].mask))) {
dev_err(fa->fmc->hwdev, "value 0x%x must fit mask 0x%x\n",
usr_val, fld->mask);
usr_val, zfad_regs[index].mask);
return -EINVAL;
}
/* Read current register*/
cur = fmc_readl(fa->fmc, fld->addr);
val = zio_set_field(fld, cur, usr_val);
cur = fmc_readl(fa->fmc, zfad_regs[index].addr);
val = zio_set_field(&zfad_regs[index], cur, usr_val);
/* FIXME re-write usr_val when possible (zio need a patch) */
/* If the attribute has a valid address */
fmc_writel(fa->fmc, val, fld->addr);
fmc_writel(fa->fmc, val, zfad_regs[index].addr);
return 0;
}
static inline void zfa_common_info_get(struct fa_dev *fa,
const struct zio_field_desc *fld,
enum zfadc_dregs_enum index,
uint32_t *usr_val)
{
uint32_t cur;
/* Read current register*/
cur = fmc_readl(fa->fmc, fld->addr);
cur = fmc_readl(fa->fmc, zfad_regs[index].addr);
/* Return the value */
*usr_val = zio_get_field(fld, cur);
*usr_val = zio_get_field(&zfad_regs[index], cur);
}
extern struct zio_trigger_type zfat_type;
/* Registers lists used in fd-zio-drv.c and fd-zio-trg.c */
extern const struct zio_field_desc zfad_regs[];
/* Functions exported by fa-zio.c */
......
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