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FMC ADC 100M 14b 4cha - Testing
Commit 08568437 authored by Matthieu Cattin's avatar Matthieu Cattin
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register maps: Add register map description string.

parent 2e52b071
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Showing with 55 additions and 55 deletions
test/fmcadc100m14b4cha/python/carrier_csr.py
View file @ 08568437
......@@ -9,7 +9,7 @@
# Control and status registers of the SPEC board
CARRIER_CSR={
CARRIER_CSR=['Carrier control and status registers',{
'CARRIER':[0x00, 'Carrier', {
'PCB_REV':[0, 'PCB revision', 0xF],
'TYPE':[16, 'Carrier type', 0xFFFF]}],
......@@ -26,4 +26,4 @@ CARRIER_CSR={
'LED_GREEN':[0, 'Green LED', 0x1],
'LED_RED':[1, 'Red LED', 0x1],
'DAC_CLR_N':[2, 'VCXO DAC clear (active low)', 0x1]}]
}
}]
test/fmcadc100m14b4cha/python/irq_controller_regs.py
View file @ 08568437
......@@ -9,7 +9,7 @@
# IRQ controller core registers
IRQ_CONTROLLER_REGS={
IRQ_CONTROLLER_REGS=['IRQ controller registers', {
'MULTI_IRQ':[0x00, 'Multiple interrupt', {
'DMA_END':[0, 'End of DMA transfer', 0x1],
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
......@@ -25,4 +25,4 @@ IRQ_CONTROLLER_REGS={
'DMA_ERR':[1, 'Error in DMA transfer', 0x1],
'ACQ_TRG':[2, 'Acquisition triggered', 0x1],
'ACQ_END':[3, 'Acquisition finished', 0x1]}]
}
}]
test/fmcadc100m14b4cha/python/utc_core_regs.py
View file @ 08568437
......@@ -9,7 +9,7 @@
# UTC core registers
UTC_CORE_REGS={
UTC_CORE_REGS=['UTC core registers', {
'SECONDS':[0x00, 'UTC seconds', {}],
'COARSE':[0x04, 'UTC coarse time (8ns resolution)', {}],
'TRIG_TAG_META':[0x08, 'Trigger time-tag metadata', {}],
......@@ -28,4 +28,4 @@ UTC_CORE_REGS={
'ACQ_END_TAG_SECONDS':[0x3C, 'Acquisition end time-tag UTC seconds', {}],
'ACQ_END_TAG_COARSE':[0x40, 'Acquisition end time-tag UTC coarse time', {}],
'ACQ_END_TAG_FINE':[0x44, 'Acquisition end time-tag fine time', {}]
}
}]
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