Add test19, plots the 4 channels with the selected input range.

6632e8f9 · Matthieu Cattin · 45d297db · 6632e8f9
Commit 6632e8f9 authored Dec 12, 2011 by Matthieu Cattin
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test19.py test/fmcadc100m14b4cha/python/test19.py +262 -0

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--- a/test/fmcadc100m14b4cha/python/test19.py
+++ b/test/fmcadc100m14b4cha/python/test19.py
+#!   /usr/bin/env   python
+#    coding: utf8
+
+# Copyright CERN, 2011
+# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
+# Licence: GPL v2 or later.
+# Website: http://www.ohwr.org
+
+import sys
+import rr
+import time
+import os
+from numpy import *
+from pylab import *
+
+from ptsexcept import *
+
+import spec_fmc_adc
+import fmc_adc
+import calibr_box
+from PAGE.Agilent33250A import *
+from PAGE.SineWaveform import *
+
+
+"""
+test17: Plot all channels
+
+Note: Requires test00.py to run first to load the firmware!
+"""
+
+GN4124_CSR = 0x0
+
+USB_DEVICE = "/dev/ttyUSB0"
+RS232_BAUD = 57600
+NB_CHANNELS = 4
+
+AWG_SET_SLEEP = 1
+SSR_SET_SLEEP = 0.05
+BOX_SET_SLEEP = 1
+DAC_SET_SLEEP = 0.1
+
+ACQ_TIMEOUT = 10
+
+MAX_FIRMWARE_RELOAD = 10
+
+PRE_TRIG_SAMPLES = 1000
+POST_TRIG_SAMPLES = 50000
+NB_SHOTS = 1
+
+ACQ_LENGTH = 50000 # in samples
+DMA_LENGTH = 4096 # in bytes
+
+ADC_NBITS = 16 # ADC chip is 14 bits, but shifted to 16 bits in the firmware
+DAC_NBITS = 16
+DAC_FS = 10 # DAC full scale range is 10V
+
+
+def load_firmware(default_directory):
+    print('Load firmware to FPGA')
+    path_fpga_loader = '../../../gnurabbit/user/fpga_loader';
+    path_firmware = '../firmwares/spec_fmcadc100m14b4cha_test.bin';
+
+    firmware_loader = os.path.join(default_directory, path_fpga_loader)
+    bitstream = os.path.join(default_directory, path_firmware)
+    print firmware_loader + ' ' + bitstream
+    os.system( firmware_loader + ' ' + bitstream )
+
+    time.sleep(2);
+
+
+def disconnect_channels(fmc):
+    for i in range(1,NB_CHANNELS+1):
+        fmc.set_ssr(i, 0x00)
+        time.sleep(SSR_SET_SLEEP)
+
+
+def fmc_adc_init(spec, fmc):
+    print('Initialise FMC board.')
+    fmc.__init__(spec)
+    # Reset offset DACs
+    fmc.dc_offset_reset()
+    # Make sure all switches are OFF
+    disconnect_channels(fmc)
+    # Reset offset DACs
+    fmc.dc_offset_reset()
+    # Set trigger
+    fmc.set_soft_trig()
+    # Set acquisition
+    fmc.set_pre_trig_samples(PRE_TRIG_SAMPLES)
+    fmc.set_post_trig_samples(POST_TRIG_SAMPLES)
+    fmc.set_shots(NB_SHOTS)
+    # Print configuration
+    #fmc.print_adc_core_config()
+
+
+def set_awg_freq(gen, sine, freq):
+    sine.frequency = freq
+    gen.play(sine)
+    print('Sine frequency:%3.3fMHz')%(sine.frequency/1E6)
+    time.sleep(AWG_SET_SLEEP)
+
+
+def acquisition_all(fmc, spec_fmc):
+    # Make sure no acquisition is running
+    fmc.stop_acq()
+    #print('Acquisition FSM state : %s') % fmc.get_acq_fsm_state()
+    # Start acquisition
+    fmc.start_acq()
+    time.sleep(0.01)
+    # Trigger
+    fmc.sw_trig()
+    # Wait end of acquisition
+    timeout = 0
+    while('IDLE' != fmc.get_acq_fsm_state()):
+        #print fmc.get_acq_fsm_state()
+        time.sleep(.1)
+        timeout += 1
+        if(ACQ_TIMEOUT < timeout):
+            print('Acquisition timeout. Check that the AWG is switched ON and properly connected.')
+            return 1
+    # Retrieve data trough DMA
+    trig_pos = fmc.get_trig_pos()
+    #print('Trigger position; 0x%X')%(trig_pos)
+    channels_data = spec_fmc.get_data((trig_pos<<3), ACQ_LENGTH*8)
+    return channels_data
+
+
+def plot_all(data, mean, ylimit):
+    sample = arange(len(data)/4)
+    clf()
+    plot(sample, data[0::4], 'b', label='Channel 1')
+    plot(sample, data[1::4], 'g', label='Channel 2')
+    plot(sample, data[2::4], 'c', label='Channel 3')
+    plot(sample, data[3::4], 'm', label='Channel 4')
+    plot(sample, [mean[0]]*len(sample), 'r')
+    plot(sample, [mean[1]]*len(sample), 'r')
+    plot(sample, [mean[2]]*len(sample), 'r')
+    plot(sample, [mean[3]]*len(sample), 'r')
+    ylim(-ylimit-(ylimit/10.0), ylimit+(ylimit/10.0))
+    grid(which='both')
+    legend()
+    draw()
+    show()
+    return 0
+
+
+# Converts digital value to volts
+def digital2volt(value, full_scale, nb_bit):
+    return float(value) * float(full_scale)/2**nb_bit - full_scale/2.0
+
+
+# Converts volts to digital value
+def volt2digital(value, full_scale, nb_bit):
+    digital = (value + full_scale/2) * 2**nb_bit/full_scale
+    if(digital > 2**nb_bit - 1):
+        digital = 2**nb_bit - 1
+    if(digital < 0):
+        digital = 0
+    return int(digital)
+
+
+def set_offset_dac(fmc, dac_fs, dac_nbits, channel, offset_volt):
+    dac_v = offset_volt
+    dac_d = volt2digital(dac_v,dac_fs,dac_nbits)
+    #print('DAC value: 0x%X (%fV)')%(dac_d, dac_v)
+    fmc.set_dc_offset(channel,dac_d)
+    time.sleep(DAC_SET_SLEEP)
+
+
+def get_mean_value(adc_fs, adc_nbits, acq):
+    mean_d = []
+    for channel in range(1,NB_CHANNELS+1):
+        mean_d.append(mean(acq[channel-1::4]))
+    mean_v = [digital2volt(item,adc_fs,adc_nbits) for item in mean_d]
+    return mean_v
+
+
+def main (default_directory = '.'):
+
+    # Load firmware to FPGA
+    load_firmware(default_directory)
+
+    # Objects declaration
+    spec = rr.Gennum() # bind to the SPEC board
+    spec_fmc = spec_fmc_adc.CSpecFmcAdc100Ms(spec)
+    fmc = fmc_adc.CFmcAdc100Ms(spec)
+    gen = Agilent33250A(device=USB_DEVICE, bauds=RS232_BAUD)
+    sine = SineWaveform()
+    box = calibr_box.CCalibr_box(1)
+
+    # Enable "DMA finished" IRQ
+    spec_fmc.set_irq_en_mask(0x1)
+
+    # Initialise fmc adc
+    fmc_adc_init(spec, fmc)
+
+    # Connect to AWG
+    #gen.connect()
+
+    # Switch AWG output OFF
+    #gen.output = False
+
+    # Measure FMC and carrier temperature
+    print('SPEC temperature: %3.3f°C') % spec_fmc.get_temp()
+    print('FMC temperature : %3.3f°C') % fmc.get_temp()
+
+    # Open all switches, reset offset DAC to mid-scale (0V)
+    for channel in range(1,NB_CHANNELS+1):
+        fmc.set_input_range(channel, 'OPEN')
+        fmc.set_input_term(channel, 'OFF')
+    fmc.dc_offset_reset()
+
+
+    # ADC full scale is 100mV
+    select = raw_input('Select input range [1=10V, 2=1V, 3=100mV]:')
+    if('1' == select):
+        print('10V input range selected')
+        ADC_FS = 10.0
+        in_range = '10V'
+    elif('2' == select):
+        print('1V input range selected')
+        ADC_FS = 1.0
+        in_range = '1V'
+    elif('3' == select):
+        print('100mV input range selected')
+        ADC_FS = 0.1
+        in_range = '100mV'
+    else:
+        print('10V input range selected')
+        ADC_FS = 10.0
+        in_range = '10V'
+
+    # Set calibration box to AWG
+    box.select_output('AWG')
+    time.sleep(BOX_SET_SLEEP)
+
+    # All offset DACs to 0V
+    for channel in range(1,NB_CHANNELS+1):
+        set_offset_dac(fmc, DAC_FS, DAC_NBITS, channel, 0.0)
+
+    # Set channel input range
+    for channel in range(1,NB_CHANNELS+1):
+        fmc.set_input_range(channel, in_range)
+        time.sleep(SSR_SET_SLEEP)
+
+    # Measures value on each channel
+    acq_d = acquisition_all(fmc, spec_fmc)
+    acq_v = [digital2volt(item,ADC_FS,ADC_NBITS) for item in acq_d]
+    mean_v = get_mean_value(ADC_FS, ADC_NBITS, acq_d)
+    plot_all(acq_v, mean_v, ADC_FS/2.0)
+
+
+    # Close AWG
+    #gen.close()
+
+    # Check if an error occured during frequency response test
+    #if(error != 0):
+    #    raise PtsError('An error occured during frequency response test, check log for details.')
+
+
+if __name__ == '__main__' :
+    main()