Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC ADC 100M 14b 4cha - Testing
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC ADC 100M 14b 4cha - Testing
Commits
6c18bc6c
Commit
6c18bc6c
authored
Jul 17, 2013
by
Matthieu Cattin
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
fmc_adc: Fix (svec specific) functions name.
parent
53ad6e22
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
2 additions
and
2 deletions
+2
-2
fmc_adc.py
test/fmcadc100m14b4cha/python/fmc_adc.py
+2
-2
No files found.
test/fmcadc100m14b4cha/python/fmc_adc.py
View file @
6c18bc6c
...
...
@@ -898,13 +898,13 @@ class CFmcAdc100m:
# Write data to DDR
# carrier_addr is in 32-bit word
# data must be a array of 32-bit words
def
ge
t_data
(
self
,
carrier_addr
,
data
):
def
pu
t_data
(
self
,
carrier_addr
,
data
):
self
.
bus
.
iwrite
(
0
,
self
.
DDR_ADR_ADDR
,
4
,
carrier_addr
)
for
i
in
range
(
len
(
data
)):
self
.
bus
.
iwrite
(
0
,
self
.
DDR_DAT_ADDR
,
4
,
data
[
i
])
# Clear DDR
def
get_data
(
self
):
def
clear_ddr
(
self
):
self
.
bus
.
iwrite
(
0
,
self
.
DDR_ADR_ADDR
,
4
,
0x0
)
for
i
in
range
(
0x4000000
):
self
.
bus
.
iwrite
(
0
,
self
.
DDR_DAT_ADDR
,
4
,
0x0
)
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment