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FMC ADC 100M 14b 4cha - Testing
Commit 7c75c0d3 authored by Matthieu Cattin's avatar Matthieu Cattin
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svec_test01, svec_test12: Add tests

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test/fmcadc100m14b4cha/python/svec_test01.py 0 → 100755
View file @ 7c75c0d3
#! ./python
# coding: utf8
# Copyright CERN, 2013
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Import system modules
import sys
import time
import os
# Add common modules and libraries location to path
sys.path.append('../../../')
sys.path.append('../../../common/')
sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/')
# Import common modules
from ptsexcept import *
from rr2vv import *
# Import specific modules
from fmc_adc_svec import *
from fmc_adc import *
"""
test01: Test mezzanines (all peripherals, 1-wire, i2c, spi, etc...)
"""
def main (default_directory='.'):
# Constants declaration
LUN = 0
TEST_NB = 1
FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0
NB_CHANNELS = 4
EEPROM_ADDR = 0x50
SI570_ADDR = 0x55
TEST_PATTERN = 0x6A1
start_test_time = time.time()
print "\n================================================================================"
print "==> [SVEC] Test%02d start\n" % TEST_NB
# SVEC object declaration
print "Loading hardware access library and opening device.\n"
bus = VME_rr_compatible(LUN)
print "Initialising device.\n"
# Load FMC ADC firmware
ask = 'N'
while ((ask != "Y") and (ask != "N")) :
ask = raw_input("Do you want to load the firmware: %s? [y,n]"%(FMC_ADC_BITSTREAM))
ask = ask.upper()
print " "
if (ask == "Y"):
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM
bus.vv_init()
ret = bus.vv_load(FMC_ADC_BITSTREAM, 1)
print('')
time.sleep(2)
else:
bus.vv_open()
# Carrier object declaration (SPEC board specific part)
try:
carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE)
except FmcAdc100mSvecOperationError as e:
raise PtsCritical("Carrier init failed, test stopped: %s" % e)
# Test carrier periherals
print('\n-------------------------------------------------------------')
print('[Carrier]')
carrier.print_unique_id()
carrier.print_temp()
# Mezzanines object declaration (FmcAdc100m14b4cha board specific part)
fmc = []
for i in range(2):
try:
print('\n-------------------------------------------------------------')
print('[FMC slot %d]'%(i+1))
mezz_offset = 0x2000+i*0x4000
print('Mezzanine offset: 0x%08X'%(mezz_offset))
fmc.append(CFmcAdc100m(bus, mezz_offset))
except FmcAdc100mOperationError as e:
raise PtsCritical("Mezzanine %d init failed, test stopped: %s" % (i+1, e))
# Test mezzanines peripherals
error = ['','']
for i in range(2):
try:
print('\n-------------------------------------------------------------')
print('[FMC slot %d]'%(i+1))
# 1-wire
fmc[i].print_unique_id()
fmc[i].print_temp()
# System i2c bus
EEPROM_ADDR = EEPROM_ADDR+i*0x2
periph_addr = fmc[i].sys_i2c_scan()
if(0 == len(periph_addr)):
error[i] = "No peripheral detected on system management I2C bus"
if(1 != len(periph_addr)):
error[i] = "Signal integrity problem detected on system management I2C bus, %d devices detected instead of 1" % len(periph_addr)
if(EEPROM_ADDR != periph_addr[0]):
error[i] = "Wrong device mounted on system management I2C bus or soldering issues, address is:0x%.2X expected:0x%.2X" % (periph_addr[0],EEPROM_ADDR)
# LEDs
"""
print('\nBlinking LEDs')
for j in range(3):
fmc[i].trig_led(1)
fmc[i].acq_led(1)
time.sleep(.5)
fmc[i].trig_led(0)
fmc[i].acq_led(0)
time.sleep(.5)
"""
# i2c bus
periph_addr = fmc[i].i2c_scan()
if(0 == len(periph_addr)):
error[i] = 'No peripheral detected on I2C bus'
if(1 != len(periph_addr)):
error[i] = 'Signal integrity problem detected on I2C bus, %d devices detected instead of 1'%(len(periph_addr))
if(SI570_ADDR != periph_addr[0]):
error[i] = 'Wrong device mounted on I2C bus, address is:0x%.2X expected:0x%.2X'%(periph_addr[0],SI570_ADDR)
# CSR
#fmc[i].print_adc_core_config()
# LTC2174 (SPI)
fmc[i].testpat_en(TEST_PATTERN)
pattern = fmc[i].get_testpat()
if(TEST_PATTERN != pattern):
print('pattern:%.4X read:%.4X')%(TEST_PATTERN, pattern)
raise PtsError('Cannot access LTC2174 ADC through SPI')
fmc[i].print_adc_regs()
if(0 == fmc[i].get_serdes_sync_stat()):
print('SerDes are not synchronised')
raise PtsError('SerDes are not synchronised')
else:
print "SerDes are synchronised.\n"
print "Check received data."
for j in range(1,NB_CHANNELS+1):
adc_value = fmc[i].get_current_adc_value(j)
adc_s = '0b{0:0>16b}'.format(int(adc_value))
pat_s = '0b{0:0>16b}'.format(int(TEST_PATTERN<<2))
print('ADC channel %d value:%s' % (j, adc_s))
print(' expected:%s' % (pat_s))
if((TEST_PATTERN<<2) != adc_value):
print('[Channel %d] Error: value mismatch!'%(j))
error[i] = '[Channel %d] LTC2174 test pattern error: value mismatch!'%(j)
# External trigger
# hw trig, rising edge, external, sw disable, no delay
print('')
fmc[i].set_trig_config(1, 0, 1, 1, 1, 0, 0)
fmc[i].set_pre_trig_samples(500)
fmc[i].set_post_trig_samples(500)
fmc[i].set_shots(1)
fmc[i].stop_acq()
print "Acquisition FSM state : %s (should be IDLE)" % fmc[i].get_acq_fsm_state()
fmc[i].start_acq()
print "Wait for trigger."
time.sleep(1.1)
if('WAIT_TRIG' == fmc[i].get_acq_fsm_state()):
raise PtsError('Acquisition FSM state : %s' % fmc[i].get_acq_fsm_state())
else:
print('The external trigger input is working fine.')
# DDR access
print('\nTest DDR access')
print('Read DDR')
ddr_data_rd = fmc[i].get_data(0x0, 15)
print('Write DDR')
ddr_data_wr = range(10)
fmc[i].put_data(0x0, ddr_data_wr)
ddr_data_wr.extend([0x0]*5)
print('Read DDR')
ddr_data_rdb = fmc[i].get_data(0x0, 15)
print('addr: read: written: read back:')
for j in range(len(ddr_data_rd)):
print('%.3d 0x%.8x 0x%.8x 0x%.8x'%(j, ddr_data_rd[j], ddr_data_wr[j], ddr_data_rdb[j]))
except FmcAdc100mOperationError as e:
raise PtsError("Mezzanine %d onewire test failed: %s" % (i+1, e))
print('')
print "==> End of test%02d" % TEST_NB
print "================================================================================"
end_test_time = time.time()
print "[SVEC] Test%02d elapsed time: %.2f seconds\n" % (TEST_NB, end_test_time-start_test_time)
if(error[0] != ''):
raise PtsError('[FMC slot 1]' + error[0])
if(error[1] != ''):
raise PtsError('[FMC slot 2]' + error[1])
bus.vv_close()
if __name__ == '__main__' :
main()
test/fmcadc100m14b4cha/python/svec_test12.plot 0 → 100644
View file @ 7c75c0d3
set title 'Two fmc-adc on svec'
set xlabel 'Samples'
set ylabel 'Volts'
set yr[-11:11]
plot 'svec_test12_data.txt' using 1:2 title 'FMC1 Channel 1' with line, \
'svec_test12_data.txt' using 1:3 title 'FMC1 Channel 2' with line, \
'svec_test12_data.txt' using 1:4 title 'FMC1 Channel 3' with line, \
'svec_test12_data.txt' using 1:5 title 'FMC1 Channel 4' with line, \
'svec_test12_data.txt' using 1:6 title 'FMC2 Channel 1' with line, \
'svec_test12_data.txt' using 1:7 title 'FMC2 Channel 2' with line, \
'svec_test12_data.txt' using 1:8 title 'FMC2 Channel 3' with line, \
'svec_test12_data.txt' using 1:9 title 'FMC2 Channel 4' with line
pause -1 "Hit carrige return to continue"
\ No newline at end of file
test/fmcadc100m14b4cha/python/svec_test12.py 0 → 100755
View file @ 7c75c0d3
#! ./python
# coding: utf8
# Copyright CERN, 2013
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 30/5/2012
# Import system modules
import sys
import time
import os
# Add common modules and libraries location to path
sys.path.append('../../../')
sys.path.append('../../../common/')
sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/')
# Import common modules
from ptsexcept import *
from rr2vv import *
# Import specific modules
from fmc_adc_svec import *
from fmc_adc import *
from numpy import *
"""
svec_test12: Takes an aqcuisition of all channels and print it to a file
Set UTC and read UTC time-tags
Note: Requires svec_test00.py to run first to load the firmware!
"""
NB_CHANNELS = 4
AWG_SET_SLEEP = 0.3
SSR_SET_SLEEP = 0.05
BOX_SET_SLEEP = 0.01
ACQ_TIMEOUT = 10
PRE_TRIG_SAMPLES = 10
POST_TRIG_SAMPLES = 10000
NB_SHOTS = 1
ACQ_LENGTH = 10000 # in samples
def open_all_channels(fmc):
for i in range(1,NB_CHANNELS+1):
fmc.set_input_range(i, 'OPEN')
time.sleep(SSR_SET_SLEEP)
def fmc_adc_init(bus, fmc):
print "Initialise FMC board.\n"
# Reset offset DACs
fmc.dc_offset_reset()
# Make sure all switches are OFF
open_all_channels(fmc)
# Set software trigger
fmc.set_soft_trig()
# Set acquisition
fmc.set_pre_trig_samples(PRE_TRIG_SAMPLES)
fmc.set_post_trig_samples(POST_TRIG_SAMPLES)
fmc.set_shots(NB_SHOTS)
# Converts two's complement hex to signed
def hex2signed(value):
if(value & 0x8000):
return -((~value & 0xFFFF) + 1)
else:
return value
# Converts digital value to volts
def digital2volt(value, full_scale, nb_bit):
return float(value) * float(full_scale)/2**nb_bit
def acq_channels(fmc, carrier, adc_fs, pause):
# Make sure no acquisition is running
fmc.stop_acq()
time.sleep(pause)
# Start acquisition
fmc.start_acq()
time.sleep(pause)
# Trigger
fmc.sw_trig()
# Wait end of acquisition
timeout = 0
while('IDLE' != fmc.get_acq_fsm_state()):
time.sleep(.1)
timeout += 1
if(ACQ_TIMEOUT < timeout):
print "Acquisition timeout. Missing trigger?."
print "Acq FSm state: %s"%fmc.get_acq_fsm_state()
return 1
# Retrieve data trough DMA
trig_pos = fmc.get_trig_pos()
# Read ACQ_LENGTH samples after the trigger for all channels
print('Getting data from DDR...')
channels_data = fmc.get_data((trig_pos<<3), ACQ_LENGTH*8)
#print [hex(val) for val in channels_data[0::4][:10]]
channels_data = [hex2signed(item) for item in channels_data]
#print [hex(val) for val in channels_data[0::4][:10]]
channels_data = [digital2volt(item,adc_fs,16) for item in channels_data]
#print channels_data[0::4][:10]
return channels_data
def main (default_directory='.'):
# Constants declaration
LUN = 0
TEST_NB = 12
FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x0
start_test_time = time.time()
print "================================================================================"
print "[SVEC] Test%02d start\n" % TEST_NB
# SVEC object declaration
print "Loading hardware access library and opening device.\n"
bus = VME_rr_compatible(LUN)
bus.vv_open()
# Carrier object declaration (SVEC board specific part)
# Used to check that the firmware is loaded.
try:
carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE)
except FmcAdc100mSvecOperationError as e:
raise PtsCritical("Carrier init failed, test stopped: %s" % e)
"""
# Mezzanine object declaration (FmcAdc100m14b4cha board specific part)
try:
fmc = CFmcAdc100m(bus, 0x2000)
except FmcAdc100mOperationError as e:
raise PtsCritical("Mezzanine init failed, test stopped: %s" % e)
"""
# Mezzanines object declaration (FmcAdc100m14b4cha board specific part)
fmc = []
for i in range(2):
try:
print('\n--------------------------------------------------------------------------------')
print('\n--------------------------------------------------------------------------------')
print('[FMC slot %d]'%(i+1))
mezz_offset = 0x2000+i*0x4000
print('Mezzanine offset: 0x%08X'%(mezz_offset))
fmc.append(CFmcAdc100m(bus, mezz_offset))
except FmcAdc100mOperationError as e:
raise PtsCritical("Mezzanine %d init failed, test stopped: %s" % (i+1, e))
try:
fmc_channels = [[],[]]
for i in range(2):
print('\n--------------------------------------------------------------------------------')
print('\n--------------------------------------------------------------------------------')
print('[FMC slot %d]'%(i+1))
# Initialise fmc adc
fmc_adc_init(bus, fmc[i])
# Use test data instead of data from ADC
# fmc.test_data_en()
# Use data pattern instead of ADC data
# fmc.testpat_en(0x2000)
# Print configuration
fmc[i].print_adc_core_config()
# Print ADC config
fmc[i].print_adc_config()
# Set UTC
current_time = time.time()
utc_seconds = int(current_time)
fmc[i].set_utc_second_cnt(utc_seconds)
print "UTC core seconds counter initialised to : %d" % fmc[i].get_utc_second_cnt()
utc_coarse = int((current_time - utc_seconds)/8E-9)
fmc[i].set_utc_coarse_cnt(utc_coarse)
print "UTC core coarse counter initialised to : %d" % fmc[i].get_utc_coarse_cnt()
# Acquisition parameters
ACQ_PAUSE = 1 # pause between acq. stop and start, start and trigger
IN_RANGE = '10V'
IN_TERM = 'ON'
ADC_FS = {'10V':10.0, '1V':1.0, '100mV':0.1}
channels_data = [[],[],[],[]]
for ch in range(NB_CHANNELS):
# Configure analogue input
fmc[i].set_input_range(ch+1, IN_RANGE)
fmc[i].set_input_term(ch+1, IN_TERM)
time.sleep(SSR_SET_SLEEP)
# Perform an acquisition
print "\nAcquiring channels"
acq_data = acq_channels(fmc[i], carrier, ADC_FS[IN_RANGE], ACQ_PAUSE)
for ch in range(NB_CHANNELS):
channels_data[ch] = acq_data[ch::4]
# Get time-tags
trig_tag = fmc[i].get_utc_trig_tag()
start_tag = fmc[i].get_utc_start_tag()
stop_tag = fmc[i].get_utc_stop_tag()
end_tag = fmc[i].get_utc_end_tag()
print('Acq stop time-tag : %10.10f [s]')%(stop_tag[2]+(stop_tag[3]*8E-9))
print('Acq start time-tag : %10.10f [s]')%(start_tag[2]+(start_tag[3]*8E-9))
print('Trigger time-tag : %10.10f [s]')%(trig_tag[2]+(trig_tag[3]*8E-9))
print('Acq end time-tag : %10.10f [s]')%(end_tag[2]+(end_tag[3]*8E-9))
fmc[i].print_utc_core_regs()
# Calculate mean for each channel data
ch_mean = []
for ch in range(NB_CHANNELS):
ch_mean.append(mean(channels_data[ch]))
# Make sure all switches are OFF
open_all_channels(fmc[i])
fmc_channels[i] = channels_data
# print aqcuisition to file
file_name = "svec_test12_data.txt"
f = open(file_name, 'w')
f.write("#Sample, FMC1 ch1 value [V], FMC1 ch2 value [V], FMC1 ch3 value [V], FMC1 ch4 value [V], FMC2 ch1 value [V], FMC2 ch2 value [V], FMC2 ch3 value [V], FMC2 ch4 value [V]\n")
for i in range(len(fmc_channels[0][0])):
f.write("%d, %2.9f, %2.9f, %2.9f, %2.9f, %2.9f, %2.9f, %2.9f, %2.9f\n"%(i, fmc_channels[0][0][i], fmc_channels[0][1][i], fmc_channels[0][2][i], fmc_channels[0][3][i], fmc_channels[1][0][i], fmc_channels[1][1][i], fmc_channels[1][2][i], fmc_channels[1][3][i]))
f.close()
except(FmcAdc100mSvecOperationError, FmcAdc100mOperationError) as e:
raise PtsError("Test failed: %s" % e)
print ""
print "==> End of test%02d" % TEST_NB
print "================================================================================"
end_test_time = time.time()
print "Test%02d elapsed time: %.2f seconds\n" % (TEST_NB, end_test_time-start_test_time)
if __name__ == '__main__' :
main()
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