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FMC ADC 100M 14b 4cha - Testing
Commit 87681ba7 authored by Matthieu Cattin's avatar Matthieu Cattin
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Add test16, frequency response test.

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test/fmcadc100m14b4cha/python/test16.py 0 → 100755
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#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
import sys
import rr
import time
import os
from numpy import *
from pylab import *
from ptsexcept import *
import gn4124
import spec_fmc_adc
import fmc_adc
from PAGE.Agilent33250A import *
from PAGE.SineWaveform import *
"""
test16: Test analogue front-end frequency response
Note: Requires test00.py to run first to load the firmware!
"""
GN4124_CSR = 0x0
USB_DEVICE = "/dev/ttyUSB0"
RS232_BAUD = 57600
NB_CHANNELS = 4
AWG_SET_SLEEP = 1
SSR_SET_SLEEP = 0.05
ACQ_TIMEOUT = 10
MAX_FIRMWARE_RELOAD = 10
PRE_TRIG_SAMPLES = 10
POST_TRIG_SAMPLES = 1000
NB_SHOTS = 1
ACQ_LENGTH = 1 # in samples
DMA_LENGTH = 4096 # in bytes
# col 0: freq
# col 1: expected amplitude (ADC raw data)
# col 2: tolerance on the amplitude
points = [[1E3, 33300, 4000],
[10E3, 33300, 4000],
[100E3, 33300, 4000],
[1E6, 33300, 4000],
[10E6, 21000, 4000],
[15E6, 16500, 4000],
[16E6, 15700, 4000],
[17E6, 15000, 4000],
[18E6, 14500, 4000],
[19E6, 14000, 4000],
[20E6, 12500, 4000],
[21E6, 12500, 4000],
[22E6, 12500, 4000],
[23E6, 12000, 4000],
[24E6, 11500, 4000],
[25E6, 10000, 4000],
[30E6, 9000, 4000],
[32E6, 9000, 4000],
[34E6, 9000, 4000],
[36E6, 9000, 4000],
[38E6, 9000, 4000],
[40E6, 4500, 4000],
[42E6, 4500, 4000],
[44E6, 4500, 4000],
[46E6, 4500, 4000],
[48E6, 4500, 4000],
[60E6, 1000, 700],
[80E6, 400, 300]]
# The following table is used to test the test
"""
points = [[1E6, 36300, 1000],
[10E6, 24000, 1000],
[15E6, 19500, 1000],
[16E6, 18700, 1000],
[17E6, 18000, 1000],
[18E6, 17500, 1000],
[19E6, 17000, 1000],
[20E6, 15500, 1000],
[21E6, 15500, 1000],
[22E6, 15500, 1000],
[23E6, 15000, 1000],
[24E6, 14500, 1000],
[25E6, 14000, 2000],
[30E6, 12000, 1000],
[40E6, 7500, 1000],
[60E6, 4000, 500],
[80E6, 3400, 200]]
"""
def load_firmware(default_directory):
print('Load firmware to FPGA')
path_fpga_loader = '../../../gnurabbit/user/fpga_loader';
path_firmware = '../firmwares/spec_fmcadc100m14b4cha_test.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
print firmware_loader + ' ' + bitstream
os.system( firmware_loader + ' ' + bitstream )
time.sleep(2);
def open_all_channels(fmc):
for i in range(1,NB_CHANNELS+1):
fmc.set_input_range(i, 'OPEN')
time.sleep(SSR_SET_SLEEP)
def fmc_adc_init(spec, fmc):
print('Initialise FMC board.')
fmc.__init__(spec)
# Reset offset DACs
fmc.dc_offset_reset()
# Make sure all switches are OFF
open_all_channels(fmc)
# Set trigger
fmc.set_soft_trig()
# Set acquisition
fmc.set_pre_trig_samples(PRE_TRIG_SAMPLES)
fmc.set_post_trig_samples(POST_TRIG_SAMPLES)
fmc.set_shots(NB_SHOTS)
# Print configuration
fmc.print_adc_core_config()
def set_awg_freq(gen, sine, freq):
sine.frequency = freq
gen.play(sine)
print('Sine frequency:%3.3fMHz')%(sine.frequency/1E6)
time.sleep(AWG_SET_SLEEP)
def acquisition(gnum, pages, fmc, spec_fmc, channel_nb):
# Make sure no acquisition is running
fmc.stop_acq()
#print('Acquisition FSM state : %s') % fmc.get_acq_fsm_state()
# Start acquisition
fmc.start_acq()
time.sleep(0.01)
# Trigger
fmc.sw_trig()
# Wait end of acquisition
timeout = 0
while('IDLE' != fmc.get_acq_fsm_state()):
#print fmc.get_acq_fsm_state()
time.sleep(.1)
timeout += 1
if(ACQ_TIMEOUT < timeout):
print('Acquisition timeout. Check that the AWG is switched ON and properly connected.')
return 1
# Retrieve data trough DMA
channels_data = spec_fmc.get_data(0x0, ACQ_LENGTH*8)
return channels_data[channel_nb-1::4]
def show_result_graph(points, ch_diff):
pt = array(points)
freq = pt[:,0]
a_min = pt[:,1] - pt[:,2]
a_max = pt[:,1] + pt[:,2]
semilogx(freq, ch_diff[0::4], 'b', label='Channel 1')
semilogx(freq, ch_diff[1::4], 'g', label='Channel 2')
semilogx(freq, ch_diff[2::4], 'r', label='Channel 3')
semilogx(freq, ch_diff[3::4], 'c', label='Channel 4')
#semilogx(freq, a_min, 'r:', label='Lower limit')
#semilogx(freq, a_max, 'r:', label='Upper limit')
grid(which='both')
legend()
show()
return 0
def main (default_directory='.'):
# Load firmware to FPGA
path_fpga_loader = '../../../gnurabbit/user/fpga_loader';
path_firmware = '../firmwares/spec_fmcadc100m14b4cha_test.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
print firmware_loader + ' ' + bitstream
os.system( firmware_loader + ' ' + bitstream )
time.sleep(2);
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
gnum = gn4124.CGN4124(spec, GN4124_CSR)
spec_fmc = spec_fmc_adc.CSpecFmcAdc100Ms(spec)
fmc = fmc_adc.CFmcAdc100Ms(spec)
gen = Agilent33250A(device=USB_DEVICE, bauds=RS232_BAUD)
sine = SineWaveform()
# Enable "DMA finished" IRQ
spec_fmc.set_irq_en_mask(0x1)
# Initialise fmc adc
fmc_adc_init(spec, fmc)
# Set sine params
sine.frequency = 1E6
sine.amplitude = 0.8
sine.dc = 0
print('Sine frequency:%3.3fMHz amplitude:%2.3fVp offset:%2.3fV')%(sine.frequency/1E6, sine.amplitude, sine.dc)
# Set AWG
gen.connect()
gen.play(sine)
gen.output = True
# Get physical addresses of the pages for DMA transfer
pages = gnum.get_physical_addr()
# Test frequency response of all channels
ch_diff = []
for j in range(len(points)):
set_awg_freq(gen, sine, points[j][0])
for i in range(1,NB_CHANNELS+1):
fmc.set_input_range(i, '1V')
fmc.set_input_term(i, 'ON')
time.sleep(SSR_SET_SLEEP)
channel_data = []
channel_data = acquisition(gnum, pages, fmc, spec_fmc, i)
diff = max(channel_data)-min(channel_data)
#print('CH%d amplitude:%d expected:%d +/-%d')%(i, diff, points[j][1], points[j][2])
ch_diff.append(diff)
fmc.set_input_range(i, 'OPEN')
fmc.set_input_term(i, 'OFF')
# print freqency response to log
print('Channels frequency response')
print('Frequency, CH1 value, CH2 value, CH3 value, CH4 value')
for i in range(len(points)):
print('%2.3f, %d, %d, %d, %d')%(points[i][0]/1E6, ch_diff[i*4], ch_diff[i*4+1], ch_diff[i*4+2], ch_diff[i*4+3])
# print aqcuisition to file
# open test09 log file in read mode
file_name = raw_input('Enter a file name (default=log_test16.txt):')
if file_name == "":
file_name = "log_test16.txt"
file = open(file_name, 'w')
file.write("Frequency, CH1 amplitude, CH2 amplitude, CH3 amplitude, CH4 amplitude\n")
for i in range(len(points)):
file.write('%2.3f, %d, %d, %d, %d\n'%(points[i][0]/1E6, ch_diff[i*4], ch_diff[i*4+1], ch_diff[i*4+2], ch_diff[i*4+3]))
# Plot results
show_result_graph(points, ch_diff)
# Make sure all switches are OFF
open_all_channels(fmc)
# Switch AWG OFF
gen.output = False
gen.close()
# Check if an error occured during frequency response test
#if(error != 0):
# raise PtsError('An error occured during frequency response test, check log for details.')
if __name__ == '__main__' :
main()
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