Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC ADC 100M 14b 4cha - Testing
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC ADC 100M 14b 4cha - Testing
Commits
8c77befe
Commit
8c77befe
authored
Sep 06, 2011
by
Matthieu Cattin
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
work on test09
parent
4511dc39
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
88 additions
and
94 deletions
+88
-94
test05.py
test/fmcadc100m14b4cha/python/test05.py
+1
-1
test09.py
test/fmcadc100m14b4cha/python/test09.py
+87
-93
No files found.
test/fmcadc100m14b4cha/python/test05.py
View file @
8c77befe
...
@@ -65,4 +65,4 @@ def main (default_directory='.'):
...
@@ -65,4 +65,4 @@ def main (default_directory='.'):
if
__name__
==
'__main__'
:
if
__name__
==
'__main__'
:
main
()
;
main
()
test/fmcadc100m14b4cha/python/test09.py
View file @
8c77befe
...
@@ -10,6 +10,8 @@ import sys
...
@@ -10,6 +10,8 @@ import sys
import
rr
import
rr
import
time
import
time
import
os
import
os
from
numpy
import
*
from
pylab
import
*
from
ptsexcept
import
*
from
ptsexcept
import
*
...
@@ -25,6 +27,7 @@ test09: Test analogue front-end frequency response
...
@@ -25,6 +27,7 @@ test09: Test analogue front-end frequency response
Note: Requires test00.py to run first to load the firmware!
Note: Requires test00.py to run first to load the firmware!
"""
"""
GN4124_CSR
=
0x0
USB_DEVICE
=
"/dev/ttyUSB0"
USB_DEVICE
=
"/dev/ttyUSB0"
RS232_BAUD
=
57600
RS232_BAUD
=
57600
...
@@ -33,91 +36,48 @@ NB_CHANNELS = 4
...
@@ -33,91 +36,48 @@ NB_CHANNELS = 4
AWG_SET_SLEEP
=
1
AWG_SET_SLEEP
=
1
SSR_SET_SLEEP
=
0.05
SSR_SET_SLEEP
=
0.05
ADC_MID_TOL
=
500
PRE_TRIG_SAMPLES
=
1000
ADC_MID_THRESHOLD
=
10
POST_TRIG_SAMPLES
=
1000
NB_SHOTS
=
1
SW1_TOL
=
30000
DMA_LENGTH
=
4096
# DMA length in bytes
SW2_TOL
=
5000
SW3_TOL
=
5000
SW4_TOL
=
10000
SW5_TOL
=
100
SW6_TOL
=
20000
SW7_TOL
=
20000
RETRY_NB
=
10
FREQ_POINTS
=
[
1E6
,
10E6
,
15E6
,
16E6
,
17E6
,
18E6
,
19E6
,
20E6
,
21E6
,
22E6
,
23E6
,
24E6
,
25E6
,
30E6
,
40E6
,
60E6
,
80E6
]
SW1_THRESHOLD
=
10
SW2_THRESHOLD
=
10
SW3_THRESHOLD
=
10
SW4_THRESHOLD
=
10
SW5_THRESHOLD
=
5
SW6_THRESHOLD
=
10
SW7_THRESHOLD
=
10
def
open_all_channels
(
fmc
):
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
fmc
.
set_input_range
(
i
,
'OPEN'
)
time
.
sleep
(
SSR_SET_SLEEP
)
def
set_awg_freq
(
gen
,
sine
,
freq
):
def
set_awg_freq
(
gen
,
sine
,
freq
):
sine
.
frequency
=
freq
sine
.
frequency
=
freq
gen
.
play
(
sine
)
gen
.
play
(
sine
)
print
(
'Sine frequency:
%3.3
fMHz'
)
%
(
sine
.
frequency
/
1E6
)
time
.
sleep
(
AWG_SET_SLEEP
)
time
.
sleep
(
AWG_SET_SLEEP
)
def
print_current_adc_value
(
fmc
,
channel
,
file
):
def
acquisition
(
gnum
,
pages
,
fmc
,
channel
):
adc_value
=
fmc
.
get_current_adc_value
(
channel
)
# Start acquisition
print
(
'CH
%
d ADC value:0x
%.4
X
%
d'
)
%
(
channel
,
adc_value
,
adc_value
)
fmc
.
stop_acq
()
file
.
write
(
'CH
%
d: 0x
%.4
X
%
d
\n
'
%
(
channel
,
adc_value
,
adc_value
))
#print('Acquisition FSM state : %s') % fmc.get_acq_fsm_state()
fmc
.
start_acq
()
# Routine to test SSR (Solid State Relay)
# Wait end of acquisition
# Basic operation: Set AWG DC offset and SSRs -> read ADC value, change 1 SSR -> read ADC -> check ADC values difference
while
(
'IDLE'
!=
fmc
.
get_acq_fsm_state
()):
# Options: retry -> run the same test several times
#print fmc.get_acq_fsm_state()
# threshold -> minimum number of try to pass the test
time
.
sleep
(
.1
)
def
sw_test
(
gen
,
sine
,
awg_offset
,
fmc
,
sw
,
ssr_1
,
ssr_2
,
diff_tol
,
retry_nb
=
0
,
threshold
=
0
):
print
(
'
\n
Testing switch
%
d
\n
-------------------------'
)
%
sw
set_awg_offset
(
gen
,
sine
,
awg_offset
)
print
(
'AWG offset:
%1.3
fV'
)
%
awg_offset
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
# Retrieve data trough DMA
pass_nb
=
0
gnum
.
add_dma_item
(
0x100
,
pages
[
1
],
DMA_LENGTH
,
0
,
0
)
for
j
in
range
(
retry_nb
):
gnum
.
start_dma
()
fmc
.
set_ssr
(
i
,
ssr_1
)
gnum
.
wait_irq
()
time
.
sleep
(
SSR_SET_SLEEP
)
page1_data
=
gnum
.
get_memory_page
(
1
)
adc_value_before
=
fmc
.
get_current_adc_value
(
i
)
channels
=
[]
fmc
.
set_ssr
(
i
,
ssr_2
)
for
i
in
range
(
len
(
page1_data
)):
time
.
sleep
(
SSR_SET_SLEEP
)
channels
.
append
(
page1_data
[
i
]
&
0xFFFF
)
adc_value
=
fmc
.
get_current_adc_value
(
i
)
channels
.
append
(
page1_data
[
i
]
>>
16
)
diff
=
adc_value_before
-
adc_value
print
(
'CH
%
d ssr=0x
%.2
X:
%
d ssr=0x
%.2
X:
%
d diff:
%
d'
)
%
(
i
,
ssr_1
,
adc_value_before
,
ssr_2
,
adc_value
,
diff
)
if
(
diff_tol
<=
abs
(
diff
)):
pass_nb
+=
1
fmc
.
set_ssr
(
i
,
0x0
)
time
.
sleep
(
SSR_SET_SLEEP
)
print
(
' Number of good tests:
%
d threshold:
%
d'
)
%
(
pass_nb
,
threshold
)
if
(
pass_nb
<
threshold
):
print
(
'#####################################'
)
print
(
'SW
%
d of channel
%
d is malfunctionning'
)
%
(
sw
,
i
)
print
(
'#####################################'
)
raise
PtsError
(
'SW
%
d of channel
%
d is malfunctionning'
%
(
sw
,
i
))
def
adc_mid_test
(
gen
,
sine
,
awg_offset
,
fmc
,
tol
,
retry_nb
=
0
,
threshold
=
0
):
print
(
'
\n
Testing ADC middle scale
\n
-------------------------'
)
set_awg_offset
(
gen
,
sine
,
awg_offset
)
print
(
'AWG offset:
%1.3
fV'
)
%
awg_offset
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
return
channels
[
channel
-
1
::
4
]
pass_nb
=
0
ssr_1
=
0x0
for
j
in
range
(
retry_nb
):
fmc
.
set_ssr
(
i
,
ssr_1
)
time
.
sleep
(
SSR_SET_SLEEP
)
adc_value
=
fmc
.
get_current_adc_value
(
i
)
diff
=
adc_value
-
0x8000
print
(
'CH
%
d ssr=0x
%.2
X:
%
d diff:
%
d'
)
%
(
i
,
ssr_1
,
adc_value
,
diff
)
if
((
-
tol
<
diff
)
&
(
tol
>
diff
)):
pass_nb
+=
1
print
(
' Number of good tests:
%
d threshold:
%
d'
)
%
(
pass_nb
,
threshold
)
if
(
pass_nb
<
threshold
):
print
(
'############################################'
)
print
(
'One of channel
%
d switches is malfunctioning'
)
%
i
print
(
'############################################'
)
raise
PtsError
(
'One of channel
%
d switches is malfunctioning'
%
i
)
def
main
(
default_directory
=
'.'
):
def
main
(
default_directory
=
'.'
):
...
@@ -136,52 +96,86 @@ def main (default_directory='.'):
...
@@ -136,52 +96,86 @@ def main (default_directory='.'):
# Objects declaration
# Objects declaration
spec
=
rr
.
Gennum
()
# bind to the SPEC board
spec
=
rr
.
Gennum
()
# bind to the SPEC board
gnum
=
gn4124
.
CGN4124
(
spec
,
GN4124_CSR
)
fmc
=
fmc_adc
.
CFmcAdc100Ms
(
spec
)
fmc
=
fmc_adc
.
CFmcAdc100Ms
(
spec
)
gen
=
Agilent33250A
(
device
=
USB_DEVICE
,
bauds
=
RS232_BAUD
)
gen
=
Agilent33250A
(
device
=
USB_DEVICE
,
bauds
=
RS232_BAUD
)
sine
=
SineWaveform
()
sine
=
SineWaveform
()
# Set sine params
# Set sine params
sine
.
frequency
=
1E6
sine
.
frequency
=
1E6
sine
.
amplitude
=
1
sine
.
amplitude
=
0.25
sine
.
dc
=
0
sine
.
dc
=
0
print
(
'Sine frequency:
%3.3
fMHz amplitude:
%2.3
fVp offset:
%2.3
fV'
)
%
(
sine
.
frequency
/
1E6
,
sine
.
amplitude
,
sine
.
dc
)
# Set AWG
# Set AWG
gen
.
connect
()
gen
.
connect
()
gen
.
play
(
sine
)
gen
.
play
(
sine
)
gen
.
output
=
True
# Reset offset DACs
# Reset offset DACs
fmc
.
dc_offset_reset
()
fmc
.
dc_offset_reset
()
# Make sure all switches are OFF
# Make sure all switches are OFF
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
open_all_channels
(
fmc
)
fmc
.
set_ssr
(
i
,
0x00
)
# Get physical addresses of the pages for DMA transfer
pages
=
gnum
.
get_physical_addr
()
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
# Set trigger
fmc
.
set_input_range
(
i
,
'1V'
)
# hw trig, rising edge, external, sw disable, no delay
fmc
.
set_trig_config
(
1
,
0
,
1
,
1
,
0
,
0
,
0
)
# Turn AWG ON
gen
.
output
=
True
#
# Set acquisition
fmc
.
set_pre_trig_samples
(
PRE_TRIG_SAMPLES
)
fmc
.
set_post_trig_samples
(
POST_TRIG_SAMPLES
)
fmc
.
set_shots
(
NB_SHOTS
)
ch_diff
=
[]
for
j
in
range
(
len
(
FREQ_POINTS
)):
set_awg_freq
(
gen
,
sine
,
FREQ_POINTS
[
j
])
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
fmc
.
set_input_range
(
i
,
'1V'
)
time
.
sleep
(
SSR_SET_SLEEP
)
channel
=
acquisition
(
gnum
,
pages
,
fmc
,
i
)
ch_diff
.
append
(
max
(
channel
)
-
min
(
channel
))
fmc
.
set_input_range
(
i
,
'OPEN'
)
npoints
=
arange
(
0
,
len
(
ch_diff
)
/
4
,
1
)
loglog
(
FREQ_POINTS
,
ch_diff
[
0
::
4
],
'b'
,
FREQ_POINTS
,
ch_diff
[
1
::
4
],
'g'
,
FREQ_POINTS
,
ch_diff
[
2
::
4
],
'r'
,
FREQ_POINTS
,
ch_diff
[
3
::
4
],
'c'
)
show
()
raw_input
(
'Press ENTER'
)
adc_mid_test
(
gen
,
sine
,
0.25
,
fmc
,
ADC_MID_TOL
,
RETRY_NB
,
ADC_MID_THRESHOLD
)
"""
# Start acquisition
fmc.stop_acq()
print('Acquisition FSM state :
%
s')
%
fmc.get_acq_fsm_state()
fmc.start_acq()
# Wait end of acquisition
while('IDLE' != fmc.get_acq_fsm_state()):
print fmc.get_acq_fsm_state()
time.sleep(1)
# Retrieve data trough DMA
gnum.add_dma_item(0*DMA_LENGTH, pages[1]+0*DMA_LENGTH, DMA_LENGTH, 0, 0)
gnum.start_dma()
gnum.wait_irq()
page1_data = gnum.get_memory_page(1)
channels = []
for i in range(len(page1_data)):
channels.append(page1_data[i] & 0xFFFF)
channels.append(page1_data[i]>>16)
channel = [[],[],[],[]]
for i in range(NB_CHANNELS):
channel[i] = (channels[i::4])
print('ch
%
d min:
%
d max:
%
d diff:
%
d')
%
(i+1, min(channel[i]), max(channel[i]), max(channel[i])-min(channel[i]))
"""
sw_test
(
gen
,
sine
,
0.25
,
fmc
,
1
,
0x00
,
0x01
,
SW1_TOL
,
RETRY_NB
,
SW1_THRESHOLD
)
#for i in range(40):
sw_test
(
gen
,
sine
,
0.25
,
fmc
,
4
,
0x01
,
0x09
,
SW4_TOL
,
RETRY_NB
,
SW4_THRESHOLD
)
# print("channels:%.4X ch1:%.4X ch2:%.4X ch3:%.4X ch4:%.4X") % (channels[i], channel[0][i/4], channel[1][i/4], channel[2][i/4], channel[3][i/4])
sw_test
(
gen
,
sine
,
0.25
,
fmc
,
5
,
0x41
,
0x51
,
SW5_TOL
,
RETRY_NB
,
SW5_THRESHOLD
)
sw_test
(
gen
,
sine
,
0.25
,
fmc
,
6
,
0x00
,
0x60
,
SW5_TOL
,
RETRY_NB
,
SW6_THRESHOLD
)
sw_test
(
gen
,
sine
,
0.25
,
fmc
,
7
,
0x01
,
0x41
,
SW6_TOL
,
RETRY_NB
,
SW7_THRESHOLD
)
sw_test
(
gen
,
sine
,
0.01
,
fmc
,
2
,
0x20
,
0x22
,
SW2_TOL
,
RETRY_NB
,
SW2_THRESHOLD
)
sw_test
(
gen
,
sine
,
0.01
,
fmc
,
3
,
0x22
,
0x26
,
SW3_TOL
,
RETRY_NB
,
SW3_THRESHOLD
)
# Make sure all switches are OFF
# Make sure all switches are OFF
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
open_all_channels
(
fmc
)
fmc
.
set_ssr
(
i
,
0x00
)
# Switch AWG OFF
# Switch AWG OFF
gen
.
output
=
False
gen
.
output
=
False
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment