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FMC ADC 100M 14b 4cha - Testing
Commit 8ef2a6f5 authored by Matthieu Cattin's avatar Matthieu Cattin
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Optimise test time.

parent 087c8276
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Showing with 94 additions and 86 deletions
test/fmcadc100m14b4cha/python/fmc_adc.py
View file @ 8ef2a6f5
......@@ -32,6 +32,21 @@ def volt2digital(value, full_scale, nb_bit):
#print('volt2digital: %2.9f > %2.9f')%(value,digital)
return int(digital)
# Converts two's complement hex to signed
def hex2signed(value):
if(value & 0x8000):
return -((~value & 0xFFFF) + 1)
else:
return value
# Converts signed to two's complement hex
def signed2hex(value):
if value < 0:
return (((abs(value) ^ 0xffff) + 1) & 0xffff)
else:
return value
class CFmcAdc100Ms:
......@@ -138,8 +153,10 @@ class CFmcAdc100Ms:
IN_TERM_MASK = 0x08
IN_RANGES = {'100mV': 0x23, '1V': 0x11, '10V': 0x45, 'CAL': 0x40, 'OPEN': 0x00, 'CAL_100mV': 0x42, 'CAL_1V': 0x40, 'CAL_10V': 0x44}
dac_offset_corr = [0.0] * 4
dac_gain_corr = [1.0] * 4
dac_corr_data = {'10V':{'offset':[0x0,0x0,0x0,0x0],'gain':[0x8000,0x8000,0x8000,0x8000]},
'1V':{'offset':[0x0,0x0,0x0,0x0],'gain':[0x8000,0x8000,0x8000,0x8000]},
'100mV':{'offset':[0x0,0x0,0x0,0x0],'gain':[0x8000,0x8000,0x8000,0x8000]}}
def channel_addr(self, channel, reg):
......@@ -301,50 +318,29 @@ class CFmcAdc100Ms:
else:
raise Exception('Unsupported parameter, channel number from 1 to 4')
def set_dac_corr(self, gain, offset):
self.dac_offset_corr = offset
self.dac_gain_corr = gain
def set_dac_corr(self, corr_data):
self.dac_corr_data = corr_data
def dac_apply_corr(self, value, gain_corr, offset_corr):
value = digital2volt(value, 10, 16)
value_corr = (float(value) + offset_corr) * gain_corr
return volt2digital(value_corr, 10, 16)
#print "dac_apply_corr: value:%d offset:%d gain:%d"%(value, hex2signed(offset_corr), gain_corr)
value_corr = (((((value - 0x8000) + hex2signed(offset_corr)) << 15) * gain_corr) >> 30) + 0x8000
return value_corr
# Set DC offset with gain and offset correction
# value = DAC unsigned integer value
def set_dc_offset_corrected(self, channel, value):
print_value = False
def set_dc_offset_corrected(self, channel, in_range, value, print_value=False):
uncorr_value = value
value = self.dac_apply_corr(value, self.dac_corr_data[in_range]['gain'][channel-1],self.dac_corr_data[in_range]['offset'][channel-1])
if(print_value):
print('CH%d DAC uncorrected value: 0x%.4X')%(channel, uncorr_value)
print('CH%d DAC corrected value : 0x%.4X')%(channel, value)
if(1 == channel):
uncorr_value = value
value = self.dac_apply_corr(value, self.dac_gain_corr[channel-1],self.dac_offset_corr[channel-1])
#print('gain corr: %1.9f offset corr: %1.9f')%(self.dac_gain_corr[channel-1], self.dac_offset_corr[channel-1])
if(print_value):
print('CH%d DAC uncorrected value: 0x%.4X')%(channel, uncorr_value)
print('CH%d DAC corrected value : 0x%.4X')%(channel, value)
self.dac_ch1.set_offset(value)
elif(2 == channel):
uncorr_value = value
value = self.dac_apply_corr(value, self.dac_gain_corr[channel-1],self.dac_offset_corr[channel-1])
#print('gain corr: %1.9f offset corr: %1.9f')%(self.dac_gain_corr[channel-1], self.dac_offset_corr[channel-1])
if(print_value):
print('CH%d DAC uncorrected value: 0x%.4X')%(channel, uncorr_value)
print('CH%d DAC corrected value : 0x%.4X')%(channel, value)
self.dac_ch2.set_offset(value)
elif(3 == channel):
uncorr_value = value
value = self.dac_apply_corr(value, self.dac_gain_corr[channel-1],self.dac_offset_corr[channel-1])
#print('gain corr: %1.9f offset corr: %1.9f')%(self.dac_gain_corr[channel-1], self.dac_offset_corr[channel-1])
if(print_value):
print('CH%d DAC uncorrected value: 0x%.4X')%(channel, uncorr_value)
print('CH%d DAC corrected value : 0x%.4X')%(channel, value)
self.dac_ch3.set_offset(value)
elif(4 == channel):
uncorr_value = value
value = self.dac_apply_corr(value, self.dac_gain_corr[channel-1],self.dac_offset_corr[channel-1])
#print('gain corr: %1.9f offset corr: %1.9f')%(self.dac_gain_corr[channel-1], self.dac_offset_corr[channel-1])
if(print_value):
print('CH%d DAC uncorrected value: 0x%.4X')%(channel, uncorr_value)
print('CH%d DAC corrected value : 0x%.4X')%(channel, value)
self.dac_ch4.set_offset(value)
else:
raise Exception('Unsupported parameter, channel number from 1 to 4')
......@@ -543,8 +539,9 @@ class CFmcAdc100Ms:
# Software trigger
def sw_trig(self):
while('WAIT_TRIG' != self.get_acq_fsm_state()):
print self.get_acq_fsm_state()
time.sleep(.1)
#print self.get_acq_fsm_state()
#time.sleep(.001)
pass
self.fmc_adc_csr.wr_reg(self.R_SW_TRIG, 0xFFFFFFFF)
# Software trigger without wait on WAIT_TRIG state
......
test/fmcadc100m14b4cha/python/test07.py
View file @ 8ef2a6f5
......@@ -38,7 +38,7 @@ ACQ_TIMEOUT = 10
OFFSET_POS = 0x0000
OFFSET_NEG = 0xFFFF
DAC_SET_SLEEP = 0.1 # in [s]
DAC_SET_SLEEP = 0.01 # in [s]
# Expected ADC values
ADC_NEG = -32768.0
......
test/fmcadc100m14b4cha/python/test08.py
View file @ 8ef2a6f5
......@@ -47,9 +47,9 @@ NB_SHOTS = 1
ACQ_LENGTH = 50000 # in samples
ACQ_TIMEOUT = 10
AWG_SET_SLEEP = 0.6
SSR_SET_SLEEP = 0.05
BOX_SET_SLEEP = 0.3
AWG_SET_SLEEP = 0.1
SSR_SET_SLEEP = 0.005
BOX_SET_SLEEP = 0.01
ADC_MID_VALUE = 0
ADC_MID_TOL = 500
......@@ -63,6 +63,16 @@ SW6_TOL = 20000
SW7_TOL = 20000
def load_firmware(default_directory):
print('Load firmware to FPGA')
path_fpga_loader = '../../../gnurabbit/user/fpga_loader';
path_firmware = '../firmwares/spec_fmcadc100m14b4cha_test.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
print firmware_loader + ' ' + bitstream
os.system( firmware_loader + ' ' + bitstream )
time.sleep(2);
def hex2signed(value):
if(value & 0x8000):
return -((~value & 0xFFFF) + 1)
......@@ -83,13 +93,13 @@ def get_channels_mean(fmc, spec_fmc):
fmc.stop_acq()
# Start acquisition
fmc.start_acq()
time.sleep(0.01)
# Trigger
fmc.sw_trig()
# Wait end of acquisition
timeout = 0
time.sleep(0.001)
while('IDLE' != fmc.get_acq_fsm_state()):
time.sleep(.1)
time.sleep(.01)
timeout += 1
if(ACQ_TIMEOUT < timeout):
print "Acquisition timeout. Missing trigger?."
......@@ -124,10 +134,8 @@ def print_current_adc_value(fmc, channel, file):
# Basic operation: Set AWG DC offset and SSRs -> read ADC value, change 1 SSR -> read ADC -> check ADC values difference
# Options: retry -> run the same test several times
# threshold -> minimum number of try to pass the test
def sw_test(box, gen, sine, awg_offset, spec_fmc, fmc, sw, ssr_1, ssr_2, diff_tol):
def sw_test(box, gen, sine, spec_fmc, fmc, sw, ssr_1, ssr_2, diff_tol):
print('\nTesting switch %d\n-------------------------')%sw
set_awg_offset(gen, sine, awg_offset)
print('AWG offset: %1.3fV') % awg_offset
error = 0
for i in range(1,NB_CHANNELS+1):
......@@ -135,10 +143,10 @@ def sw_test(box, gen, sine, awg_offset, spec_fmc, fmc, sw, ssr_1, ssr_2, diff_to
box.select_output_ch(i) # connect AWG to current channel
time.sleep(BOX_SET_SLEEP)
fmc.set_ssr(i,ssr_1)
time.sleep(SSR_SET_SLEEP)
#time.sleep(SSR_SET_SLEEP)
adc_value_before = get_channels_mean(fmc, spec_fmc)[i-1]
fmc.set_ssr(i,ssr_2)
time.sleep(SSR_SET_SLEEP)
#time.sleep(SSR_SET_SLEEP)
adc_value = get_channels_mean(fmc, spec_fmc)[i-1]
diff = adc_value_before-adc_value
print('CH%d ssr=0x%.2X: %6d ssr=0x%.2X: %6d diff:%6d ,min_diff:%6d') % (i, ssr_1, adc_value_before, ssr_2, adc_value, abs(diff), diff_tol)
......@@ -147,7 +155,7 @@ def sw_test(box, gen, sine, awg_offset, spec_fmc, fmc, sw, ssr_1, ssr_2, diff_to
#raise PtsError('SW%d of channel %d is malfunctioning' % (sw, i))
error += 1
fmc.set_ssr(i,0x0)
time.sleep(SSR_SET_SLEEP)
#time.sleep(SSR_SET_SLEEP)
return error
def adc_mid_test(spec_fmc, fmc, tol):
......@@ -157,7 +165,7 @@ def adc_mid_test(spec_fmc, fmc, tol):
for i in range(1,NB_CHANNELS+1):
ssr_1 = 0x0
fmc.set_ssr(i,ssr_1)
time.sleep(SSR_SET_SLEEP)
#time.sleep(SSR_SET_SLEEP)
diff = get_channels_mean(fmc, spec_fmc)[i-1]
print('CH%d ssr=0x%.2X, value:%6d, expected value: %d, diff:%6d, tolerence:%d') % (i, ssr_1, diff, ADC_MID_VALUE, diff, tol)
if(abs(diff) > tol):
......@@ -169,17 +177,8 @@ def adc_mid_test(spec_fmc, fmc, tol):
def main (default_directory='.'):
"""
path_fpga_loader = '../../../gnurabbit/user/fpga_loader';
path_firmware = '../firmwares/spec_fmcadc100m14b4cha.bin';
firmware_loader = os.path.join(default_directory, path_fpga_loader)
bitstream = os.path.join(default_directory, path_firmware)
print firmware_loader + ' ' + bitstream
os.system( firmware_loader + ' ' + bitstream )
time.sleep(2);
"""
# Load firmware
#load_firmware(default_directory)
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
......@@ -227,13 +226,24 @@ def main (default_directory='.'):
error += adc_mid_test(spec_fmc, fmc, ADC_MID_TOL)
error += sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 1, 0x00, 0x01, SW1_TOL)
error += sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 4, 0x01, 0x09, SW4_TOL)
error += sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 5, 0x41, 0x51, SW5_TOL)
error += sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 6, 0x00, 0x60, SW6_TOL)
error += sw_test(box, gen, sine, 0.25, spec_fmc, fmc, 7, 0x01, 0x41, SW7_TOL)
error += sw_test(box, gen, sine, 0.01, spec_fmc, fmc, 2, 0x20, 0x22, SW2_TOL)
error += sw_test(box, gen, sine, 0.01, spec_fmc, fmc, 3, 0x22, 0x26, SW3_TOL)
# Set AWG offset
awg_offset = 0.25
set_awg_offset(gen, sine, awg_offset)
print('AWG offset: %1.3fV') % awg_offset
error += sw_test(box, gen, sine, spec_fmc, fmc, 1, 0x00, 0x01, SW1_TOL)
error += sw_test(box, gen, sine, spec_fmc, fmc, 4, 0x01, 0x09, SW4_TOL)
error += sw_test(box, gen, sine, spec_fmc, fmc, 5, 0x41, 0x51, SW5_TOL)
error += sw_test(box, gen, sine, spec_fmc, fmc, 6, 0x00, 0x60, SW6_TOL)
error += sw_test(box, gen, sine, spec_fmc, fmc, 7, 0x01, 0x41, SW7_TOL)
# Set AWG offset
awg_offset = 0.01
set_awg_offset(gen, sine, awg_offset)
print('AWG offset: %1.3fV') % awg_offset
error += sw_test(box, gen, sine, spec_fmc, fmc, 2, 0x20, 0x22, SW2_TOL)
error += sw_test(box, gen, sine, spec_fmc, fmc, 3, 0x22, 0x26, SW3_TOL)
# Make sure all switches are OFF
for i in range(1,NB_CHANNELS+1):
......
test/fmcadc100m14b4cha/python/test09.py
View file @ 8ef2a6f5
......@@ -41,9 +41,9 @@ AWG_BAUD = 57600
NB_CHANNELS = 4
AWG_SET_SLEEP = 0.6
SSR_SET_SLEEP = 0.05
BOX_SET_SLEEP = 0.3
AWG_SET_SLEEP = 0.2
SSR_SET_SLEEP = 0.005
BOX_SET_SLEEP = 0.01
ACQ_TIMEOUT = 10
......@@ -59,27 +59,28 @@ ACQ_LENGTH = 10000 # in samples
points = [[10E3 , 0 , 1],
[100E3, 0 , 1],
[1E6 , 0 , 1],
[5E6 , 0 , 1],
#[5E6 , 0 , 1],
[10E6 , 0 , 1],
[12E6 , 0 , 1],
[14E6 , 0 , 1],
[16E6 , 0 , 2],
#[12E6 , 0 , 1],
#[14E6 , 0 , 1],
#[16E6 , 0 , 2],
[18E6 , 0 , 2],
[20E6 , 0 , 2],
#[20E6 , 0 , 2],
[22E6 , 0 , 2],
[24E6 , -0.5, 2],
[26E6 , -1 , 2],
[28E6 , -2 , 2],
[30E6 , -3.5, 2],
[32E6 , -4.5, 2],
[34E6 , -6.5, 2],
[36E6 , -8.5, 2],
[38E6 , -10.5, 2],
#[32E6 , -4.5, 2],
#[34E6 , -6.5, 2],
#[36E6 , -8.5, 2],
#[38E6 , -10.5, 2],
[40E6 , -13.5, 2],
[42E6 , -15 , 2],
[44E6 , -17.5, 2],
[46E6 , -20 , 2],
[48E6 , -22.5, 2],
#[42E6 , -15 , 2],
#[44E6 , -17.5, 2],
#[46E6 , -20 , 2],
#[48E6 , -22.5, 2],
#[50E6 , -31 , 3],
[60E6 , -38 , 3],
[80E6 , -66 , 3]]
......@@ -136,13 +137,13 @@ def acq_channels(fmc, spec_fmc):
fmc.stop_acq()
# Start acquisition
fmc.start_acq()
time.sleep(0.01)
# Trigger
fmc.sw_trig()
# Wait end of acquisition
timeout = 0
time.sleep(0.001)
while('IDLE' != fmc.get_acq_fsm_state()):
time.sleep(.1)
time.sleep(.01)
timeout += 1
if(ACQ_TIMEOUT < timeout):
print "Acquisition timeout. Missing trigger?."
......@@ -182,7 +183,7 @@ def show_result_graph(points, ch_att):
def main (default_directory='.'):
# Load firmware
load_firmware(default_directory)
#load_firmware(default_directory)
# Objects declaration
spec = rr.Gennum() # bind to the SPEC board
......
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