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FMC ADC 100M 14b 4cha - Testing
Commit 8f91e0f5 authored by Matthieu Cattin's avatar Matthieu Cattin
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svec many: Change interrupt scheme, now uses two stages (eic + vic).

parent 51a96037
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Showing with 85 additions and 97 deletions
test/fmcadc100m14b4cha/python/fmc_adc_svec.py
View file @ 8f91e0f5
......@@ -14,15 +14,16 @@ import random
import math
# Import specific modules
from sdb import *
from csr import *
from onewire import *
from gn4124 import *
from ds18b20 import *
from i2c import *
from vic import *
# Import register maps
from svec_carrier_csr import *
from svec_irq_controller_regs import *
# Global constants
LED_COLOR = {"OFF":0x0, "GREEN":0x1, "RED":0x2, "ORANGE":0x3}
......@@ -39,10 +40,11 @@ class FmcAdc100mSvecOperationError(Exception):
class CFmcAdc100mSvec:
# Wishbone core base addresses
SDB_ADDR = 0x0
I2C_ADDR = 0x1000
ONEWIRE_ADDR = 0x1100
CSR_ADDR = 0x1200
IRQ_CONTROLLER_ADDR = 0x1300
VIC_ADDR = 0x1300
# Onewire core port
DS18B20_PORT = 0
......@@ -54,11 +56,13 @@ class CFmcAdc100mSvec:
self.bus = bus
# Objects declaration
self.sdb_csr = CCSR(self.bus, self.SDB_ADDR)
self.sdb = CSDB(self.sdb_csr)
self.i2c = COpenCoresI2C(self.bus, self.I2C_ADDR, 249)
self.onewire = COpenCoresOneWire(self.bus, self.ONEWIRE_ADDR, 624, 124)
self.ds18b20 = CDS18B20(self.onewire, self.DS18B20_PORT)
self.csr = CCSR(self.bus, self.CSR_ADDR, CARRIER_CSR)
self.irq_controller = CCSR(self.bus, self.IRQ_CONTROLLER_ADDR, IRQ_CONTROLLER_REGS)
self.vic = CVic(self.bus, self.VIC_ADDR)
# Check if bitstream is properly loaded by reading a register
ct = self.get_carrier_type()
......@@ -68,6 +72,18 @@ class CFmcAdc100mSvec:
# Release the mezzanines software reset
self.set_sw_rst(0,1)
self.set_sw_rst(1,1)
time.sleep(0.001) # gives time for ddr core to calibrates
# Configure VIC
#self.vic.print_regs()
self.vic.set_polarity(1) # output active high
#self.vic.enable_emu_edge(750) # emulate edge sensitive output (pulse width = 750 * 1/sys_clk = 6us)
self.vic.enable_int(0) # enable interrupts from fmc0 eic
self.vic.enable_int(1) # enable interrupts from fmc1 eic
self.vic.enable_module()
self.fmc_eic_addr = []
self.fmc_eic_addr.append(self.vic.get_vector_addr(0))
self.fmc_eic_addr.append(self.vic.get_vector_addr(1))
# TODO
# Check if the expected bitstream loaded
......@@ -82,6 +98,14 @@ class CFmcAdc100mSvec:
raise FmcAdc100mSvecOperationError("Mezzanine in slot 2 not present or PRSNT_M2C_L line faulty.")
#======================================================================
# SDB records
# Dump SDB records
def sdb_dump(self):
self.sdb.dump()
#======================================================================
# Control and status registers (CSR)
......@@ -168,10 +192,12 @@ class CFmcAdc100mSvec:
self.csr.set_field('RST', 'FMC0', 0)
time.sleep(0.001)
self.csr.set_field('RST', 'FMC0', 1)
time.sleep(0.001)
elif slot == 1:
self.csr.set_field('RST', 'FMC1', 0)
time.sleep(0.001)
self.csr.set_field('RST', 'FMC1', 1)
time.sleep(0.001)
else:
raise FmcAdc100mSvecOperationError("Slot number out of range [0:1]")
except CSRDeviceOperationError as e:
......@@ -236,69 +262,16 @@ class CFmcAdc100mSvec:
#======================================================================
# Interrupt controller core
# Print IRQ controller register map
def print_irq_controller_regs(self):
self.irq_controller.print_reg_map()
# Set IRQ enable mask
def set_irq_en_mask(self, mask):
try:
self.irq_controller.set_reg('ENABLE', mask)
self.irq_controller.set_reg('DISABLE', ~mask)
return self.irq_controller.get_reg('MASK')
except CSRDeviceOperationError as e:
raise FmcAdc100mSvecOperationError(e)
# Get IRQ enable mask
def get_irq_en_mask(self):
try:
return self.irq_controller.get_reg('MASK')
except CSRDeviceOperationError as e:
raise FmcAdc100mSvecOperationError(e)
# Returns IRQ status
def get_irq_status(self):
try:
return self.irq_controller.get_reg('STATUS')
except CSRDeviceOperationError as e:
raise FmcAdc100mSvecOperationError(e)
# Vectored Interrupt Controller (VIC)
# Clears interrupt
def clear_interrupt(self, irq):
try:
self.irq_controller.set_reg('STATUS', irq)
return self.irq_controller.get_reg('STATUS')
except CSRDeviceOperationError as e:
raise FmcAdc100mSvecOperationError(e)
# Get current interrupt vector address
def vic_get_current_vector_addr(self):
return self.vic.get_int_vector_addr()
# Set acquisition end interrupt mask
def set_irq_acq_end_mask(self, slot, value):
try:
if slot == 0:
fmc = 'FMC0_ACQ_END'
elif slot == 1:
fmc = 'FMC1_ACQ_END'
else:
raise FmcAdc100mSvecOperationError("Slot number out of range [0:1]")
self.irq_controller.set_field('ENABLE', fmc, value)
self.irq_controller.set_field('DISABLE', fmc, ~value)
return self.irq_controller.get_field('MASK', fmc)
except CSRDeviceOperationError as e:
raise FmcAdc100mSvecOperationError(e)
# Acknowledge current vector
def vic_ack_current_vector(self):
self.vic.int_ack()
# Set trigger interrupt mask
def set_irq_trig_mask(self, slot, value):
try:
if slot == 0:
fmc = 'FMC0_ACQ_TRG'
elif slot == 1:
fmc = 'FMC1_ACQ_TRG'
else:
raise FmcAdc100mSvecOperationError("Slot number out of range [0:1]")
self.irq_controller.set_field('ENABLE', fmc, value)
self.irq_controller.set_field('DISABLE', fmc, ~value)
return self.irq_controller.get_field('MASK', fmc)
except CSRDeviceOperationError as e:
raise FmcAdc100mSvecOperationError(e)
# Get raw interrupt status
def vic_get_raw_status(self):
return self.vic.get_raw_int_status()
test/fmcadc100m14b4cha/python/svec_test01.py
View file @ 8f91e0f5
......@@ -115,6 +115,10 @@ def main (default_directory='.'):
error[i] = "Wrong device mounted on system management I2C bus or soldering issues, address is:0x%.2X expected:0x%.2X" % (periph_addr[0],EEPROM_ADDR)
continue
# Timetag core
fmc[i].print_utc_core_regs()
# LEDs
print('\nBlinking LEDs')
for j in range(3):
......
test/fmcadc100m14b4cha/python/svec_test02.py
View file @ 8f91e0f5
......@@ -55,7 +55,7 @@ def main (default_directory='.'):
print "Initialising device.\n"
# Load FMC ADC firmware
ask = 'N'
ask = ''
while ((ask != "Y") and (ask != "N")) :
ask = raw_input("Do you want to load the firmware: %s? [y,n]"%(FMC_ADC_BITSTREAM))
ask = ask.upper()
......@@ -79,6 +79,11 @@ def main (default_directory='.'):
# Test carrier periherals
print('\n-------------------------------------------------------------')
print('[Carrier]')
# Reset mezzanines
#carrier.sw_rst(0)
#carrier.sw_rst(1)
carrier.print_unique_id()
carrier.print_temp()
......@@ -94,6 +99,9 @@ def main (default_directory='.'):
except FmcAdc100mOperationError as e:
raise PtsCritical("Mezzanine %d init failed, test stopped: %s" % (i+1, e))
carrier.vic.print_regs()
# Test mezzanines peripherals
error = ['','']
for i in range(2):
......@@ -101,53 +109,56 @@ def main (default_directory='.'):
print('\n-------------------------------------------------------------')
print('[FMC slot %d]'%(i+1))
# Disable and clear all interrupts
carrier.set_irq_en_mask(0x0)
ret = carrier.get_irq_status()
carrier.clear_interrupt(ret)
# Enable trigger interrupt
carrier.print_irq_controller_regs()
print('Enable trigger interrupt')
carrier.set_irq_trig_mask(i, 1)
carrier.print_irq_controller_regs()
# Acquisition setup
# hw trig, rising edge, external, sw disable, no delay
print('')
for j in range(100):
print('Enable trigger interrupt')
fmc[i].enable_trig_irq()
fmc[i].print_eic_regs()
fmc[i].set_trig_config(1, 0, 1, 1, 1, 0, 0)
fmc[i].set_pre_trig_samples(500)
fmc[i].set_post_trig_samples(500)
fmc[i].set_shots(1)
fmc[i].stop_acq()
#fmc[i].fmc_adc_csr.print_reg_map()
print "%d: Acquisition FSM state : %s (should be IDLE)" % (j,fmc[i].get_acq_fsm_state())
fmc[i].start_acq()
#time.sleep(3)
time.sleep(0.001)
print "%d: Acquisition FSM state : %s" % (j,fmc[i].get_acq_fsm_state())
print "Wait for trigger."
# Wait from interrupt
# Wait for interrupt
ret = bus.vv_irqwait()
print('[irq wait] irq source reg = 0x%.8X'%ret)
ret = carrier.get_irq_status()
print('irq status = 0x%.8X'%ret)
time.sleep(1)
ret = carrier.clear_interrupt(ret)
print('Clear interrupt, irq status = 0x%.8X'%ret)
#carrier.print_irq_controller_regs()
time.sleep(1)
# Disable trigger interrupt
print('Disable trigger interrupt')
carrier.set_irq_trig_mask(i, 0)
carrier.print_irq_controller_regs()
print('[irq wait] Vector Address Register (VAR) = 0x%.8X'%ret)
print('Check if interrupt is TRIGGER')
irq_src = fmc[i].get_eic_src()
irq_vect = carrier.vic_get_current_vector_addr()
print("FMC%d EIC irq source : %.8X"%(i,irq_src))
print("VIC current vector : 0x%08X"%irq_vect)
if(irq_vect == carrier.fmc_eic_addr[i]):
if(fmc[i].get_trig_status()):
fmc[i].clear_trig_irq()
carrier.vic_ack_current_vector()
print("FMC%d EIC irq source : %.8X"%(i, fmc[i].get_eic_src()))
else:
raise FmcAdc100mSvecOperationError("Bad IRQ source : 0x%08X"%irq_src)
else:
raise FmcAdc100mSvecOperationError("Bad IRQ vector. expected:0x%08X got:0x%08X" %(carrier.fmc_eic_addr[i], irq_vect))
print('Disable trigger interrupt')
fmc[i].disable_trig_irq()
fmc[i].print_eic_regs()
carrier.vic.print_regs()
except FmcAdc100mOperationError as e:
raise PtsError("Mezzanine %d onewire test failed: %s" % (i+1, e))
raise PtsError("Mezzanine %d interrupts test failed: %s" % (i+1, e))
print('')
print "==> End of test%02d" % TEST_NB
......
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