fmc_adc_spec: Add 1ms delay after fmc reset release to let the ddr core finish calibration.

abba8cbd · Matthieu Cattin · fea8c6d4 · abba8cbd
Commit abba8cbd authored Dec 13, 2013 by Matthieu Cattin
Hide whitespace changes
Inline Side-by-side

Showing with 1 addition and 0 deletions

fmc_adc_spec.py test/fmcadc100m14b4cha/python/fmc_adc_spec.py +1 -0

No files found.
--- a/test/fmcadc100m14b4cha/python/fmc_adc_spec.py
+++ b/test/fmcadc100m14b4cha/python/fmc_adc_spec.py
@@ -82,6 +82,7 @@ class CFmcAdc100mSpec:

        # Release the mezzanine software reset
        self.set_sw_rst(1)
+        time.sleep(0.001) # gives time for ddr core to calibrates

        # Configure VIC
        #self.vic.print_regs()