fmc_adc_svec: Fix issues to make svec_test00.py run in a vem front-end.

c8bb3ab5 · Matthieu Cattin · d4e9bf35 · c8bb3ab5 · c8bb3ab5 · c8bb3ab5
Commit c8bb3ab5 authored Jul 16, 2013 by Matthieu Cattin
Showing with 39 additions and 20 deletions

fmc-adc_svec.txt test/fmcadc100m14b4cha/doc/fmc-adc_svec.txt +21 -9

fmc_adc_svec.py test/fmcadc100m14b4cha/python/fmc_adc_svec.py +9 -6

svec_test00.py test/fmcadc100m14b4cha/python/svec_test00.py +9 -5

No files found.
--- a/test/fmcadc100m14b4cha/doc/fmc-adc_svec.txt
+++ b/test/fmcadc100m14b4cha/doc/fmc-adc_svec.txt
 Running fmc-adc test on SVEC carrier requires:
 - vmebus driver
- vmeio driver*
+- vmeio driver [1]
- vv_lib (.so + .py)*
+- vv_lib (.so + .py) [1]
+- python 2.7 [1]
+- ctypes [1]
 - rr2vv.py VME class extension (in dir common/)
-* Taken from Julian's pts:
+[1] Taken from Julian's pts:
-  /acc/src/dsc/drivers/cohtdrep/lewis/pts/
+    /acc/src/dsc/drivers/cohtdrep/lewis/pts/
-  or
+    or
-  http://www.ohwr.org/projects/pts/repository/revisions/master/show/test/svec/svec_pts_structure/
+    http://www.ohwr.org/projects/pts/repository/revisions/master/show/test/svec/svec_pts_structure/
-    -> vmeio driver:    src/driver
+       -> vmeio driver:    src/driver
-    -> vv_lib C source: src/lib
+       -> vv_lib C source: src/lib
-    -> vv_lib.py:       ubuntu/pts/pyts
+       -> vv_lib.py:       ubuntu/pts/pyts
+       -> python 2.7:      ubuntu/pts/2.7.3
+       -> ctypes:          ubuntu/pts/ctypes
+    In install.VMEIO:
+       -> vme1 = slot * 0x80000 (CSR space)
+       -> vme2 can be freely mapped, not dependent on slot (access to Wishbone bus address space)
+-> Create a symlink to python 2.7 in ubuntu/pts/2.7.3 in the folder containing tests.py
+-> Put #! ./python on the begining of each test file
--- a/test/fmcadc100m14b4cha/python/fmc_adc_svec.py
+++ b/test/fmcadc100m14b4cha/python/fmc_adc_svec.py
@@ -18,6 +18,7 @@ from csr import *
 from onewire import *
 from gn4124 import *
 from ds18b20 import *
+from i2c import *
 # Import register maps
 from svec_carrier_csr import *
@@ -78,8 +79,10 @@ class CFmcAdc100mSvec:
        #    raise FmcAdc100mSvecOperationError("Wrong bitsream. Excpect:0x%08X, Read:0x%08X" % (bs_type, bs))
        # Ckeck if a mezzanine is present
-        if(not self.get_fmc_presence()):
+        if(not self.get_fmc_presence(0)):
-            raise FmcAdc100mSvecOperationError("Mezzanine not present or PRSNT_M2C_L line faulty.")
+            raise FmcAdc100mSvecOperationError("Mezzanine in slot 1 not present or PRSNT_M2C_L line faulty.")
+        if(not self.get_fmc_presence(1)):
+            raise FmcAdc100mSvecOperationError("Mezzanine in slot 2 not present or PRSNT_M2C_L line faulty.")
    #======================================================================
@@ -123,7 +126,7 @@ class CFmcAdc100mSvec:
        try:
            if slot == 0:
                fmc = 'FMC0_PRES'
-            else if slot == 1:
+            elif slot == 1:
                fmc = 'FMC1_PRES'
            else:
                raise FmcAdc100mSvecOperationError("Slot number out of range [0:1]")
@@ -143,7 +146,7 @@ class CFmcAdc100mSvec:
        try:
            if ddr == 0:
                val = 'DDR0_CAL_DONE'
-            else if ddr == 1:
+            elif ddr == 1:
                val = 'DDR1_CAL_DONE'
            else:
                raise FmcAdc100mSvecOperationError("DDR number out of range [0:1]")
@@ -252,7 +255,7 @@ class CFmcAdc100mSvec:
        try:
            if slot == 0:
                fmc = 'FMC0_ACQ_END'
-            else if slot == 1:
+            elif slot == 1:
                fmc = 'FMC1_ACQ_END'
            else:
                raise FmcAdc100mSvecOperationError("Slot number out of range [0:1]")
@@ -265,7 +268,7 @@ class CFmcAdc100mSvec:
        try:
            if slot == 0:
                fmc = 'FMC0_ACQ_TRG'
-            else if slot == 1:
+            elif slot == 1:
                fmc = 'FMC1_ACQ_TRG'
            else:
                raise FmcAdc100mSvecOperationError("Slot number out of range [0:1]")

--- a/test/fmcadc100m14b4cha/python/svec_test00.py
+++ b/test/fmcadc100m14b4cha/python/svec_test00.py
-#!   /usr/bin/env   python
+#!   ./python
 #    coding: utf8
 # Copyright CERN, 2013
@@ -14,9 +14,11 @@ import os
 # Add common modules and libraries location to path
 sys.path.append('../../../')
 sys.path.append('../../../common/')
+sys.path.append('../../../../svec_pts/ubuntu/pts/pyts/')
 # Import common modules
 from ptsexcept import *
+from rr2vv import *
 # Import specific modules
 from fmc_adc_svec import *
@@ -31,7 +33,7 @@ def main (default_directory='.'):
    # Constants declaration
    LUN = 0
    TEST_NB = 0
-    FMC_ADC_BITSTREAM = '../firmwares/svec_fmcadc100m14b4cha.bin'
+    FMC_ADC_BITSTREAM = '../../../../../firmwares/svec_fmcadc100m14b4cha.bin'
    FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
    EXPECTED_BITSTREAM_TYPE = 0x0
@@ -48,13 +50,13 @@ def main (default_directory='.'):
    # Load FMC ADC firmware
    print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM
-    bus.vv_load(FMC_ADC_BITSTREAM, 1)
+    ret = bus.vv_load(FMC_ADC_BITSTREAM, 1)
    time.sleep(2)
    # Carrier object declaration (SPEC board specific part)
    try:
-        carrier = CFmcAdc100mSpec(bus, EXPECTED_BITSTREAM_TYPE)
+        carrier = CFmcAdc100mSvec(bus, EXPECTED_BITSTREAM_TYPE)
-    except FmcAdc100mSpecOperationError as e:
+    except FmcAdc100mSvecOperationError as e:
        raise PtsCritical("Carrier init failed, test stopped: %s" % e)
    # Print bitsteam type
@@ -62,6 +64,8 @@ def main (default_directory='.'):
    print('Carrier type:0x%.8X') % carrier_type
    if carrier_type == 2:
        print "Carrier type OK.\n"
+    else:
+        raise PtsCritical("Unexpected carrier type!\n")
    # Print carrier CSR registers
    carrier.print_csr()