10-10-2011: Feedback from fabricator improves design
added by Erik van der Bij on 2011-10-10 13:36:40.995797
INCAA, the company who will make the first series production of the ADC
card, reviewed the design before production. They found a problem in the
schematics (the 6 Volt rail could be 6.2 Volt) and raised an issue about
the PCB layout (thermal brakes too large). These issues were handled and
also some minor improvements that we had still had in the
are now included in the V5 design. INCAA will produce 40 of those boards
for delivery in early January 2012.
20-09-2011: Production of 40 cards starts
added by Erik van der Bij on 2011-09-20 17:01:01.679001
After a succesful price enquiry, CERN has decided to use the company
INCAA Computers in The Netherlands to
produce 40 FMC ADC cards. They will be delivered in January 2012. CERN
needs to finalise the production test software still before shipping a
test bench to INCAA.
This card is the second CERN Open Hardware product that will be produced
in quantity by industry. The first one was the SPEC FMC
carrier that is being produced
by Seven Solutions from Spain.
Note that according to the CERN Open Hardware
Licence any company may
produce these designs.
29-03-2011: V2 works on the SPEC
added by Anonymous on 2011-03-29 09:46:37.231185
A first version of the firmware (single shot) has been tested on the
SPEC along with a python test program.
The acquired ADC data are read from DDR3 via
25-03-2011: ADC card usable for radio telescopes?
added by Erik van der Bij on 2011-03-25 08:58:06.268136
added by Erik van der Bij on 2011-01-07 10:51:21.762071
Ten V2 boards have arrived and are ready for testing.
25-10-2010: OHR design possibly used for Hadron therapy
added by Erik van der Bij on 2010-10-25 11:40:40.538078
One of the prototype FMC ADC cards has been donated to the non-profit
institution TERA. The primary objective of the TERA Foundation is the
development of radiotherapy techniques based on the use of hadron
particles. The ADC card, that is designed under the Open Hardware
paradigm, fulfills the needs of TERA and may in the future be used to
read-out detectors used in hadron therapies.
25-10-2010: Ten V2 boards will be produced
added by Erik van der Bij on 2010-10-25 11:29:03.639714
After extensive testing of the prototype card (V1), several improvements
have been made. This culminated in the V2 version of which ten will be
produced, to be available on a December timescale.
08-09-2010: Testing continues
added by Erik van der Bij on 2010-09-08 17:44:48.853804
The ADC board is extensively being tested. The harmonics problem seen
was actually caused by the signal generator used. The I2C bus is tested
and accessing the EEPROM memory, setting the sampling frequency and
making temperature measurements are now possible. There appeared an
issue with linearity in the 30-90 kHz region caused by offset
compensation circuit. This issue, which is repeatable by simulation, is
4-08-2010: The board is working
added by Erik van der Bij on 2010-08-04 09:41:59.143624
Since mid July we have one board plugged in on Xilinx development kit
and powered. Two channels are working as limited by Xilinx development
kit clock connections (we'll change our FMC connections on a V2 to cope
with this). Some changes are needed to solve thermal problems. The ENOB
& SNR are measured: >11 bits in all ranges. However, there seem to be
still a problem with the harmonic distortion that is with -60dB somewhat
higher than expected.
28-05-2010: The board is a beauty!
added by Erik van der Bij on 2010-05-28 17:45:37.285852
For bringing the SMC connectors I passed by the assembly workshop and
had a chance to have a look at the three assembled PCBs. The boards look
really beautiful with the four rows of black Panasonic switches clearly
visible. With the gold-plated SMC connectors combined with the brushed
aluminium front-plates they will look like a form of high-tech art!
3-05-2010: PCIe System Functional Spec process started
added by Javier Serrano on 2010-05-03 14:41:37.275617
added by Erik van der Bij on 2010-04-12 16:42:47.870334
Twelve PCBs are ordered. Three will be mounted for prototyping.
Components are ordered for ten.
24-03-2010 PCB layout review held
added by Erik van der Bij on 2010-03-24 17:18:25.823471
A very useful review (Review24032010) has been held
that introduced several improvements. Overall the layout was already
fine and would have given a working board. Certain of the suggested
changes will make the layout better, likely improving SNR and EMC
features. Other changes will improve the production process or are just
19-03-2010 PCB layout done. Review planned
added by Erik van der Bij on 2010-03-19 14:44:59.983696
PCB review planned for 24 March 2010.
2-03-2010 Schematics review held
added by Erik van der Bij on 2010-03-02 15:54:07.139008
The schematics review (Review02032010) revealed some
serious problems and signalled other issues that will make the design
more robust. Other comments will make that the documentation will be
improved. The changes will be implemented before finalising the PCB
24-02-2010 Draft PCB layout done. Review planned
added by Erik van der Bij on 2010-02-24 12:16:46.513020
Draft PCB layout done. Design document being written. Design review
planned for 2 March. See documents
10-02-2010 New Design made
added by Anonymous on 2010-02-10 22:00:56.709734
New design made with 3 input ranges and programmable offset. Need to
finalise local clock circuit before PCB layout can start.
2-12-2009 Project on hold
added by Anonymous on 2009-12-02 22:00:25.699073
SNR level too high with PGA. User need is to have programmable offset
instead of programmable gain (S. Deghaye).