System specifications
Functional specifications for the PCIe carrier version
Parameter | Value |
Max. sample rate | 100 MSPS |
Available sampling rates | Programmable 16-bit divider off 100 MHz |
Sampling word width | 14 bits |
ENOB | > 11 bits |
Channels | 4 |
Connectors | 4 x LEMO for signals, 1 x LEMO for trigger |
Analog bandwidth | 30 MHz, DC-coupled |
Input impedance | 1kOhm / 50 Ohm - software selectable |
Gain steps | /-50mV,/-0.5V, +/-5V for full scale |
Offset correction range | +/- 5V for every input voltage range |
Max. gain error | +/- 1% |
Clock [link](https://www.ohwr.org/project/fmc-adc-100m14b4cha/blob/master | )External (from dedicated FMC connector pins) or from programmed on-board generator (fixed or tracking external reference) |
Trigger | External (LVTTL) or internal with programmable slope, level and delay. Multi-trigger support with programmable hold-off. |
Sampling memory | 32 MSamples per channel |
Card to host sample transfer | Chained DMA engine over PCIe |
Data transfer rate over PCIe | > 50 MB/s |
Interrupts | Trigger, end of shot, temperature alarm |
Time stamping | UTC for trigger and START/STOP commands |
Technical specifications for the PCIe carrier version
See Document.
This document has been used as a basis for hdl development. But be
careful, the final implementation isn't fully compliant to this
document.
For accurate information on hdl implementation, please refer to the preliminary documentation (in Tex).
Memory map
BAR0 (1MB):*
Wishbone Cores | ||||
---|---|---|---|---|
* SDB version, offset (bytes) * | Description | Peripherals | Internal mapping | Status |
0x00000 | SDB header | - | SDB specification | In work |
0x01000 | DMA Controller | DMA config. and status | Registers | Available |
0x01100 | Carrier SPI master | DAC control (driving VCXO) | Registers | |
0x01200 | Carrier 1-wire master | Thermometer + unique ID DS18B20 | Registers | Available |
0x01300 | Carrier CSR | PLL, DDR status, LED control, etc... | Registers | Available |
0x01400 | UTC core | Trigger, acq time-tags | Registers | Available |
0x01500 | Interrupt controller | Enable mask, irq source | Registers | Available |
0x01600 | Mezzanine system management I2C master | 0x50) EEPROM (FMC standard) 24AA64T | Registers | Available |
0x01700 | Mezzanine SPI master | 0) ADC LTC2174, 1->4) DAC (for DC offset) MAX5442 | Registers | Available |
0x01800 | Mezzanine I2C master | 0x55) Oscillator (sampling clock) Si570 | Registers | Available |
0x01900 | Mezzanine ADC core CSR | ACQ state machine, input range, trigger, etc... | Registers | Available |
0x01A00 | Mezzanine 1-wire master | Thermometer + unique ID DS18B20 | Registers | Available |
HDL development Project Status
Date | Event |
25-04-2010 | Start working on project. |
04-05-2010 | Preliminary functional specs ready for discussion. |
23-09-2010 | Technical specification ready and usable for implementation of HDL development. |
12-03-2013 | Release V1.0 of the fmc-adc gateware is available. |
Maciej Firmiarz, Matthieu Cattin, Javier Serrano - 18 March 2013