Skip to content

F
fmc dac 600m 12b 1cha dds - Testing
Commit ad87833c authored by Marek Gumiński's avatar Marek Gumiński
Browse files
Options

Fixed submodules versions. 

Modified HDL so that PLL connectec to CLK2 may be reset. Test03 should work reliably.
Added some diagnostics and error handling in acq.sh.
parent 99babf85
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 472 additions and 326 deletions
etherbone-core @ 2fcdbb3e
Subproject commit c1e676dc9d35028910c50431d70328e522396c89
Subproject commit 2fcdbb3e2a141cabd45eb2c9debd49b9c0b56af9
general-cores @ 12c045eb
Subproject commit 97bc71975252b32cf8a47ba895f7010734f015e5
Subproject commit 12c045ebd49033d17f68b84cb6dec73a144f78cf
gn4124-core @ 5fd1a8b1
Subproject commit ffea5479190c09938cbba9b7076953c5c41645f3
Subproject commit 5fd1a8b14063464eef714be14d79d36550080cb4
wr-cores @ 87ad0d56
Subproject commit 598a2f6ccbf1ac937ff589c0797cd2a487306efe
Subproject commit 87ad0d563bae8eaf1ce5fddc646262d5bc234544
gateware/rtl/dds_core.vhd
View file @ ad87833c
......@@ -83,6 +83,8 @@ entity dds_core is
dac_dds_load_o : out std_logic;
dac_dds_data_o : out std_logic_vector( 16-1 downto 0 );
pll_clk2_lock_i : in std_logic;
pll_clk2_rst_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_sda_i : in std_logic;
......@@ -402,6 +404,8 @@ architecture behavioral of dds_core is
signal adc_trigger : std_logic;
signal rst_freq_meters : std_logic;
signal rst_n_freq_meters : std_logic;
function f_signed_multiply(a : std_logic_vector; b : std_logic_vector; shift : integer; output_length : integer)
......@@ -804,8 +808,13 @@ begin -- behavioral
);
pll_clk2_rst_o <= regs_out.fpgapll_clk2_ctrl_rst_o;
regs_in_local.fpgapll_clk2_stat_lock_i <= pll_clk2_lock_i;
swrst <= regs_out.rstr_sw_rst_o or (not rst_n_i);
-- rst_freq_meters <= regs_out.rstr_freq_res_o or (not rst_n_i);
-- rst_n_freq_meters <= not rst_freq_meters;
swrst_o <= swrst;
swrst_n <= not swrst;
fpll_reset_o <= regs_out.rstr_pll_rst_o or (not rst_n_i);
......
gateware/rtl/dds_wb_slave.vhd
View file @ ad87833c
This diff is collapsed.
gateware/rtl/dds_wb_slave.wb
View file @ ad87833c
......@@ -356,6 +356,16 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "Freqency meters reset";
prefix = "FREQ_RES";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......@@ -643,6 +653,32 @@ peripheral {
};
};
reg {
name = "FPGA PLL CLK2 Control";
prefix = "FPGAPLL_CLK2_CTRL";
field {
name = "Reset";
prefix = "RST";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
};
reg {
name = "FPGA PLL CLK2 Status";
prefix = "FPGAPLL_CLK2_STAT";
field {
name = "Lock detect";
prefix = "LOCK";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
type = BIT;
};
};
reg {
name = "FPGA Frequency measurement of frequecy from DAC";
prefix = "Clk0";
......
gateware/rtl/dds_wbgen2_pkg.vhd
View file @ ad87833c
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for DDS RF distribution WB Slave
---------------------------------------------------------------------------------------
-- File : /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
-- Created : Tue Aug 11 14:03:44 2015
-- File : /home/gumas/tmp/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/tmp/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
-- Created : Tue Feb 2 09:40:18 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/tmp/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -45,6 +45,7 @@ package dds_wbgen2_pkg is
pi_data_i : std_logic_vector(15 downto 0);
gw_id_i : std_logic_vector(31 downto 0);
fpgactrl_mainpll_i : std_logic;
fpgapll_clk2_stat_lock_i : std_logic;
clk0_freq_i : std_logic_vector(31 downto 0);
clk1_freq_i : std_logic_vector(31 downto 0);
clk2_freq_i : std_logic_vector(31 downto 0);
......@@ -79,6 +80,7 @@ package dds_wbgen2_pkg is
pi_data_i => (others => '0'),
gw_id_i => (others => '0'),
fpgactrl_mainpll_i => '0',
fpgapll_clk2_stat_lock_i => '0',
clk0_freq_i => (others => '0'),
clk1_freq_i => (others => '0'),
clk2_freq_i => (others => '0'),
......@@ -121,6 +123,7 @@ package dds_wbgen2_pkg is
gain_o : std_logic_vector(15 downto 0);
rstr_pll_rst_o : std_logic;
rstr_sw_rst_o : std_logic;
rstr_freq_res_o : std_logic;
i2cr_scl_out_o : std_logic;
i2cr_sda_out_o : std_logic;
pir_kp_o : std_logic_vector(15 downto 0);
......@@ -137,6 +140,7 @@ package dds_wbgen2_pkg is
test_comm_reg_o : std_logic_vector(15 downto 0);
test_comm_led_r_o : std_logic;
test_comm_led_g_o : std_logic;
fpgapll_clk2_ctrl_rst_o : std_logic;
oscdac_data_o : std_logic_vector(15 downto 0);
oscdac_load_o : std_logic;
adcinterface_source_o : std_logic;
......@@ -178,6 +182,7 @@ package dds_wbgen2_pkg is
gain_o => (others => '0'),
rstr_pll_rst_o => '0',
rstr_sw_rst_o => '0',
rstr_freq_res_o => '0',
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0',
pir_kp_o => (others => '0'),
......@@ -194,6 +199,7 @@ package dds_wbgen2_pkg is
test_comm_reg_o => (others => '0'),
test_comm_led_r_o => '0',
test_comm_led_g_o => '0',
fpgapll_clk2_ctrl_rst_o => '0',
oscdac_data_o => (others => '0'),
oscdac_load_o => '0',
adcinterface_source_o => '0',
......@@ -256,6 +262,7 @@ tmp.pi_wr_req_i := f_x_to_zero(left.pi_wr_req_i) or f_x_to_zero(right.pi_wr_req_
tmp.pi_data_i := f_x_to_zero(left.pi_data_i) or f_x_to_zero(right.pi_data_i);
tmp.gw_id_i := f_x_to_zero(left.gw_id_i) or f_x_to_zero(right.gw_id_i);
tmp.fpgactrl_mainpll_i := f_x_to_zero(left.fpgactrl_mainpll_i) or f_x_to_zero(right.fpgactrl_mainpll_i);
tmp.fpgapll_clk2_stat_lock_i := f_x_to_zero(left.fpgapll_clk2_stat_lock_i) or f_x_to_zero(right.fpgapll_clk2_stat_lock_i);
tmp.clk0_freq_i := f_x_to_zero(left.clk0_freq_i) or f_x_to_zero(right.clk0_freq_i);
tmp.clk1_freq_i := f_x_to_zero(left.clk1_freq_i) or f_x_to_zero(right.clk1_freq_i);
tmp.clk2_freq_i := f_x_to_zero(left.clk2_freq_i) or f_x_to_zero(right.clk2_freq_i);
......
gateware/top/spec_top.ucf
View file @ ad87833c
......@@ -519,9 +519,11 @@ NET "clk_125m_gtp_n_i" TNM_NET = "clk_125m_gtp_n_i";
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50 %;
NET "dds_vcxo_clk_p_i" TNM_NET = "dds_vcxo_clk_p_i";
TIMESPEC TS_dds_vcxo_clk_p_i = PERIOD "dds_vcxo_clk_p_i" 8 ns HIGH 50 %;
# TIMESPEC TS_dds_vcxo_clk_p_i = PERIOD "dds_vcxo_clk_p_i" 8 ns HIGH 50 %;
TIMESPEC TS_dds_vcxo_clk_p_i = PERIOD "dds_vcxo_clk_p_i" 20 ns HIGH 50 %;
NET "dds_vcxo_clk_n_i" TNM_NET = "dds_vcxo_clk_n_i";
TIMESPEC TS_dds_vcxo_clk_n_i = PERIOD "dds_vcxo_clk_n_i" 8 ns HIGH 50 %;
# TIMESPEC TS_dds_vcxo_clk_n_i = PERIOD "dds_vcxo_clk_n_i" 8 ns HIGH 50 %;
TIMESPEC TS_dds_vcxo_clk_n_i = PERIOD "dds_vcxo_clk_n_i" 20 ns HIGH 50 %;
......
gateware/top/spec_top.vhd
View file @ ad87833c
......@@ -192,6 +192,7 @@ entity spec_top is
dds_adc_sdi_o : out std_logic;
-- Silabs clock gen control
-- dds_si57x_oe_o : out std_logic;
-- dds_si57x_sda_b : inout std_logic;
......@@ -361,6 +362,7 @@ architecture rtl of spec_top is
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr : std_logic;
signal cnt_led : unsigned( 31 downto 0);
component dds_core
port (
......@@ -423,6 +425,8 @@ architecture rtl of spec_top is
eeprom_scl_o : out std_logic;
eeprom_sda_o : out std_logic;
pll_clk2_lock_i : in std_logic;
pll_clk2_rst_o : out std_logic;
-- si57x_oe_o : out std_logic;
-- si57x_sda_b : inout std_logic;
......@@ -504,15 +508,12 @@ architecture rtl of spec_top is
signal pllout_clk_rf : std_logic;
signal clk_rf : std_logic;
signal pll_clk2_lock : std_logic;
signal pll_clk2_rst : std_logic;
begin -- rtl
-- dds_pll_vcxo_function_o <= '1';
-- dds_pll_vcxo_cs_n_o <= '1';
-- new on dds v2
delay_data_out <= dds_delay_data;
delay_value_out <= dds_delay_value;
......@@ -594,18 +595,6 @@ begin -- rtl
IB => trig_n_in -- Diff_n buffer input (connect directly to top-level port)
);
-- reseting:
-- 1) U_Reset_Generator generates reset some time after dmtd clk (allways running) locks
-- 2) After spec_reset_n go inactive U_AD9516_bootstrap program external PLL and sets pll_nit_done
-- 3) pll_init_done resets internal PLL cmp_sys_clk_pll
-- 4) cmp_sys_clk_pll tries to lock on clock from external d3s pll
-- 5) When done fpll_locked is risen
-- 6) Some delay is added (p_gen_reset)
-- 7) local_reset_n is lowered
-- 8) wrcore (and others) should start running
-- not a good solution
-- board will be dead unless powered on with correct setup
U_Reset_Generator : spec_reset_gen
port map (
......@@ -614,23 +603,7 @@ begin -- rtl
rst_button_n_a_i => button1_i,
rst_n_o => spec_reset_n);
-- this core loads pll chip configuration
-- configuration over SPI
-- dont know what configuration is it
-- U_AD9516_bootstrap : pll_init
-- generic map (
-- g_simulation => g_simulation)
-- port map (
-- clk_i => clk_dmtd,
-- rst_n_i => spec_reset_n,
-- done_o => pll_init_done,
-- cs_n_o => dds_pll_sys_cs_n,
-- mosi_o => dds_pll_sdio,
-- sck_o => dds_pll_sclk);
-- dds_pll_sys_sync_n <= '1';
-- dds_pll_sys_reset_n <= '1';
pll_init_done <= spec_reset_n;
dds_pll_sys_cs_n_o <= dds_pll_sys_cs_n;
......@@ -743,41 +716,27 @@ begin -- rtl
CLKIN => clk_20m_vcxo_buf);
cmp_rf_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_MULT => 20,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 125 MHz
CLKOUT0_DIVIDE => 20,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_rf,
CLKOUT0 => pllout_clk_rf,
CLKOUT1 => open,
CLKOUT2 => open,
-- CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
LOCKED => pll_clk2_lock,
RST => pll_clk2_rst,
CLKFBIN => pllout_clk_fb_rf,
CLKIN => dds_vcxo_clk);
cmp_clk_rf_buf : BUFG
port map (
O => clk_rf,
......@@ -793,12 +752,6 @@ begin -- rtl
O => clk_sys,
I => pllout_clk_sys);
-- cmp_clk_dds_buf : BUFG
-- port map (
-- O => clk_dds,
-- I => pllout_clk_dds);
cmp_clk_ref_buf : BUFG
port map (
O => clk_ref,
......@@ -903,7 +856,6 @@ begin -- rtl
clk_sys_i => clk_sys,
clk_dds_i => clk_dds,
clk_ref_i => clk_ref,
-- clk_rf_i => dds_vcxo_clk,
clk_rf_i => clk_rf,
clk_dac_i => clk_dac,
rst_n_i => local_reset_n,
......@@ -959,6 +911,8 @@ begin -- rtl
delay_len_o => dds_delay_len,
trigger_i => dds_trigger,
pll_clk2_lock_i => pll_clk2_lock,
pll_clk2_rst_o => pll_clk2_rst,
slave_i => cnx_master_out(c_SLAVE_DDS_CORE),
slave_o => cnx_master_in(c_SLAVE_DDS_CORE),
......@@ -973,6 +927,7 @@ begin -- rtl
-- si57x_oe_o => dds_si57x_oe_o
);
led_red <= leds( 1 );
led_green <= leds( 0 );
......@@ -1014,128 +969,6 @@ begin -- rtl
tm_utc <= ( others => '0' );
-- U_WR_CORE : xwr_core
-- generic map (
-- g_simulation => g_simulation,
-- g_phys_uart => true,
-- g_virtual_uart => true,
-- g_with_external_clock_input => true,
-- g_aux_clks => 0,
-- g_ep_rxbuf_size => 1024,
-- g_tx_runt_padding => true,
-- g_dpram_initf => "",
-- g_dpram_size => 131072/4,
-- g_interface_mode => PIPELINED,
-- g_address_granularity => BYTE)
-- port map (
-- clk_sys_i => clk_sys,
-- clk_dmtd_i => clk_dmtd,
-- clk_ref_i => clk_ref,
-- -- rst_n_i => local_reset_n,
-- rst_n_i => wr_reset_n,
-- dac_hpll_load_p1_o => dac_hpll_load_p1,
-- dac_hpll_data_o => dac_hpll_data,
-- dac_dpll_load_p1_o => dac_dpll_load_p1,
-- dac_dpll_data_o => dac_dpll_data,
-- phy_ref_clk_i => clk_ref,
-- phy_tx_data_o => phy_tx_data,
-- phy_tx_k_o => phy_tx_k,
-- phy_tx_disparity_i => phy_tx_disparity,
-- phy_tx_enc_err_i => phy_tx_enc_err,
-- phy_rx_data_i => phy_rx_data,
-- phy_rx_rbclk_i => phy_rx_rbclk,
-- phy_rx_k_i => phy_rx_k,
-- phy_rx_enc_err_i => phy_rx_enc_err,
-- phy_rx_bitslide_i => phy_rx_bitslide,
-- phy_rst_o => phy_rst,
-- phy_loopen_o => phy_loopen,
-- led_act_o => LED_RED,
-- led_link_o => LED_GREEN,
-- scl_o => wrc_scl_out,
-- scl_i => wrc_scl_in,
-- sda_o => wrc_sda_out,
-- sda_i => wrc_sda_in,
-- sfp_scl_o => sfp_scl_out,
-- sfp_scl_i => sfp_scl_in,
-- sfp_sda_o => sfp_sda_out,
-- sfp_sda_i => sfp_sda_in,
-- sfp_det_i => sfp_mod_def0_b,
-- uart_rxd_i => uart_rxd_i,
-- uart_txd_o => uart_txd_o,
-- owr_en_o => wrc_owr_en,
-- owr_i => wrc_owr_in,
-- slave_i => cnx_master_out(c_SLAVE_WRCORE),
-- slave_o => cnx_master_in(c_SLAVE_WRCORE),
-- wrf_src_o => wrc_true_src_out,
-- wrf_src_i => wrc_true_src_in,
-- wrf_snk_o => wrc_true_snk_out,
-- wrf_snk_i => wrc_true_snk_in,
-- tm_link_up_o => tm_link_up,
-- tm_time_valid_o => tm_time_valid,
-- tm_tai_o => tm_utc,
-- tm_cycles_o => tm_cycles,
-- btn1_i => '1',
-- btn2_i => '1',
-- rst_aux_n_o => open,
-- pps_p_o => pps
-- );
-- U_GTP : wr_gtp_phy_spartan6
-- generic map (
-- g_simulation => g_simulation,
-- g_enable_ch0 => 0,
-- g_enable_ch1 => 1)
-- port map (
-- gtp_clk_i => clk_ref,
-- ch0_ref_clk_i => clk_ref,
-- ch0_tx_data_i => x"00",
-- ch0_tx_k_i => '0',
-- ch0_tx_disparity_o => open,
-- ch0_tx_enc_err_o => open,
-- ch0_rx_rbclk_o => open,
-- ch0_rx_data_o => open,
-- ch0_rx_k_o => open,
-- ch0_rx_enc_err_o => open,
-- ch0_rx_bitslide_o => open,
-- ch0_rst_i => '1',
-- ch0_loopen_i => '0',
-- ch1_ref_clk_i => clk_ref,
-- ch1_tx_data_i => phy_tx_data,
-- ch1_tx_k_i => phy_tx_k,
-- ch1_tx_disparity_o => phy_tx_disparity,
-- ch1_tx_enc_err_o => phy_tx_enc_err,
-- ch1_rx_data_o => phy_rx_data,
-- ch1_rx_rbclk_o => phy_rx_rbclk,
-- ch1_rx_k_o => phy_rx_k,
-- ch1_rx_enc_err_o => phy_rx_enc_err,
-- ch1_rx_bitslide_o => phy_rx_bitslide,
-- ch1_rst_i => phy_rst,
-- ch1_loopen_i => '0', --phy_loopen,
-- pad_txn0_o => open,
-- pad_txp0_o => open,
-- pad_rxn0_i => '0',
-- pad_rxp0_i => '0',
-- pad_txn1_o => sfp_txn_o,
-- pad_txp1_o => sfp_txp_o,
-- pad_rxn1_i => sfp_rxn_i,
-- pad_rxp1_i => sfp_rxp_i);
U_DAC_ARB : spec_serial_dac_arb
generic map (
......@@ -1257,7 +1090,6 @@ begin -- rtl
cs_data( 8 ) <= dac_din;
cs_data( 9 ) <= dac_cs1_n;
cs_data( 10 ) <= dac_cs2_n;
cs_data( 11 ) <= phy_rst;
cs_data( 12 ) <= wr_reset_n;
......
python/acq.sh
View file @ ad87833c
#!/bin/bash
(
prg=$0
if [ ! -e "$prg" ]; then
case $prg in
(*/*) exit 1;;
(*) prg=$(command -v -- "$prg") || exit;;
esac
fi
dir=$(
cd -P -- "$(dirname -- "$prg")" && pwd -P
) || exit
prg=$dir/$(basename -- "$prg") || exit
top=`echo "$prg" | sed 's/fmcdac600m12b1chadds.*/fmcdac600m12b1chadds\//'`
# echo $top
export PATH="\
$top/software/fmc-adc-100m14b4cha-sw/tools:\
$top/software/fmc-adc-100m14b4cha-sw/libtools:\
$PATH"
# echo $PATH
rm /tmp/data.bin
# echo "1"
tmp=`printf "%02x00" $3`
adcpath="/sys/bus/zio/devices/adc-100m14b-$tmp/"
echo 1 > "${adcpath}/cset0/trigger/sw-trg-enable"
# echo 1 > /sys/bus/zio/devices/adc-100m14b-0200/cset0/trigger/sw-trg-enable
# echo "2"
sleep 1
# echo "3"
fald-acq -b 0 -a $1 -r $2 -B /tmp/data.bin "0x${tmp}" &
# echo "4"
sleep 2
# echo "5"
echo 1 > "${adcpath}/cset0/trigger/sw-trg-fire"
# echo 1 > /sys/bus/zio/devices/adc-100m14b-0200/cset0/trigger/sw-trg-fire
# echo "6"
wait
# echo "7"
###########################################
######### prepare environment #############
###########################################
#finding top directory location
prg=$0
if [ ! -e "$prg" ]; then
case $prg in
(*/*) exit 1;;
(*) prg=$(command -v -- "$prg") || exit;;
esac
fi
dir=$(
cd -P -- "$(dirname -- "$prg")" && pwd -P
) || exit
prg=$dir/$(basename -- "$prg") || exit
# top directory location stored in variable
top=`echo "$prg" | sed 's/fmcdac600m12b1chadds.*/fmcdac600m12b1chadds\//'`
# format adc identifier
id=`printf "%02x00" $3`
# prepare adc interface path
adcpath="/sys/bus/zio/devices/adc-100m14b-$id/"
###########################################
############# clean up ##################
###########################################
# kill acquisition program
pid=`ps aux | awk '$11 == "fald-acq" {print $2}'`
if [ -n "$pid" ]
then
echo "killing: $pid"
kill -9 $pid
fi
# then data buffer
rm -f /tmp/data.bin
###########################################
############# acquire data ################
###########################################
# configure software trigger
echo 1 > "${adcpath}/cset0/trigger/sw-trg-enable"
sleep 1
# run acquisition program detached from current terminal
timeout 10 "$top/software/fmc-adc-100m14b4cha-sw/libtools/fald-acq" -b 0 -a $1 -r $2 -B /tmp/data.bin "0x${id}" &
# wait
sleep 1
# software trigger
echo 1 > "${adcpath}/cset0/trigger/sw-trg-fire"
# wait for fald-acq to return
# it will either return after acquisition or with timeout
wait $!
if [ "$?" -eq 0 ]
then
echo "fald-acq retured succesfully"
exit 0
else
# echo "fald-acq retured with status $?"
echo "$(tput setab 1)fald-acq retured with status $?(tput sgr 0)"
echo "retrying with bigger delay"
# kill acquisition program
pid=`ps aux | awk '$11 == "fald-acq" {print $2}'`
if [ -n "$pid" ]
then
echo "killing: $pid"
kill -9 $pid
fi
# then data buffer
rm -f /tmp/data.bin
# run acquisition program detached from current terminal
timeout 15 "$top/software/fmc-adc-100m14b4cha-sw/libtools/fald-acq" -b 0 -a $1 -r $2 -B /tmp/data.bin "0x${id}" &
# wait
sleep 5
# software trigger
echo 1 > "${adcpath}/cset0/trigger/sw-trg-fire"
wait $!
if [ "$?" -eq 0 ]
then
echo "fald-acq retured succesfully"
exit 0
else
echo "fald-acq retured with status $?"
echo "abording"
exit 1
fi
fi
)
python/regs_lib.py
View file @ ad87833c
......@@ -40,21 +40,23 @@ DDS_REG_GW = 0x00000044
DDS_REG_DAC = 0x00000048
DDS_REG_TEST_COMM = 0x0000004c
DDS_REG_FPGACTRL = 0x00000050
DDS_REG_CLK0 = 0x00000054
DDS_REG_CLK1 = 0x00000058
DDS_REG_CLK2 = 0x0000005c
DDS_REG_PDTEST = 0x00000060
DDS_REG_OSCDAC = 0x00000064
DDS_REG_ADCINTERFACE = 0x00000068
DDS_REG_DELAY = 0x0000006c
DDS_REG_DELPHASE = 0x00000070
DDS_REG_TRIGGER = 0x00000074
DDS_REG_PD_FIFO_R0 = 0x00000078
DDS_REG_PD_FIFO_CSR = 0x0000007c
DDS_REG_TUNE_FIFO_R0 = 0x00000080
DDS_REG_TUNE_FIFO_CSR = 0x00000084
DDS_REG_PI_R0 = 0x00000088
DDS_REG_PI_CSR = 0x0000008c
DDS_REG_FPGAPLL_CLK2_CTRL = 0x00000054
DDS_REG_FPGAPLL_CLK2_STAT = 0x00000058
DDS_REG_CLK0 = 0x0000005c
DDS_REG_CLK1 = 0x00000060
DDS_REG_CLK2 = 0x00000064
DDS_REG_PDTEST = 0x00000068
DDS_REG_OSCDAC = 0x0000006c
DDS_REG_ADCINTERFACE = 0x00000070
DDS_REG_DELAY = 0x00000074
DDS_REG_DELPHASE = 0x00000078
DDS_REG_TRIGGER = 0x0000007c
DDS_REG_PD_FIFO_R0 = 0x00000080
DDS_REG_PD_FIFO_CSR = 0x00000084
DDS_REG_TUNE_FIFO_R0 = 0x00000088
DDS_REG_TUNE_FIFO_CSR = 0x0000008c
DDS_REG_PI_R0 = 0x00000090
DDS_REG_PI_CSR = 0x00000094
......@@ -120,6 +122,8 @@ def DDS_RSTR_PLL_RST():
return WBGEN2_GEN_MASK(0, 1)
def DDS_RSTR_SW_RST():
return WBGEN2_GEN_MASK(1, 1)
def DDS_RSTR_FREQ_RES():
return WBGEN2_GEN_MASK(2, 1)
def DDS_I2CR_SCL_OUT():
return WBGEN2_GEN_MASK(0, 1)
def DDS_I2CR_SDA_OUT():
......@@ -166,6 +170,10 @@ def DDS_TEST_COMM_LED_G():
return WBGEN2_GEN_MASK(17, 1)
def DDS_FPGACTRL_MAINPLL():
return WBGEN2_GEN_MASK(0, 1)
def DDS_FPGAPLL_CLK2_CTRL_RST():
return WBGEN2_GEN_MASK(0, 1)
def DDS_FPGAPLL_CLK2_STAT_LOCK():
return WBGEN2_GEN_MASK(0, 1)
def DDS_CLK0_FREQ_MASK():
return WBGEN2_GEN_MASK(0, 32)
def DDS_CLK1_FREQ_MASK():
......
python/test03.py
View file @ ad87833c
......@@ -192,10 +192,44 @@ def test_refclk_presense(dut):
else:
print "AD9510: REFIN line verification succeeded"
def verify_fpll_clk2( carrier ):
lock = carrier.readl(DDS_REG_FPGAPLL_CLK2_STAT)
print "CLK2 FPGA PLL lock status: " + str( carrier.readl(DDS_REG_FPGAPLL_CLK2_STAT) )
if lock != 0:
return 1
else:
# rise reset signal for pll
carrier.writel(DDS_REG_FPGAPLL_CLK2_CTRL, 1 )
# wait
time.sleep(0.5)
# remove reset signal for pll
carrier.writel(DDS_REG_FPGAPLL_CLK2_CTRL, 0 )
# wait for pll to lock
for i in range(0,30):
lock = carrier.readl(DDS_REG_FPGAPLL_CLK2_STAT)
if lock != 0:
print "PLL locked in %d try" % (i + 1)
return 1
time.sleep(0.5)
# failed to lock
return 0
def test_clk2(carrier, set_freq = 50e6, max_diff = 5e6 ):
samples = 10;
# measurement might not be very accurate
# its just to check if clock lines are valid
# PLL tends to loose synchronization when clock source is changed
if verify_fpll_clk2( carrier ) == 0 :
raise PtsError("CLK2 FPGA PLL did not lock on reference clock");
time.sleep(3)
mean = 0
for i in range(samples):
......@@ -210,7 +244,28 @@ def test_clk2(carrier, set_freq = 50e6, max_diff = 5e6 ):
return 1
else:
return 0
def test_clk0(carrier, set_freq = 50e6, max_diff = 5e6 ):
samples = 10;
# measurement might not be very accurate
# its just to check if clock lines are valid
mean = 0
for i in range(samples):
mean += carrier.readl(DDS_REG_CLK0)
time.sleep(0.5)
mean /= samples
print "Measured frequency:%d" % mean
if abs( set_freq-mean ) > max_diff :
return 1
else:
return 0
def test_rf_in(carrier, pll,dacinst, box):
......@@ -219,6 +274,8 @@ def test_rf_in(carrier, pll,dacinst, box):
# if that is the case then if i connect this DAC output to RF IN
# i can pass this clock through PLL and measure frequency in FPGA
test_freq = 15e6;
if not AUTOMATION:
print >> __stdout__, "Please connect DAC output to RF IN input in FMC DAC 600M 12b 1cha DDS and confirm with enter button"
raw_input("")
......@@ -227,20 +284,27 @@ def test_rf_in(carrier, pll,dacinst, box):
box.select_output(calibration_box_connections.connections['raw_dac'])
time.sleep(1);
print "Testing RF IN port with 10 MHz frequency clock"
print "Testing RF IN port with %d MHz frequency clock" % (test_freq/1e6)
# Set DAC to output 10M Sine
dacinst.set_en( 1 );
dacinst.set_shape( dacinst.SHAPE_SINE );
dacinst.set_ampl( 1 );
dacinst.set_frequency( 10e6 );
dacinst.set_frequency( test_freq );
time.sleep(2);
# make sure that dac works correctly
if test_clk0( carrier, test_freq, 1e6) > 0:
raise PtsError("DAC does not generate set frequency");
else :
print "DAC output was verified on CLK0OUT"
# set pll to pass CLK1 to OUT6 without frequency division
pll.write_reg(
0x0A,
( B_BYPASS(0) | PRESCALLER(0) | POWER_DOWN(1) )
( B_BYPASS(0) | PRESCALLER(0) | POWER_DOWN(0) )
);
pll.write_reg( 0x54, 0 );
......@@ -249,6 +313,7 @@ def test_rf_in(carrier, pll,dacinst, box):
pll.write_reg(
0x55,
( BYPASS(1) | NO_SYNC(0) | FORCE(0) | START_HL(0) | PHASE_OFFSET(0) )
# ( BYPASS(0) | NO_SYNC(0) | FORCE(0) | START_HL(0) | PHASE_OFFSET(0) )
);
pll.write_reg(
......@@ -261,13 +326,14 @@ def test_rf_in(carrier, pll,dacinst, box):
pll.write_reg(
0x5A,
UPDATE_REGISTERS(1)
);
);
# wait for configuration to take effect
time.sleep(5)
time.sleep(3)
# measure frequency in fpga
if test_clk2(carrier, 10e6, 1e6) > 0:
if test_clk2(carrier, test_freq, 1e6) > 0:
print "RF IN input might be corrupted"
raise PtsError("RF IN input might be corrupted")
def test_ref_out(carrier, pll,dacinst, box):
......@@ -284,18 +350,28 @@ def test_ref_out(carrier, pll,dacinst, box):
box.select_output(calibration_box_connections.connections['ref_clk'])
time.sleep(1);
test_freq = 20e6;
print "Testing REF CLK port with 10 MHz frequency clock"
print "Testing REF CLK port with %d MHz frequency clock" % ( test_freq/1e6 )
# Set DAC to output 10M Sine
dacinst.set_en( 1 );
dacinst.set_shape( dacinst.SHAPE_SINE );
dacinst.set_ampl( 1 );
dacinst.set_frequency( 10e6 );
dacinst.set_frequency( test_freq );
time.sleep(3)
# make sure that dac works correctly
if test_clk0( carrier, test_freq, 1e6) > 0:
raise PtsError("DAC does not generate set frequency");
else:
print "DAC output was verified on CLK0OUT"
# set pll to pass CLK1 to OUT6 without frequency division
pll.write_reg(
0x0A,
( B_BYPASS(0) | PRESCALLER(0) | POWER_DOWN(1) )
( B_BYPASS(0) | PRESCALLER(0) | POWER_DOWN(0) )
);
pll.write_reg( 0x54, 0 );
......@@ -304,6 +380,7 @@ def test_ref_out(carrier, pll,dacinst, box):
pll.write_reg(
0x55,
( BYPASS(1) | NO_SYNC(0) | FORCE(0) | START_HL(0) | PHASE_OFFSET(0) )
# ( BYPASS(0) | NO_SYNC(0) | FORCE(0) | START_HL(0) | PHASE_OFFSET(0) )
);
pll.write_reg(
......@@ -322,8 +399,9 @@ def test_ref_out(carrier, pll,dacinst, box):
time.sleep(5)
# measure frequency in FPGA
if test_clk2(carrier, 10e6, 1e6) > 0:
raise PtsError("RF IN input might be corrupted")
if test_clk2(carrier, test_freq, 1e6) > 0:
print "REF CLK output might be corrupted"
raise PtsError("REF CLK output might be corrupted")
def test_beam_out(carrier, pll,dacinst, box):
......@@ -337,9 +415,11 @@ def test_beam_out(carrier, pll,dacinst, box):
else:
box.select_output(calibration_box_connections.connections['beam_clk'])
time.sleep(1);
time.sleep(5);
print "Testing Beam CLK port with 50 MHz frequency clock"
test_freq = 50e6
print "Testing Beam CLK port with %d MHz frequency clock" % ( test_freq/1e6)
# set pll to pass CLK1 to OUT6 with 10x frequency division
pll.write_reg(
0x0A,
......@@ -369,9 +449,10 @@ def test_beam_out(carrier, pll,dacinst, box):
time.sleep(5)
# measure frequency in FPGA
# BEAM should be 500MHz
if test_clk2(carrier, 50e6, 10e6) > 0:
raise PtsError("RF IN input might be corrupted")
# BEAM should be 500MHz divided by 10 in output divider
if test_clk2(carrier, test_freq, 2e6) > 0:
print "BEAM CLK output might be corrupted"
raise PtsError("BEAM CLK output might be corrupted")
......@@ -417,8 +498,7 @@ def main (card=None, default_directory='.',suite=None):
# default configuration after reset
vcxo_pll = ad9510(carrier, 1);
# check status line
test_ld_line(vcxo_pll);
......@@ -429,17 +509,20 @@ def main (card=None, default_directory='.',suite=None):
test_refclk_presense(vcxo_pll);
time.sleep(2)
print "Testing CLK2 line with 50 MHz frequency clock"
# validate CLK2 lines to FPGA
print "Testing CLK2 line with 50 MHz frequency clock"
if test_clk2(carrier, 50e6, 5e6) > 0:
raise PtsError("ad9510: CLK2 clock lines might be corrupted")
print "CLK2 line verification succeeded"
if TEST_RAW_DAC:
# validate RF IN input connector
test_rf_in(carrier, vcxo_pll, dacinst, box)
# validate REF OUT output connector
test_ref_out(carrier, vcxo_pll, dacinst, box)
vcxo_pll = ad9510(carrier, 1);
# validate BEAM OUT output connector
......
software/regs/dds_regs.h
View file @ ad87833c
/*
Register definitions for slave core: DDS RF distribution WB Slave
* File : /home/gumas/pts/test/fmcdac600m12b1chadds//software/regs/dds_regs.h
* Author : auto-generated by wbgen2 from /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
* Created : Tue Aug 11 14:03:44 2015
* File : /home/gumas/tmp/pts/test/fmcdac600m12b1chadds//software/regs/dds_regs.h
* Author : auto-generated by wbgen2 from /home/gumas/tmp/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
* Created : Tue Feb 2 09:40:19 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/tmp/pts/test/fmcdac600m12b1chadds//gateware/rtl/dds_wb_slave.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_/HOME/GUMAS/PTS/TEST/FMCDAC600M12B1CHADDS//GATEWARE/RTL/DDS_WB_SLAVE_WB
#define __WBGEN2_REGDEFS_/HOME/GUMAS/PTS/TEST/FMCDAC600M12B1CHADDS//GATEWARE/RTL/DDS_WB_SLAVE_WB
#ifndef __WBGEN2_REGDEFS_/HOME/GUMAS/TMP/PTS/TEST/FMCDAC600M12B1CHADDS//GATEWARE/RTL/DDS_WB_SLAVE_WB
#define __WBGEN2_REGDEFS_/HOME/GUMAS/TMP/PTS/TEST/FMCDAC600M12B1CHADDS//GATEWARE/RTL/DDS_WB_SLAVE_WB
#include <inttypes.h>
......@@ -139,6 +139,9 @@
/* definitions for field: FPGA DDS Logic software reset in reg: Reset Register */
#define DDS_RSTR_SW_RST WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Freqency meters reset in reg: Reset Register */
#define DDS_RSTR_FREQ_RES WBGEN2_GEN_MASK(2, 1)
/* definitions for register: I2C bitbanged IO register */
/* definitions for field: SCL Line out in reg: I2C bitbanged IO register */
......@@ -280,6 +283,16 @@
/* definitions for field: MainPll in reg: FPGA control registers */
#define DDS_FPGACTRL_MAINPLL WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FPGA PLL CLK2 Control */
/* definitions for field: Reset in reg: FPGA PLL CLK2 Control */
#define DDS_FPGAPLL_CLK2_CTRL_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FPGA PLL CLK2 Status */
/* definitions for field: Lock detect in reg: FPGA PLL CLK2 Status */
#define DDS_FPGAPLL_CLK2_STAT_LOCK WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FPGA Frequency measurement of frequecy from DAC */
/* definitions for field: Measured frequency in reg: FPGA Frequency measurement of frequecy from DAC */
......@@ -456,34 +469,38 @@
#define DDS_REG_TEST_COMM 0x0000004c
/* [0x50]: REG FPGA control registers */
#define DDS_REG_FPGACTRL 0x00000050
/* [0x54]: REG FPGA Frequency measurement of frequecy from DAC */
#define DDS_REG_CLK0 0x00000054
/* [0x58]: REG FPGA Frequency measurement of frequecy from AD9516 */
#define DDS_REG_CLK1 0x00000058
/* [0x5c]: REG FPGA Frequency measurement of frequecy from AD9510 */
#define DDS_REG_CLK2 0x0000005c
/* [0x60]: REG Period of LD output */
#define DDS_REG_PDTEST 0x00000060
/* [0x64]: REG Oscillator DAC communication */
#define DDS_REG_OSCDAC 0x00000064
/* [0x68]: REG ADC interface control */
#define DDS_REG_ADCINTERFACE 0x00000068
/* [0x6c]: REG Delay controls */
#define DDS_REG_DELAY 0x0000006c
/* [0x70]: REG Delay phase comparator */
#define DDS_REG_DELPHASE 0x00000070
/* [0x74]: REG Trigger input clock frequency */
#define DDS_REG_TRIGGER 0x00000074
/* [0x78]: REG FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */
#define DDS_REG_PD_FIFO_R0 0x00000078
/* [0x7c]: REG FIFO 'PD ADC Test FIFO (test mode)' control/status register */
#define DDS_REG_PD_FIFO_CSR 0x0000007c
/* [0x80]: REG FIFO 'DDS Tuning FIFO (test mode)' data input register 0 */
#define DDS_REG_TUNE_FIFO_R0 0x00000080
/* [0x84]: REG FIFO 'DDS Tuning FIFO (test mode)' control/status register */
#define DDS_REG_TUNE_FIFO_CSR 0x00000084
/* [0x88]: REG FIFO 'PI Controller' data output register 0 */
#define DDS_REG_PI_R0 0x00000088
/* [0x8c]: REG FIFO 'PI Controller' control/status register */
#define DDS_REG_PI_CSR 0x0000008c
/* [0x54]: REG FPGA PLL CLK2 Control */
#define DDS_REG_FPGAPLL_CLK2_CTRL 0x00000054
/* [0x58]: REG FPGA PLL CLK2 Status */
#define DDS_REG_FPGAPLL_CLK2_STAT 0x00000058
/* [0x5c]: REG FPGA Frequency measurement of frequecy from DAC */
#define DDS_REG_CLK0 0x0000005c
/* [0x60]: REG FPGA Frequency measurement of frequecy from AD9516 */
#define DDS_REG_CLK1 0x00000060
/* [0x64]: REG FPGA Frequency measurement of frequecy from AD9510 */
#define DDS_REG_CLK2 0x00000064
/* [0x68]: REG Period of LD output */
#define DDS_REG_PDTEST 0x00000068
/* [0x6c]: REG Oscillator DAC communication */
#define DDS_REG_OSCDAC 0x0000006c
/* [0x70]: REG ADC interface control */
#define DDS_REG_ADCINTERFACE 0x00000070
/* [0x74]: REG Delay controls */
#define DDS_REG_DELAY 0x00000074
/* [0x78]: REG Delay phase comparator */
#define DDS_REG_DELPHASE 0x00000078
/* [0x7c]: REG Trigger input clock frequency */
#define DDS_REG_TRIGGER 0x0000007c
/* [0x80]: REG FIFO 'PD ADC Test FIFO (test mode)' data output register 0 */
#define DDS_REG_PD_FIFO_R0 0x00000080
/* [0x84]: REG FIFO 'PD ADC Test FIFO (test mode)' control/status register */
#define DDS_REG_PD_FIFO_CSR 0x00000084
/* [0x88]: REG FIFO 'DDS Tuning FIFO (test mode)' data input register 0 */
#define DDS_REG_TUNE_FIFO_R0 0x00000088
/* [0x8c]: REG FIFO 'DDS Tuning FIFO (test mode)' control/status register */
#define DDS_REG_TUNE_FIFO_CSR 0x0000008c
/* [0x90]: REG FIFO 'PI Controller' data output register 0 */
#define DDS_REG_PI_R0 0x00000090
/* [0x94]: REG FIFO 'PI Controller' control/status register */
#define DDS_REG_PI_CSR 0x00000094
#endif
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment