added AD9512 SPI mux (between automatic configuration and WB access)

52f577fb · Jan Pospisil · 42357774 · 52f577fb · 52f577fb · 52f577fb
Commit 52f577fb authored Apr 04, 2017 by Jan Pospisil
10 changed files
--- a/doc/manual/ffpg_csr.htm
+++ b/doc/manual/ffpg_csr.htm
@@ -763,6 +763,23 @@ ffpg_control_fine_delay_enable_o
 </td>
 <td  class="td_pblock_left">
+</td>
+<td  class="td_sym_center">
+</td>
+<td  class="td_pblock_right">
+ffpg_control_ad9512_spi_override_o
+</td>
+<td  class="td_arrow_right">
+&rarr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+</td>
+<td  class="td_pblock_left">
 </td>
 <td  class="td_sym_center">
 &nbsp;
@@ -2807,8 +2824,8 @@ CONTROL
 <td  class="td_unused">
 -
 </td>
-<td  class="td_unused">
+<td style="border: solid 1px black;" colspan=1  class="td_field">
-
+AD9512_SPI_OVERRIDE
 </td>
 <td style="border: solid 1px black;" colspan=1  class="td_field">
 FINE_DELAY_ENABLE
@@ -2914,6 +2931,11 @@ AD9512_SYNC
 FINE_DELAY_ENABLE
 </b>[<i>read/write</i>]: AD9512 OUT4 fine delay enable
 <br>If set to 1, fine delay on OUT4 output of AD9512 is enabled. Fine delay itself can be set in a separate register.
+<li><b>
+[11] 
+AD9512_SPI_OVERRIDE
+</b>[<i>read/write</i>]: Override automatic AD9512 configuration by WB-SPI access
+<br>If set to 1, the AD9512 SPI port is connected to the WB-SPI bridge. Otherwise, the automatic configuration block is connected to the AD9512 SPI.
 </ul>
 <a name="VCXO_VOLTAGE"></a>
 <h3><a name="sect_3_3">3.3. VCXO voltage register</a></h3>

--- a/hdl/ffpg/rtl/FfpgCore.vhd
+++ b/hdl/ffpg/rtl/FfpgCore.vhd
@@ -150,7 +150,10 @@ architecture syn of FfpgCore is
    -- SPI
    signal ChipSelect_b32: std_logic_vector(31 downto 0);
+    signal SpiAd9512SclkWb, SpiAd9512CsWb_n, SpiAd9512MosiWb: std_logic;
+    signal SpiAd9512SclkFfpg, SpiAd9512CsFfpg_n, SpiAd9512MosiFfpg: std_logic;
+    signal Ad9512SpiOverride: std_logic;
 begin
    cResetSyncerSys: entity work.ResetSyncer(syn)
@@ -220,10 +223,11 @@ begin
            Trigger_i => Trigger_i,
            Clk2Sel_o => Clk2Sel_o,
            Led_ob => Led_ob,
-            SpiAd9512Cs_on => open,
+            SpiAd9512Cs_on => SpiAd9512CsFfpg_n,
-            SpiAd9512Sclk_o => open,
+            SpiAd9512Sclk_o => SpiAd9512SclkFfpg,
-            SpiAd9512Mosi_o => open,
+            SpiAd9512Mosi_o => SpiAd9512MosiFfpg,
-            SpiAd9512Miso_i => '1',
+            SpiAd9512Miso_i => SpiAd9512Miso_i,
+            Ad9512SpiOverride_o => Ad9512SpiOverride,
            Ad9512Func_o => Ad9512Func_o,
            ClkOut_ok => ClkOut_ok
        );
@@ -263,7 +267,7 @@ begin
    Owr <= Onewire_io;
    ----------------------------------
-    -- AD9512 SPI slave
+    -- AD9512 WB-SPI slave
    ----------------------------------
    cSpiMasterWb: entity work.SpiMasterWb
@@ -279,8 +283,8 @@ begin
        Ack_oa => CnxMasterIn(c_SlaveAd9512Id).ack,
        WaitingNewData_o => open,
        ModuleIdle_o => open,
-        SClk_o => SpiAd9512Sclk_o,
+        SClk_o => SpiAd9512SclkWb,
-        MoSi_o => SpiAd9512Mosi_o,
+        MoSi_o => SpiAd9512MosiWb,
        MiSo_ib32(0) => SpiAd9512Miso_i,
        MiSo_ib32(31 downto 1) => "0000000000000000000000000000000",
        SS_onb32 => ChipSelect_b32
@@ -289,6 +293,20 @@ begin
    CnxMasterIn(c_SlaveAd9512Id).rty <= '0';
    CnxMasterIn(c_SlaveAd9512Id).stall <= '0';
    CnxMasterIn(c_SlaveAd9512Id).int <= '0';
-    SpiAd9512Cs_on <= ChipSelect_b32(0);
+    SpiAd9512CsWb_n <= ChipSelect_b32(0);
+    ----------------------------------
+    -- AD9512 SPI mux
+    ----------------------------------
+    SpiAd9512Sclk_o <=
+        SpiAd9512SclkWb when Ad9512SpiOverride = '1' else
+        SpiAd9512SclkFfpg;
+    SpiAd9512Mosi_o <=
+        SpiAd9512MosiWb when Ad9512SpiOverride = '1' else
+        SpiAd9512MosiFfpg;
+    SpiAd9512Cs_on <= 
+        SpiAd9512CsWb_n when Ad9512SpiOverride = '1' else
+        SpiAd9512CsFfpg_n;
 end architecture;
--- a/hdl/ffpg/rtl/FfpgSlave.vhd
+++ b/hdl/ffpg/rtl/FfpgSlave.vhd
@@ -87,6 +87,7 @@ entity FfpgSlave is
        SpiAd9512Mosi_o: out std_logic;
        SpiAd9512Miso_i: in std_logic;
        SpiAd9512Cs_on: out std_logic;
+        Ad9512SpiOverride_o: out std_logic;
        -- AD9512 func. pin
        Ad9512Func_o: out std_logic;
        -- clock output
@@ -350,6 +351,8 @@ begin
            SpiAd9512Cs_on => SpiAd9512Cs_on
        );
+    Ad9512SpiOverride_o <= WbRegsOutput.control_ad9512_spi_override_o;
    cAd9512Syncer: entity work.Ad9512Syncer(syn)
        generic map (
            g_ClkFrequency => g_ClkFrequency

--- a/hdl/ffpg/rtl/ffpg_csr.vhd
+++ b/hdl/ffpg/rtl/ffpg_csr.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/ffpg_csr.vhd
 -- Author         : auto-generated by wbgen2 from ffpg_csr.wb
-- Created        : 12/19/16 17:04:33
+-- Created        : 04/04/17 16:13:19
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ffpg_csr.wb
@@ -72,6 +72,7 @@ architecture syn of ffpg_csr is
  signal ffpg_control_ad9512_sync_dly0            : std_logic;
  signal ffpg_control_ad9512_sync_int             : std_logic;
  signal ffpg_control_fine_delay_enable_int       : std_logic;
+  signal ffpg_control_ad9512_spi_override_int     : std_logic;
  signal ffpg_ch1_set_mem_rddata_int              : std_logic_vector(31 downto 0);
  signal ffpg_ch1_set_mem_rd_int                  : std_logic;
  signal ffpg_ch1_set_mem_wr_int                  : std_logic;
@@ -119,6 +120,7 @@ begin
      ffpg_control_led_test_int <= '0';
      ffpg_control_ad9512_sync_int <= '0';
      ffpg_control_fine_delay_enable_int <= '0';
+      ffpg_control_ad9512_spi_override_int <= '0';
      regs_o.vcxo_voltage_load_o <= '0';
      regs_o.clock_ratio_m1_load_o <= '0';
      regs_o.ch1_delay_set_load_o <= '0';
@@ -198,6 +200,7 @@ begin
                ffpg_control_led_test_int <= wrdata_reg(8);
                ffpg_control_ad9512_sync_int <= wrdata_reg(9);
                ffpg_control_fine_delay_enable_int <= wrdata_reg(10);
+                ffpg_control_ad9512_spi_override_int <= wrdata_reg(11);
              end if;
              rddata_reg(1 downto 0) <= ffpg_control_clock_selection_int;
              rddata_reg(2) <= ffpg_control_ch1_oe_int;
@@ -207,7 +210,8 @@ begin
              rddata_reg(8) <= ffpg_control_led_test_int;
              rddata_reg(9) <= '0';
              rddata_reg(10) <= ffpg_control_fine_delay_enable_int;
-              rddata_reg(31 downto 11) <= (others => 'X');
+              rddata_reg(11) <= ffpg_control_ad9512_spi_override_int;
+              rddata_reg(31 downto 12) <= (others => 'X');
              ack_sreg(2) <= '1';
              ack_in_progress <= '1';
            when "0010" => 
@@ -445,6 +449,8 @@ begin
 -- AD9512 OUT4 fine delay enable
  regs_o.control_fine_delay_enable_o <= ffpg_control_fine_delay_enable_int;
+-- Override automatic AD9512 configuration by WB-SPI access
+  regs_o.control_ad9512_spi_override_o <= ffpg_control_ad9512_spi_override_int;
 -- VCXO voltage register value
  regs_o.vcxo_voltage_o <= unsigned(wrdata_reg(15 downto 0));
 -- Clock ratio-1

--- a/hdl/ffpg/rtl/ffpg_csr_pkg.vhd
+++ b/hdl/ffpg/rtl/ffpg_csr_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/ffpg_csr_pkg.vhd
 -- Author         : auto-generated by wbgen2 from ffpg_csr.wb
-- Created        : 12/19/16 17:04:33
+-- Created        : 04/04/17 16:13:19
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ffpg_csr.wb
@@ -93,6 +93,7 @@ package ffpg_wbgen2_pkg is
    control_led_test_o                       : std_logic;
    control_ad9512_sync_o                    : std_logic;
    control_fine_delay_enable_o              : std_logic;
+    control_ad9512_spi_override_o            : std_logic;
    vcxo_voltage_o                           : unsigned(15 downto 0);
    vcxo_voltage_load_o                      : std_logic;
    clock_ratio_m1_o                         : unsigned(4 downto 0);
@@ -130,6 +131,7 @@ package ffpg_wbgen2_pkg is
    control_led_test_o => '0',
    control_ad9512_sync_o => '0',
    control_fine_delay_enable_o => '0',
+    control_ad9512_spi_override_o => '0',
    vcxo_voltage_o => (others => '0'),
    vcxo_voltage_load_o => '0',
    clock_ratio_m1_o => (others => '0'),

--- a/hdl/ffpg/sim/testbench/ffpg_csr.svh
+++ b/hdl/ffpg/sim/testbench/ffpg_csr.svh
@@ -34,6 +34,8 @@
 `define FFPG_CONTROL_AD9512_SYNC 32'h00000200
 `define FFPG_CONTROL_FINE_DELAY_ENABLE_OFFSET 10
 `define FFPG_CONTROL_FINE_DELAY_ENABLE 32'h00000400
+`define FFPG_CONTROL_AD9512_SPI_OVERRIDE_OFFSET 11
+`define FFPG_CONTROL_AD9512_SPI_OVERRIDE 32'h00000800
 `define ADDR_FFPG_VCXO_VOLTAGE         16'h8
 `define ADDR_FFPG_CLOCK_RATIO_M1       16'hc
 `define ADDR_FFPG_CH1_DELAY_SET        16'h10

--- a/hdl/ffpg/wb_gen/ffpg_csr.h
+++ b/hdl/ffpg/wb_gen/ffpg_csr.h
@@ -3,7 +3,7 @@
  * File           : ffpg_csr.h
  * Author         : auto-generated by wbgen2 from ffpg_csr.wb
-  * Created        : 12/19/16 17:04:33
+  * Created        : 04/04/17 16:13:19
  * Standard       : ANSI C
    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ffpg_csr.wb
@@ -95,6 +95,9 @@
 /* definitions for field: AD9512 OUT4 fine delay enable in reg: Control register */
 #define FFPG_CONTROL_FINE_DELAY_ENABLE        WBGEN2_GEN_MASK(10, 1)
+/* definitions for field: Override automatic AD9512 configuration by WB-SPI access in reg: Control register */
+#define FFPG_CONTROL_AD9512_SPI_OVERRIDE      WBGEN2_GEN_MASK(11, 1)
 /* definitions for register: VCXO voltage register */
 /* definitions for register: Clock ratio-1 register */

--- a/hdl/ffpg/wb_gen/ffpg_csr.wb
+++ b/hdl/ffpg/wb_gen/ffpg_csr.wb
@@ -146,6 +146,14 @@ peripheral { name = "FMC DEL 1ns 2cha core registers";
            access_dev = READ_ONLY;
        };
+        field { name = "Override automatic AD9512 configuration by WB-SPI access";
+            description = "If set to 1, the AD9512 SPI port is connected to the WB-SPI bridge. Otherwise, the automatic configuration block is connected to the AD9512 SPI.";
+            prefix = "ad9512_spi_override";
+            type = BIT;
+            access_bus = READ_WRITE;
+            access_dev = READ_ONLY;
+        };
    };
    reg { name = "VCXO voltage register";

--- a/sw/FFPG_driver.py
+++ b/sw/FFPG_driver.py
@@ -60,7 +60,7 @@ calibrationData = [ # -1 = uncalibrated
    [51.29, 51.11]      # FMC slot 1
 ]
-fmcSlot = 1 # 0 | 1
+fmcSlot = 0 # 0 | 1
 channel = 1 # 1 | 2
 ad9512Config = (
@@ -84,14 +84,9 @@ ad9512Config = (
 def Init(pg):
    global calibrationData
-    global ad9512Config
    pg.Reset()
    pg.SelectClock("external", 400.789)
    pg.SetRatio(2)
-    pg.ad9512.Config(ad9512Config)
    pg.SetOverflow(17820)
    pg.Ad9512Sync()
    pg.SetTriggerThreshold(0.5)
@@ -160,7 +155,12 @@ pg.PrintControl()
 pg.PrintStatus()
 pg.PrintDebug()
-# pg.ad9512.Check(ad9512Config)
+'''
+pg.Ad9512ActivateWbAccess()
+pg.ad9512.Config(ad9512Config)
+pg.ad9512.Check(ad9512Config)
+pg.Ad9512DisableWbAccess()
+'''
 # pg.ad9512.debug = True
 # pg.wb.SetDebug(True)

--- a/sw/Ffpg.py
+++ b/sw/Ffpg.py
@@ -130,6 +130,13 @@ class Ffpg(object):
    def Ad9512Sync(self):
        """ synchronize AD9512 dividers """
        self.wb.SetBits("control", 1<<9)
+    def Ad9512ActivateWbAccess(self):
+        self.wb.SetBits("control", 1<<11)
+    def Ad9512DisableWbAccess(self):
+        # return back to the automatic configuration
+        self.wb.SetBits("control", 1<<11, 0)
    def SetTriggerThreshold(self, voltage):
        """ voltage in [V] """