Skip to content

F
FMC DEL 1ns 4cha
Commit c43e9ebc authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

HDL: fd_spi_master: change MOSI status and sample MISO in between SCK edges

parent 5ba77508
Hide whitespace changes
Inline Side-by-side
Showing with 19 additions and 8 deletions
hdl/rtl/fd_spi_master.vhd
View file @ c43e9ebc
...@@ -46,7 +46,7 @@ architecture behavioral of fd_spi_master is ...@@ -46,7 +46,7 @@ architecture behavioral of fd_spi_master is
signal sreg : std_logic_vector(23 downto 0); signal sreg : std_logic_vector(23 downto 0);
signal rx_sreg : std_logic_vector(23 downto 0); signal rx_sreg : std_logic_vector(23 downto 0);
type t_state is (IDLE, TX_CS, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP); type t_state is (IDLE, TX_CS, TX_DAT1, TX_DAT2, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
signal state : t_state; signal state : t_state;
signal sclk : std_logic; signal sclk : std_logic;
...@@ -88,7 +88,7 @@ begin -- rtl ...@@ -88,7 +88,7 @@ begin -- rtl
else else
case state is case state is
when IDLE => when IDLE =>
sclk <= '1'; sclk <= '0';
counter <= (others => '0'); counter <= (others => '0');
if(start_i = '1') then if(start_i = '1') then
sreg <= data_i; sreg <= data_i;
...@@ -101,26 +101,37 @@ begin -- rtl ...@@ -101,26 +101,37 @@ begin -- rtl
when TX_CS => when TX_CS =>
if divider_muxed = '1' then if divider_muxed = '1' then
state <= TX_SCK1; state <= TX_DAT1;
end if; end if;
when TX_SCK1 => when TX_DAT1 =>
if(divider_muxed = '1') then if(divider_muxed = '1') then
sclk <= not sclk;
spi_mosi_o <= sreg(sreg'high); spi_mosi_o <= sreg(sreg'high);
sreg <= sreg(sreg'high-1 downto 0) & '0'; sreg <= sreg(sreg'high-1 downto 0) & '0';
state <= TX_SCK1;
end if;
when TX_SCK1 =>
if(divider_muxed = '1') then
sclk <= not sclk;
counter <= counter + 1; counter <= counter + 1;
state <= TX_SCK2; state <= TX_DAT2;
end if; end if;
when TX_DAT2 =>
if(divider_muxed = '1') then
rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
state <= TX_SCK2;
end if;
when TX_SCK2 => when TX_SCK2 =>
if(divider_muxed = '1') then if(divider_muxed = '1') then
sclk <= not sclk; sclk <= not sclk;
rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
if(counter = 24) then if(counter = 24) then
state <= TX_CS2; state <= TX_CS2;
else else
state <= TX_SCK1; state <= TX_DAT1;
end if; end if;
end if; end if;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment