Commit f354a5d6 authored by Dimitris Lampridis's avatar Dimitris Lampridis

ci: reuse common hdl synthesis job template

parent 982968c2
......@@ -12,7 +12,6 @@ include:
ref: master
file:
- 'edl-gitlab-ci.yml'
- local: 'hdl/syn/.gitlab-ci.yml'
cppcheck:
stage: analyse
......@@ -40,3 +39,12 @@ kernel_build_validation:
echo "Checking Dependencies"
if [ "$FMC_BUILDS" != "0" ]; then echo 'FMC did not build successfully. Exiting'; exit 1; fi
if [ "$ZIO_BUILDS" != "0" ]; then echo 'ZIO did not build successfully. Exiting'; exit 1; fi
fpga_synthesis:
extends: .synthesis-ise-14-7
interruptible: true
parallel:
matrix:
- EDL_CI_SYN_SRC_PATH:
- hdl/syn/spec
- hdl/syn/svec
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
variables:
_FMC_DELAY_BITSTREAM_DEST: $CI_PROJECT_DIR/$EDL_CI_EOS_OUTPUT_DIR/bitstreams
.syn_template: &syn_template
interruptible: true
stage: build
needs: []
tags:
- xilinx_ise
- "14.7"
script:
- git submodule init && git submodule update
- cd hdl/syn/"$SYN_NAME"/
- hdlmake
- make
- |
if [[ $(cat *.par | grep -c "All constraints were met") = 0 ]]
then
echo -e "\e[31mTiming errors detected in PAR report. Aborting...\e[0m"
exit 1
fi
- tar -cJf $SYN_NAME.tar.xz *.syr *.par *.twr *.bit *.bin
- mkdir -p $_FMC_DELAY_BITSTREAM_DEST
- cp $SYN_NAME.tar.xz $_FMC_DELAY_BITSTREAM_DEST
artifacts:
name: "$SYN_NAME-synthesis-$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
paths:
- $_FMC_DELAY_BITSTREAM_DEST/*
SPEC synthesis:
variables:
SYN_NAME: "spec"
<<: *syn_template
SVEC synthesis:
variables:
SYN_NAME: "svec"
<<: *syn_template
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