Changelog 20012011
Schematics:*
- connected J6C.g1 to GND (FMC requirement)
- removed EXT_CLK (J6.g2, J6.g3) - it's mezzanine to carrier clock
- rerouted FPGA_TDC_REF_CLK to J6.g2
- connected mounting holes (B1..B4) directly to GND
- input stage: R108 reconnected after R120 (directly to IC18.3)
PCB:*
- Removed all routes on the bottom layer from under AD9516 PLL.
- Increased number of thermal vias under AD9516 and removed solder mask on the bottom layer under the chip to improve heat dissipation
- Moved IC13/IC22 to bottom layer (too close to board edge)
- Removed necks from various polygons
- Widened VDDC_TDC plane next to TDC_STOP2 diff pair
- Placed CERN logo on the bottom layer
- Fixed overlapping silkscreen labels
- Updated stackup info