FMC Delay 1ns 4cha - Gateware Release 2.0
(red) WARNING! Release v2.0 Wiki Page in progress. Please don't update anything yet.
Gateware
- v2.0-rc1 bitstream for the SVEC carrier (VME64x): svec-fine-delay-v2.0rc1-20140319.bin
- v2.0-rc1 bitstream for the SPEC carrier (PCIe): spec-fine-delay-v2.0rc1-20140319.bin
Memory map
- Top level interconnect: see ""Driver developers information"":Driver-developers-information-
- Detailed register map: see Design notes
Drivers
Please use the latest master branch of the Fine Delay Software. Release info will be updated soon.
Documentation
Sources
All components correspond to the revisions with tag v2.0-rc1 in the repositories listed below:
- FmcDelay1ns4cha repository. Dependent repositories are referenced as submodules.
Release date
- TBD
Release notes
New features:*
- SVEC: official support for White Rabbit on both mezzanines.
- SVEC: squeezed A24 window size to 0x80000 to allow more than 15 cards in a crate.
- All carriers: Support for interrupts through the VIC interrupt controller.
- All carriers: Embedded SDB synthesis information.
- WR Core: Integrated v2.1 of the WR PTP Core HDL and firmware.
- FD Core: WR Core has no physical access to the mezzanine if disabled by the driver.
- FD Core: improvements in DDMTD calibration logic. |
Major fixes:*
- FD Core: ACAM TDC now works in G-Mode (fixes 1.5 ns timestamping errors).
- FD Core: reset ACAM FIFO each sample (prevents timestamp corruption when pulse rate is too high).
19 March 2014