Project Status
Date |
Event |
22-04-2010 |
Start working on project |
Preliminary functional system specifications
- 1 ns resolution or better.
- 1 us - 120 s range or better.
- 1 input, selectable between front panel and FMC connector. This
input is shared by all output channels.
- Input electrical standard will be TTL, with optional 50 Ohm
termination.
- Output standards to be supported: 50 Ohm TTL drivers (with 2V/ns or
faster rising edges) and 50 Ohm blocking (0-15V) drivers.
- 8 individually controllable outputs, with independent delay, width
and enable/disable.
- Delay circuit reacts on input rising or falling edge (programmable).
Minimum input pulse width: 100 ns.
- Output pulse width is programmable in steps of system clock ticks
(~125 MHz) with a 16-bit register per output channel.
- Jitter will be measured by probing the positive pins of two output
channels which have been programmed with the same delay. The sigma
of the distribution of delay measurements between the rising edges
of any two channels should not exceed 100 ps. This should hold for
any programmed delay within the whole delay range.
- Accuracy better than 200 ps for delays smaller than 1 ms.
Preliminary ideas for the technical specifications
- The system could be split in two parts: an FMC with LVDS I/O and
parallel connectors plus one or more patch panels for level
conversion.
- Baseline solution: TDC at the inputs followed by coarse count in the
FPGA and fine delay chips at the outputs. To be considered for
improving jitter: monolithic FFs in the FMC, before the fine delay
chips. Continuous calibration of fine delay chips might be needed to
compensate for Process-Voltage-Temperature (PVT) effects.