Fine Delay Functional Specifications
Hardware
-
1 TTL trigger input, selectable between front panel and FMC
connector. Front panel input has programmable 50 ohm termination,
the default power-up state is high impedance. A LED will signal
termination status. This input is shared by all output channels.
- External input protected against +15V pulses with a pulse width of at least 10us @ 50Hz.
- Rising-edge sensitive -
4 TTL outputs capable of driving a 50 Ohm load.
- 2 V/ns or faster rising edges
- Output levels: 4.5 V Voh @ 50 Ohm load, 6 V Voh @ Hi-Z load
- Default power-up state: low, with no glitches.
- Must withstand a continuous short-circuit on all the outputs at the same time. - LEMO 00 connectors for input and outputs.
- FMC Low pin count (LPC) connector, 2.5/3.3 V Vadj required.
Modes of operation
- Pulse delay: a pulse coming to the input triggers generation of pulse(s) of given width and frequency on chosen outputs after a certain time programmed by the user.
- Single channel TDC: time tags of incoming pulses are provided to the user via a circular buffer.
- Pulse generator: produce a pulse or a series of pulses of arbitrary length and frequency starting at a given UTC/TAI time.
Notes:
- TDC mode can be used in parallel with Pulse Delay/Pulse Generator mode.
- Pulse Delay/Pulse Generator modes can be used simultaneously on different outputs. Mode of each output is controlled individually.
Performance and limitations
Common parameters (all modes)
- Minimum input pulse width: 100 ns. Pulses below 24 ns are ignored.
- Minimum output pulse width: 50 ns, 10 ps resolution
- Minimum output pulse spacing: 100 ns, 10 ps resolution
- Output repeat (train generation): 1 - 65536 pulses or infinity (continuous mode)