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FMC DIO 5ch TTL a
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FMC DIO 5ch TTL a
Commits
1a316e51
Commit
1a316e51
authored
Apr 07, 2020
by
Jorge Machado
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Plain Diff
Modified programmable pulse train process. It is working now
parent
85963c01
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17 additions
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30 deletions
+17
-30
pulse_gen_pl.vhd
hdl/modules/wr_dio/pulse_gen_pl.vhd
+17
-30
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hdl/modules/wr_dio/pulse_gen_pl.vhd
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1a316e51
...
@@ -200,24 +200,6 @@ begin -- architecture rtl
...
@@ -200,24 +200,6 @@ begin -- architecture rtl
end
if
;
end
if
;
end
process
ready_for_trig
;
end
process
ready_for_trig
;
-- Pulse train generator
pulse_train_gen
:
process
(
rst_n_i
,
clk_ref_i
)
begin
if
rst_n_i
=
'0'
then
pulse_train_trigger
<=
'0'
;
elsif
clk_ref_i
'event
and
clk_ref_i
=
'1'
then
if
train_counter
=
1
then
pulse_train_trigger
<=
'1'
;
train_counter
<=
train_counter
-1
;
elsif
train_counter
/=
0
then
train_counter
<=
train_counter
-1
;
elsif
(
pulse_o_internal
=
'1'
and
nozeroperiod
)
then
train_counter
<=
unsigned
(
pulse_period_ref
)
-2
;
else
pulse_train_trigger
<=
'0'
;
end
if
;
end
if
;
end
process
pulse_train_gen
;
-- Produce output
-- Produce output
-- Note rst_n_i is used as an async reset because it comes from the
-- Note rst_n_i is used as an async reset because it comes from the
...
@@ -232,19 +214,24 @@ begin -- architecture rtl
...
@@ -232,19 +214,24 @@ begin -- architecture rtl
elsif
clk_ref_i
'event
and
clk_ref_i
=
'1'
then
elsif
clk_ref_i
'event
and
clk_ref_i
=
'1'
then
if
tm_time_valid_i
=
'0'
then
if
tm_time_valid_i
=
'0'
then
pulse_o_internal
<=
'0'
;
pulse_o_internal
<=
'0'
;
elsif
tm_utc_i
=
trig_utc_ref
and
tm_cycles_i
=
trig_cycles_ref
and
nozerolength
then
elsif
tm_utc_i
=
trig_utc_ref
and
tm_cycles_i
=
trig_cycles_ref
and
nozerolength
then
--Original trigger
pulse_o_internal
<=
'1'
;
pulse_o_internal
<=
'1'
;
counter
<=
unsigned
(
pulse_length_ref
)
-1
;
counter
<=
unsigned
(
pulse_length_ref
)
-1
;
elsif
tm_utc_i
>=
trig_utc_ref
and
tm_cycles_i
>=
trig_cycles_ref
and
nozeroperiod
and
pulse_o_internal
=
'0'
then
train_counter
<=
unsigned
(
pulse_period_ref
);
--Store the value of the period
if
(
pulse_train_trigger
=
'1'
)
then
elsif
counter
/=
0
then
--The period counter is reduced at the same time than the pulse counter
counter
<=
counter
-1
;
if
(
nozeroperiod
)
then
train_counter
<=
train_counter
-1
;
end
if
;
-- elsif(train_counter = 10) then --Load new values for then next cycle
-- load_values <= '1';
elsif
(
train_counter
=
1
)
then
--Period trigger. Rearm both counters
pulse_o_internal
<=
'1'
;
pulse_o_internal
<=
'1'
;
counter
<=
unsigned
(
pulse_length_ref
)
-1
;
counter
<=
unsigned
(
pulse_length_ref
)
-1
;
end
if
;
train_counter
<=
unsigned
(
pulse_period_ref
);
elsif
counter
=
1
then
--Update the pulse length value in the last cycle of the pulse generation
elsif
train_counter
/=
0
then
load_values
<=
'1'
;
train_counter
<=
train_counter
-1
;
counter
<=
counter
-1
;
pulse_o_internal
<=
'0'
;
elsif
counter
/=
0
then
counter
<=
counter
-1
;
load_values
<=
'0'
;
load_values
<=
'0'
;
else
else
pulse_o_internal
<=
'0'
;
pulse_o_internal
<=
'0'
;
...
...
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