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FMC DIO 5ch TTL a
Commit 85963c01 authored by Jorge Machado's avatar Jorge Machado
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Add some fixes detected during testing

parent a2ff9b09
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hdl/modules/wr_dio/imm_pulse_train_gen.vhd
View file @ 85963c01
......@@ -15,7 +15,7 @@ use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
......@@ -43,24 +43,27 @@ architecture Behavioral of imm_pulse_train_gen is
dio_pulse_immed_stb_d2, dio_pulse_immed_stb_d3 : std_logic;
-- Internal registers to hold pulse duration
signal counter : unsigned (pulse_period_width-1 downto 0);
signal counter : unsigned (pulse_period_width-1 downto 0);
-- Signals for states
type counter_state is (WAIT_ST, COUNTING, CAPTURE_PERIOD, TRIGGER);
signal state : counter_state;
signal repeat_pulse : std_logic;
-- Aux
constant zeros : std_logic_vector(pulse_period_width-1 downto 0) := (others => '0');
begin
synchronization : process(clk_i, rst_n_i)
synchronization : process(clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_pulse_immed_stb_d0 <= '0';
dio_pulse_immed_stb_d1 <= '0';
dio_pulse_immed_stb_d2 <= '0';
dio_pulse_immed_stb_d3 <= '0';
elsif rising_edge(clk_i) then
elsif rising_edge(clk_ref_i) then
dio_pulse_immed_stb_d0 <= dio_pulse_immed_stb_i;
dio_pulse_immed_stb_d1 <= dio_pulse_immed_stb_d0;
dio_pulse_immed_stb_d2 <= dio_pulse_immed_stb_d1;
......@@ -73,19 +76,19 @@ begin
end if;
end process;
state_process : process(clk_i, rst_n_i)
state_process : process(clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
counter <= (others => '0');
state <= WAIT_ST;
repeat_pulse <= '0';
elsif rising_edge(clk_i) then
state <= WAIT_ST;
repeat_pulse <= '0';
elsif rising_edge(clk_ref_i) then
case state is
when WAIT_ST =>
if (dio_pulse_immed_stb_d3 = '1' or repeat_pulse = '1') and nozeroperiod then
state <= COUNTING;
--Store the period two cycle before than the immed_pulse_counter_process to not lost one cycle.
counter <= unsigned(pulse_period)-3;
counter <= unsigned(pulse_period_i)-4;
else
state <= WAIT_ST;
end if;
......@@ -129,7 +132,5 @@ begin
end if;
end process;
end Behavioral;
hdl/modules/wr_dio/pulse_gen_pl.vhd
View file @ 85963c01
......@@ -76,8 +76,9 @@ entity pulse_gen_pl is
trig_utc_i : in std_logic_vector(39 downto 0);
trig_cycles_i : in std_logic_vector(27 downto 0);
trig_valid_p1_i : in std_logic;
pulse_length_i : in std_logic_vector(27 downto 0)
);
pulse_length_i : in std_logic_vector(27 downto 0);
pulse_period_i : in std_logic_vector(27 downto 0)
);
end pulse_gen_pl;
......@@ -87,7 +88,7 @@ architecture rtl of pulse_gen_pl is
signal trig_utc, trig_utc_ref : std_logic_vector(39 downto 0);
signal trig_cycles, trig_cycles_ref : std_logic_vector(27 downto 0);
signal pulse_length, pulse_length_ref : std_logic_vector(27 downto 0);
signal pulse_period, pulse_period_ref : std_logic_vector(27 downto 0);
-- Signals for the synchronizer
signal trig_valid_sys_d1, trig_valid_sys_d2 : std_logic;
signal rst_from_sync, rst_from_sync_d1 : std_logic;
......@@ -97,8 +98,11 @@ architecture rtl of pulse_gen_pl is
-- Aux
constant zeros : std_logic_vector(27 downto 0) := (others => '0');
signal counter : unsigned (27 downto 0);
signal nozerolength : boolean;
signal counter, train_counter : unsigned (27 downto 0);
signal nozerolength, nozeroperiod : boolean;
signal pulse_o_internal : std_logic;
signal pulse_train_trigger : std_logic;
signal load_values : std_logic;
begin -- architecture rtl
......@@ -110,10 +114,12 @@ begin -- architecture rtl
trig_utc <= (others => '0');
trig_cycles <= (others => '0');
pulse_length <= (others => '0');
pulse_period <= (others => '0');
elsif trig_valid_p1_i = '1' then
trig_utc <= trig_utc_i;
trig_cycles <= trig_cycles_i;
pulse_length <= pulse_length_i;
pulse_period <= pulse_period_i;
end if;
end if;
end process trig_regs;
......@@ -166,11 +172,13 @@ begin -- architecture rtl
trig_regs_ref : process (clk_ref_i)
begin
if clk_ref_i'event and clk_ref_i = '1' then
if trig_valid_ref_p1 = '1' then
if trig_valid_ref_p1 = '1' or load_values = '1' then
trig_utc_ref <= trig_utc;
trig_cycles_ref <= trig_cycles;
pulse_length_ref <= pulse_length;
pulse_period_ref <= pulse_period;
pulse_length_ref <= pulse_length;
nozerolength <= pulse_length /= zeros;
nozeroperiod <= pulse_period /= zeros;
end if;
end if;
end process trig_regs_ref;
......@@ -192,6 +200,25 @@ begin -- architecture rtl
end if;
end process ready_for_trig;
-- Pulse train generator
pulse_train_gen : process(rst_n_i, clk_ref_i)
begin
if rst_n_i = '0' then
pulse_train_trigger <= '0';
elsif clk_ref_i'event and clk_ref_i = '1' then
if train_counter = 1 then
pulse_train_trigger <= '1';
train_counter <= train_counter-1;
elsif train_counter /= 0 then
train_counter <= train_counter-1;
elsif(pulse_o_internal = '1' and nozeroperiod) then
train_counter <= unsigned(pulse_period_ref)-2;
else
pulse_train_trigger <= '0';
end if;
end if;
end process pulse_train_gen;
-- Produce output
-- Note rst_n_i is used as an async reset because it comes from the
-- clk_sys_i domain. Not the most elegant but it ensures no glitches
......@@ -201,19 +228,31 @@ begin -- architecture rtl
gen_out : process (rst_n_i, clk_ref_i)
begin
if rst_n_i = '0' then
pulse_o <= '0';
pulse_o_internal <= '0';
elsif clk_ref_i'event and clk_ref_i = '1' then
if tm_time_valid_i = '0' then
pulse_o <= '0';
pulse_o_internal <= '0';
elsif tm_utc_i = trig_utc_ref and tm_cycles_i = trig_cycles_ref and nozerolength then
pulse_o <= '1';
pulse_o_internal <= '1';
counter <= unsigned(pulse_length_ref)-1;
elsif tm_utc_i >= trig_utc_ref and tm_cycles_i >= trig_cycles_ref and nozeroperiod and pulse_o_internal = '0' then
if(pulse_train_trigger = '1') then
pulse_o_internal <= '1';
counter <= unsigned(pulse_length_ref)-1;
end if;
elsif counter = 1 then --Update the pulse length value in the last cycle of the pulse generation
load_values <= '1';
counter <= counter-1;
elsif counter /= 0 then
counter <= counter-1;
load_values <= '0';
else
pulse_o <= '0';
pulse_o_internal <= '0';
load_values <= '0';
end if;
end if;
end process gen_out;
end architecture rtl;
pulse_o <= pulse_o_internal;
end architecture rtl;
\ No newline at end of file
hdl/modules/wr_dio/wr_dio_pkg.vhd
View file @ 85963c01
......@@ -70,7 +70,7 @@ package wr_dio_pkg is
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
addr_last => x"00000000000003ff",
product => (
vendor_id => x"00000000000075CB", -- SEVEN SOLUTIONS
device_id => x"00000001",
......
hdl/modules/wr_dio/xwr_dio.vhd
View file @ 85963c01
......@@ -49,7 +49,7 @@
-- 0x100: DIO-I2C
-- 0x200: DIO-GPIO
-- 0x300: DIO-TIMING REGISTERS
-- 0x400: SDB-BRIDGE --> MAGIC NUMBER
-- 0x800: SDB-BRIDGE --> MAGIC NUMBER
library ieee;
use ieee.std_logic_1164.all;
......@@ -105,6 +105,7 @@ end xwr_dio;
architecture rtl of xwr_dio is
-------------------------------------------------------------------------------
-- Component only for debugging (in order to generate seconds time)
-------------------------------------------------------------------------------
......@@ -152,7 +153,8 @@ architecture rtl of xwr_dio is
trig_utc_i : in std_logic_vector(39 downto 0);
trig_cycles_i : in std_logic_vector(27 downto 0);
trig_valid_p1_i : in std_logic;
pulse_length_i : in std_logic_vector(27 downto 0)
pulse_length_i : in std_logic_vector(27 downto 0);
pulse_period_i : in std_logic_vector(27 downto 0)
);
end component;
......@@ -476,9 +478,10 @@ architecture rtl of xwr_dio is
signal dio_tsf_tag_seconds : t_seconds_array;
signal dio_tsf_tag_cycles : t_cycles_array;
signal dio_tsf_leap_second : t_leap_seconds_array;
signal dio_tsf_leap_second_valid : std_logic_vector(5 downto 0);
-- Fifos no-empty interrupts
signal irq_nempty : std_logic_vector (4 downto 0);
signal irq_nempty : std_logic_vector (5 downto 0);
-- DEBUG SIGNALS FOR USING seconds time values from dummy_time instead WRPC
signal tm_seconds : std_logic_vector (39 downto 0);
......@@ -489,9 +492,9 @@ architecture rtl of xwr_dio is
(0 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00000000"), -- ONEWIRE
1 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00000100"), -- I2C
2 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00000200"), -- GPIO
3 => f_sdb_embed_device(c_xwr_dio_wb_sdb, x"00000300") -- DIO REGISTERS
3 => f_sdb_embed_device(c_xwr_dio_wb_sdb, x"00000400") -- DIO REGISTERS
);
constant c_diobar_sdb_address : t_wishbone_address := x"00000400";
constant c_diobar_sdb_address : t_wishbone_address := x"00000800";
signal cbar_master_in : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
......@@ -518,6 +521,9 @@ architecture rtl of xwr_dio is
signal dio_led_bot_o_ch : std_logic_vector(4 downto 0);
signal dio_prog_interrupt : std_logic;
-------------------------------------------------------------------------------
-- rtl
-------------------------------------------------------------------------------
......@@ -535,7 +541,7 @@ begin
------------------------------------------------------------------------------
-- GEN AND STAMPER
------------------------------------------------------------------------------
gen_pulse_modules : for i in 0 to 5 generate
gen_pulse_modules : for i in 0 to 4 generate
U_pulse_gen : pulse_gen_pl
port map(
clk_ref_i => clk_ref_i,
......@@ -556,7 +562,8 @@ begin
trig_utc_i => trig_seconds(i),
trig_cycles_i => trig_cycles(i),
trig_valid_p1_i => trig_valid_p1(i),
pulse_length_i => pulse_length(i)
pulse_length_i => pulse_length(i),
pulse_period_i => pulse_period(i)
);
......@@ -582,6 +589,51 @@ begin
end generate gen_pulse_modules;
U_pulse_gen : pulse_gen_pl
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_o => dio_pulse_prog(5),
-- DEBUG
-- tm_time_valid_i => '1',--tm_time_valid_i,
-- tm_utc_i => tm_seconds,--tm_utc_i,
-- tm_cycles_i => tm_cycles, --tm_cycles_i,
tm_time_valid_i => tm_time_valid_i,
tm_utc_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
trig_ready_o => trig_ready(5),
trig_utc_i => trig_seconds(5),
trig_cycles_i => trig_cycles(5),
trig_valid_p1_i => trig_valid_p1(5),
pulse_length_i => pulse_length(5),
pulse_period_i => pulse_period(5)
);
U_PULSE_STAMPER : pulse_stamper
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
pulse_a_i => dio_prog_interrupt,
-- DEBUG
-- tm_time_valid_i => '1',
-- tm_utc_i => tm_seconds,
-- tm_cycles_i => tm_cycles,
tm_time_valid_i => tm_time_valid_i,
tm_tai_i => tm_seconds_i,
tm_cycles_i => tm_cycles_i,
tag_tai_o => tag_seconds(5),
tag_cycles_o => tag_cycles(5),
tag_valid_o => tag_valid_p1(5));
------------------------------------------------------------------------------
-- PULSE TRAIN GENERATOR
------------------------------------------------------------------------------
......@@ -596,7 +648,7 @@ begin
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_i,
dio_pulse_immed_stb_i => dio_pulse_immed_stb(i),
pulse_length_i => pulse_length(i),
pulse_period_i => pulse_period(i),
pulse_output_o => dio_pulse_immed_periodic(i)
);
......@@ -738,7 +790,7 @@ begin
);
end generate immediate_output_with_pulse_length;
gen_pio_assignment : for i in 0 to 5 generate
gen_pio_assignment : for i in 0 to 4 generate
gpio_in(c_IOMODE_NB*i) <= dio_in_i(i);
dio_pulse(i) <= '1' when dio_pulse_immed(i) = '1' else dio_pulse_prog(i);
dio_oe_n_o(i) <= dio_iomode_reg(c_IOMODE_NB*i+2);
......@@ -754,6 +806,9 @@ begin
end generate gen_pio_assignment;
--New channel programmed pulse has been connected directly to the input to generate the timestamp of each interrupt
dio_prog_interrupt <= dio_pulse_prog(5) or dio_pulse_immed(5) when dio_iomode_reg(c_IOMODE_NB*5) = '1' else '0';
dio_led_top_o <= dio_iomode_reg(c_IOMODE_NB*0+3) or
dio_iomode_reg(c_IOMODE_NB*1+3) or
dio_iomode_reg(c_IOMODE_NB*2+3) or
......@@ -809,7 +864,7 @@ begin
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_dio_slave_in.adr(5 downto 0),
wb_adr_i => wb_dio_slave_in.adr(6 downto 0),
wb_dat_i => wb_dio_slave_in.dat,
wb_dat_o => wb_dio_slave_out.dat,
wb_cyc_i => wb_dio_slave_in.cyc,
......@@ -830,6 +885,7 @@ begin
dio_tsf0_tag_secondsh_i => dio_tsf_tag_seconds(0)(39 downto 32),
dio_tsf0_tag_cycles_i => dio_tsf_tag_cycles(0),
dio_tsf0_leap_second_value_i => dio_tsf_leap_second(0),
dio_tsf0_leap_second_valid_i => dio_tsf_leap_second_valid(0),
irq_nempty_0_i => irq_nempty(0),
dio_tsf1_wr_req_i => dio_tsf_wr_req(1),
......@@ -839,6 +895,7 @@ begin
dio_tsf1_tag_secondsh_i => dio_tsf_tag_seconds(1)(39 downto 32),
dio_tsf1_tag_cycles_i => dio_tsf_tag_cycles(1),
dio_tsf1_leap_second_value_i => dio_tsf_leap_second(1),
dio_tsf1_leap_second_valid_i => dio_tsf_leap_second_valid(1),
irq_nempty_1_i => irq_nempty(1),
dio_tsf2_wr_req_i => dio_tsf_wr_req(2),
......@@ -848,6 +905,7 @@ begin
dio_tsf2_tag_secondsh_i => dio_tsf_tag_seconds(2)(39 downto 32),
dio_tsf2_tag_cycles_i => dio_tsf_tag_cycles(2),
dio_tsf2_leap_second_value_i => dio_tsf_leap_second(2),
dio_tsf2_leap_second_valid_i => dio_tsf_leap_second_valid(2),
irq_nempty_2_i => irq_nempty(2),
dio_tsf3_wr_req_i => dio_tsf_wr_req(3),
......@@ -857,6 +915,7 @@ begin
dio_tsf3_tag_secondsh_i => dio_tsf_tag_seconds(3)(39 downto 32),
dio_tsf3_tag_cycles_i => dio_tsf_tag_cycles(3),
dio_tsf3_leap_second_value_i => dio_tsf_leap_second(3),
dio_tsf3_leap_second_valid_i => dio_tsf_leap_second_valid(3),
irq_nempty_3_i => irq_nempty(3),
dio_tsf4_wr_req_i => dio_tsf_wr_req(4),
......@@ -866,6 +925,7 @@ begin
dio_tsf4_tag_secondsh_i => dio_tsf_tag_seconds(4)(39 downto 32),
dio_tsf4_tag_cycles_i => dio_tsf_tag_cycles(4),
dio_tsf4_leap_second_value_i => dio_tsf_leap_second(4),
dio_tsf4_leap_second_valid_i => dio_tsf_leap_second_valid(4),
irq_nempty_4_i => irq_nempty(4),
dio_tsf5_wr_req_i => dio_tsf_wr_req(5),
......@@ -875,6 +935,7 @@ begin
dio_tsf5_tag_secondsh_i => dio_tsf_tag_seconds(5)(39 downto 32),
dio_tsf5_tag_cycles_i => dio_tsf_tag_cycles(5),
dio_tsf5_leap_second_value_i => dio_tsf_leap_second(5),
dio_tsf5_leap_second_valid_i => dio_tsf_leap_second_valid(5),
irq_nempty_5_i => irq_nempty(5),
dio_trig0_seconds_o => trig_seconds(0)(31 downto 0),
......
hdl/top/dio-common/dio_common_top.vhd
View file @ 85963c01
......@@ -349,6 +349,9 @@ architecture top of dio_common_top is
-- VIC-only signals
signal vic_only_irqs : std_logic_vector(3 downto 0);
signal dio_oe_n_o_internal : std_logic_vector(5 downto 0);
signal dio_term_en_o_internal : std_logic_vector(5 downto 0);
begin -- architecture top
......@@ -663,8 +666,8 @@ begin -- architecture top
dio_pps_i => wrc_pps_out,
dio_in_i => dio_in,
dio_out_o => dio_out,
dio_oe_n_o => dio_oe_n_o,
dio_term_en_o => dio_term_en_o,
dio_oe_n_o => dio_oe_n_o_internal,
dio_term_en_o => dio_term_en_o_internal,
dio_onewire_b => dio_onewire_b,
dio_sdn_n_o => dio_sdn_n_o,
dio_sdn_ck_n_o => dio_sdn_ck_n_o,
......@@ -679,6 +682,9 @@ begin -- architecture top
dio_int => dio_int
);
dio_oe_n_o <= dio_oe_n_o_internal(4 downto 0);
dio_term_en_o <= dio_term_en_o_internal(4 downto 0);
vic_vec_int(0) <= dio_int;
NIC_GEN : if g_dio_mode = DIO_NIC generate
......
hdl/top/dio-common/dio_common_top_pkg.vhd
View file @ 85963c01
......@@ -238,7 +238,7 @@ package dio_common_top_pkg is
constant c_nic_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0001ffff", x"00011000");
constant c_wr_dio_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_product_manual_sdb(x"00000fff", x"00000400", c_xwr_dio_sdb);
f_xwb_bridge_product_manual_sdb(x"00000fff", x"00000800", c_xwr_dio_sdb);
-- Primary wishbone crossbar layout (NIC)
constant c_NIC_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
......
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