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FMC DIO 5ch TTL a
Commit a2ff9b09 authored by Jorge Machado's avatar Jorge Machado
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Immediate pulse train generator finished. Testing is pending

parent e82c4458
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Showing with 96 additions and 19 deletions
hdl/modules/wr_dio/imm_pulse_train_gen.vhd
View file @ a2ff9b09
......@@ -23,22 +23,34 @@ use IEEE.STD_LOGIC_1164.ALL;
--use UNISIM.VComponents.all;
entity imm_pulse_train_gen is
generic(
pulse_period_width : integer := 28
);
port(
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
dio_pulse_immed_stb_i : in std_logic;
pulse_length_i : in std_logic_vector(pulse_length_width-1 downto 0);
pulse_period_i : in std_logic_vector(pulse_period_width-1 downto 0);
pulse_output_o : out std_logic
);
end imm_pulse_train_gen;
architecture Behavioral of imm_pulse_train_gen is
signal nozerolength, nozerolength_aux : boolean;
signal nozeroperiod, nozeroperiod_aux : boolean;
signal dio_pulse_immed_stb_d0, dio_pulse_immed_stb_d1,
dio_pulse_immed_stb_d2, dio_pulse_immed_stb_d3 : std_logic;
-- Internal registers to hold pulse duration
signal counter : unsigned (pulse_period_width-1 downto 0);
-- Signals for states
type counter_state is (WAIT_ST, COUNTING, CAPTURE_PERIOD, TRIGGER);
signal state : counter_state;
signal repeat_pulse : std_logic;
begin
synchronization : process(clk_i, rst_n_i)
......@@ -53,12 +65,71 @@ begin
dio_pulse_immed_stb_d1 <= dio_pulse_immed_stb_d0;
dio_pulse_immed_stb_d2 <= dio_pulse_immed_stb_d1;
dio_pulse_immed_stb_d3 <= dio_pulse_immed_stb_d2;
nozerolength_aux <= pulse_length_i /= zeros;
if (dio_pulse_immed_stb_d2 = '1' and dio_pulse_immed_stb_d1 = '0') then
nozerolength <= nozerolength_aux;
nozeroperiod_aux <= pulse_period_i /= zeros;
-- Update nozeroperiod each period while the state machine is counting
if ((dio_pulse_immed_stb_d2 = '1' and dio_pulse_immed_stb_d1 = '0') or (state = CAPTURE_PERIOD)) then
nozeroperiod <= nozeroperiod_aux;
end if;
end if;
end process;
state_process : process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
counter <= (others => '0');
state <= WAIT_ST;
repeat_pulse <= '0';
elsif rising_edge(clk_i) then
case state is
when WAIT_ST =>
if (dio_pulse_immed_stb_d3 = '1' or repeat_pulse = '1') and nozeroperiod then
state <= COUNTING;
--Store the period two cycle before than the immed_pulse_counter_process to not lost one cycle.
counter <= unsigned(pulse_period)-3;
else
state <= WAIT_ST;
end if;
when COUNTING =>
if (counter = 0) then
state <= CAPTURE_PERIOD;
else
state <= COUNTING;
counter <= counter-1;
end if;
when CAPTURE_PERIOD =>
state <= TRIGGER;
when TRIGGER =>
state <= WAIT_ST;
if(nozeroperiod) then
repeat_pulse <= '1';
else
repeat_pulse <= '0';
end if;
when others =>
state <= WAIT_ST;
end case;
end if;
end process;
output_process : process(counter, state)
begin
if (rst_n_i = '0') then
pulse_output_o <= '0';
else
case state is
when WAIT_ST =>
pulse_output_o <= '0';
when COUNTING =>
pulse_output_o <= '0';
when TRIGGER =>
pulse_output_o <= '1';
when others =>
pulse_output_o <= '0';
end case;
end if;
end process;
end Behavioral;
hdl/modules/wr_dio/xwr_dio.vhd
View file @ a2ff9b09
......@@ -210,13 +210,16 @@ architecture rtl of xwr_dio is
end component;
component imm_pulse_train_gen
port(
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
dio_pulse_immed_stb_i : in std_logic;
pulse_length_i : in std_logic_vector(pulse_length_width-1 downto 0);
pulse_output_o : out std_logic
);
generic(
pulse_period_width : integer := 28
);
port(
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
dio_pulse_immed_stb_i : in std_logic;
pulse_period_i : in std_logic_vector(pulse_period_width-1 downto 0);
pulse_output_o : out std_logic
);
end component;
component wr_dio_wb is
......@@ -586,13 +589,16 @@ begin
gen_pulse_train_modules : for i in 0 to 5 generate
U_imm_pulse_train_gen : imm_pulse_train_gen
port map(
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_i,
dio_pulse_immed_stb_i => dio_pulse_immed_stb(i),
pulse_length_i => pulse_length(i),
pulse_output_o => dio_pulse_immed_periodic(i)
);
generic map(
pulse_period_width => 28
)
port map(
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_i,
dio_pulse_immed_stb_i => dio_pulse_immed_stb(i),
pulse_length_i => pulse_length(i),
pulse_output_o => dio_pulse_immed_periodic(i)
);
end generate gen_pulse_train_modules;
......
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