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FMC DIO 5ch TTL a
Commit 37e705b5 authored by Jorge Machado's avatar Jorge Machado
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Update WB and package files

parent 31e53528
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hdl/modules/wr_dio/wr_dio.wb
View file @ 37e705b5
......@@ -34,6 +34,9 @@ peripheral {
hdl_entity="wr_dio_wb";
-- Version info for wbgen2
version=2;
----------------------------------------------------
-- FIFOS & INTERRUPTS FOR INPUT EVENT TIME STAMPING
----------------------------------------------------
......@@ -47,7 +50,9 @@ peripheral {
name = "Timestamp FIFO 0";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - seconds time\
- tag_cycles - counter value for sub-second accuracy";
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
- leap_second_valid - LeapSecond valid flag";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
......@@ -76,6 +81,22 @@ peripheral {
size = 28;
};
field {
name = "LeapSecond value";
description = "LeapSecond value synchronized with PPS";
prefix = "leap_second_value";
type = SLV;
size = 16;
};
field {
name = "LeapSecond valid";
description = "LeapSecond valid";
prefix = "leap_second_valid";
type = BIT;
};
};
-- CHANNEL 0 INTERRUPTS
......@@ -95,7 +116,9 @@ peripheral {
name = "Timestamp FIFO 1";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
- leap_second_valid - LeapSecond valid flag";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
......@@ -124,6 +147,21 @@ peripheral {
size = 28;
};
field {
name = "LeapSecond value";
description = "LeapSecond value synchronized with PPS";
prefix = "leap_second_value";
type = SLV;
size = 16;
};
field {
name = "LeapSecond valid";
description = "LeapSecond valid";
prefix = "leap_second_valid";
type = BIT;
};
};
-- CHANNEL 1 INTERRUPTS
......@@ -134,6 +172,7 @@ peripheral {
trigger = LEVEL_1;
};
-- CHANNEL 2 INPUT FIFO
fifo_reg {
......@@ -143,7 +182,9 @@ peripheral {
name = "Timestamp FIFO 2";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
- leap_second_valid - LeapSecond valid flag";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
......@@ -172,6 +213,20 @@ peripheral {
size = 28;
};
field {
name = "LeapSecond value";
description = "LeapSecond value synchronized with PPS";
prefix = "leap_second_value";
type = SLV;
size = 16;
};
field {
name = "LeapSecond valid";
description = "LeapSecond valid";
prefix = "leap_second_valid";
type = BIT;
};
};
-- CHANNEL 2 INTERRUPTS
......@@ -182,6 +237,7 @@ peripheral {
trigger = LEVEL_1;
};
-- CHANNEL 3 INPUT FIFO
fifo_reg {
......@@ -191,7 +247,9 @@ peripheral {
name = "Timestamp FIFO 3";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
- leap_second_valid - LeapSecond valid flag";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
......@@ -220,6 +278,20 @@ peripheral {
size = 28;
};
field {
name = "LeapSecond value";
description = "LeapSecond value synchronized with PPS";
prefix = "leap_second_value";
type = SLV;
size = 16;
};
field {
name = "LeapSecond valid";
description = "LeapSecond valid";
prefix = "leap_second_valid";
type = BIT;
};
};
-- CHANNEL 3 INTERRUPTS
......@@ -230,6 +302,7 @@ peripheral {
trigger = LEVEL_1;
};
-- CHANNEL 4 INPUT FIFO
fifo_reg {
......@@ -239,7 +312,9 @@ peripheral {
name = "Timestamp FIFO 4";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy";
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
- leap_second_valid - LeapSecond valid flag";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
......@@ -268,6 +343,20 @@ peripheral {
size = 28;
};
field {
name = "LeapSecond value";
description = "LeapSecond value synchronized with PPS";
prefix = "leap_second_value";
type = SLV;
size = 16;
};
field {
name = "LeapSecond valid";
description = "LeapSecond valid";
prefix = "leap_second_valid";
type = BIT;
};
};
-- CHANNEL 4 INTERRUPTS
......@@ -278,6 +367,71 @@ peripheral {
trigger = LEVEL_1;
};
-- CHANNEL 5 INPUT FIFO (IRQ)
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf5";
name = "Timestamp FIFO 5";
description = "This FIFO holds the DIO input timestamps for each input channel. Each entry contains a single timestamp value consisting of 2 numbers:\
- tag_seconds - time in seconds\
- tag_cycles - counter value for sub-second accuracy\
- leap_second_value - LeapSecond value\
- leap_second_valid - LeapSecond valid flag";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "seconds time";
descritpion = "time in seconds (LSB)";
prefix = "tag_seconds";
type = SLV;
size = 32;
};
field {
name = "seconds time H";
descritpion = "time in seconds (MSB)";
prefix = "tag_secondsH";
type = SLV;
size = 8;
};
field {
name = "Sub-second accuracy";
descritpion = "Sub-second accuracy based on systme clock counters";
prefix = "tag_cycles";
type = SLV;
size = 28;
};
field {
name = "LeapSecond value";
description = "LeapSecond value synchronized with PPS";
prefix = "leap_second_value";
type = SLV;
size = 16;
};
field {
name = "LeapSecond valid";
description = "LeapSecond valid";
prefix = "leap_second_valid";
type = BIT;
};
};
-- CHANNEL 5 INTERRUPTS
irq {
name = "dio fifo not-empty 5";
description = "Interrupt active when dio input FIFO contains any timestamps.";
prefix = "nempty_5";
trigger = LEVEL_1;
};
-------------------------------------------------
-- REGISTERS FOR OUTPUT EVENT TIME-BASED TRIGGER
-------------------------------------------------
......@@ -527,6 +681,55 @@ peripheral {
};
};
-- DIO CHANNEL 5 (IRQ): seconds value . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 5 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (LSB).";
prefix = "trig5";
field {
name = "seconds field";
description = "TBD";
prefix = "seconds";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "fmc-dio 5 seconds-based trigger for pulse generation";
description = "trigger seconds value for dio output (MSB).";
prefix = "trigH5";
field {
name = "seconds field";
description = "Number of seconds";
prefix = "seconds";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 5 (IRQ): Cycles value. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio 5 cycles to trigger a pulse generation";
description = "sub-second accuracy values (clock cycles) to trigger dio output channels.";
prefix = "cyc5";
field {
name = "cycles field";
description = "Number of cycles in one second (depends on current clock frequency)";
prefix = "cyc";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-----------------------------------------
-- OUTPUT CONFIGURATION/CONTROL REGISTERS
-----------------------------------------
......@@ -534,10 +737,13 @@ peripheral {
-- Programmable IO mode selection
reg {
name = "FMC-DIO input/output configuration register. ";
description = "It allows to choose the I/0 mode for each channel. \
description = "It allows to choose the I/0 mode for each channel (CH0-CH4). \
- [0-1]: The two first bit correspond to which signal its connected: 0 (00) GPIO, 1 (01) DIO core, 2 (10) WRPC core, 3 Undefined\
- [2]: Output Enable Negative (Input enable)\
- [3]: 50 Ohm termination enable";
- [3]: 50 Ohm termination enable\
CH5 is a special one whose configuration is:\
- [0]: Enable/Disable channel for IRQ\
- [3-1]: Undefined";
prefix = "iomode";
field {
name = "channel0";
......@@ -589,6 +795,16 @@ peripheral {
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "channel5";
description = "Channel 5: Special channel for programmable IRQ";
prefix = "ch5";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
-- Single-cycle strobe signal to latch the second/cycles values of the programamble output
......@@ -627,6 +843,12 @@ peripheral {
prefix = "time_ch4";
type = MONOSTABLE;
};
field {
name = "Sincle-cycle strobe";
description = "It generates a one-clock cycle pulse for programmable time latching";
prefix = "time_ch5";
type = MONOSTABLE;
};
};
-- seconds trigger ready value. Readable-writable the bus, writable from the device.
......@@ -640,7 +862,7 @@ peripheral {
description = "TBD";
prefix = "rdy";
type = SLV;
size = 5;
size = 6;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -681,6 +903,13 @@ peripheral {
prefix = "trigger_ready_4";
trigger = LEVEL_1;
};
-- DIO CHANNEL 5 trigger ready interrupt
irq {
name = "Channel 5 trigger ready interrupt";
description = "Interrupt active when time-programmable output channels accept new time trigger command.";
prefix = "trigger_ready_5";
trigger = LEVEL_1;
};
-- DIO CHANNEL 0: Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
......@@ -699,6 +928,22 @@ peripheral {
};
};
-- DIO CHANNEL 0: Programmable/immediate output pulse period. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 0 Programmable/immediate output pulse period";
description = "Number of clk_ref clock ticks for pulse period";
prefix = "prog0_pulse_per";
field {
name = "number of ticks (period) field for channel 0";
description = "ticks number (period)";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 1: Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 1 Programmable/immediate output pulse length";
......@@ -715,6 +960,23 @@ peripheral {
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 1: Programmable/immediate output pulse period. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 1 Programmable/immediate output pulse period";
description = "Number of clk_ref clock ticks for pulse period";
prefix = "prog1_pulse_per";
field {
name = "number of ticks (period) field for channel 1";
description = "ticks number (period)";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 2: Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 2 Programmable/immediate output pulse length";
......@@ -731,6 +993,23 @@ peripheral {
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 2: Programmable/immediate output pulse period. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 2 Programmable/immediate output pulse period";
description = "Number of clk_ref clock ticks for pulse period";
prefix = "prog2_pulse_per";
field {
name = "number of ticks (period) field for channel 2";
description = "ticks number (period)";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 3: Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 3 Programmable/immediate output pulse length";
......@@ -747,6 +1026,23 @@ peripheral {
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 3: Programmable/immediate output pulse period. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 3 Programmable/immediate output pulse period";
description = "Number of clk_ref clock ticks for pulse period";
prefix = "prog3_pulse_per";
field {
name = "number of ticks (period) field for channel 3";
description = "ticks number (period)";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 4: Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 4 Programmable/immediate output pulse length";
......@@ -764,6 +1060,54 @@ peripheral {
};
};
-- DIO CHANNEL 4: Programmable/immediate output pulse period. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 4 Programmable/immediate output pulse period";
description = "Number of clk_ref clock ticks for pulse period";
prefix = "prog4_pulse_per";
field {
name = "number of ticks (period) field for channel 4";
description = "ticks number (period)";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 5 (IRQ): Programmable/immediate output pulse length . Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 5 Programmable/immediate output pulse length";
description = "Number of clk_ref clock ticks that output will be active";
prefix = "prog5_pulse";
field {
name = "number of ticks field for channel 5";
description = "ticks number";
prefix = "length";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- DIO CHANNEL 5 (IRQ): Programmable/immediate output pulse period. Readable-writable the bus, readble from the device.
reg {
name = "fmc-dio channel 5 Programmable/immediate output pulse period";
description = "Number of clk_ref clock ticks for pulse period";
prefix = "prog5_pulse_per";
field {
name = "number of ticks (period) field for channel 5";
description = "ticks number (period)";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-----------------------------------------
-- IMMEDIATE OUTPUT REGISTERS
......@@ -810,7 +1154,12 @@ peripheral {
type = MONOSTABLE;
clock = "clk_asyn_i";
};
field {
name = "pulse_gen_now_5";
description = "It generates a pulse";
prefix = "imm_5";
type = MONOSTABLE;
clock = "clk_asyn_i";
};
};
};
\ No newline at end of file
hdl/modules/wr_dio/wr_dio_pkg.vhd
View file @ 37e705b5
......@@ -70,10 +70,10 @@ package wr_dio_pkg is
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
addr_last => x"00000000000003ff",
product => (
vendor_id => x"00000000000075CB", -- SEVEN SOLUTIONS
device_id => x"00000001",
device_id => x"00000003",
version => x"00000002",
date => x"20120709",
name => "WR-DIO-Registers ")));
......
hdl/modules/wr_dio/wr_dio_wb.vhd
View file @ 37e705b5
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC-DIO-5chttla
---------------------------------------------------------------------------------------
-- File : wr_dio_wb.vhd
-- File : ./wr_dio_wb.vhd
-- Author : auto-generated by wbgen2 from wr_dio.wb
-- Created : Wed May 8 14:07:08 2013
-- Created : Tue Apr 28 15:59:03 2020
-- Version : 0x00000002
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_dio.wb
......@@ -19,7 +20,7 @@ entity wr_dio_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -27,9 +28,13 @@ entity wr_dio_wb is
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_asyn_i : in std_logic;
-- Port for std_logic_vector field: 'Version identifier' in reg: 'Version register'
dio_ver_id_o : out std_logic_vector(31 downto 0);
-- FIFO write request
dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag
......@@ -39,6 +44,8 @@ entity wr_dio_wb is
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf0_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf0_leap_second_valid_i : in std_logic;
irq_nempty_0_i : in std_logic;
-- FIFO write request
dio_tsf1_wr_req_i : in std_logic;
......@@ -49,6 +56,8 @@ entity wr_dio_wb is
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf1_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf1_leap_second_valid_i : in std_logic;
irq_nempty_1_i : in std_logic;
-- FIFO write request
dio_tsf2_wr_req_i : in std_logic;
......@@ -59,6 +68,8 @@ entity wr_dio_wb is
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf2_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf2_leap_second_valid_i : in std_logic;
irq_nempty_2_i : in std_logic;
-- FIFO write request
dio_tsf3_wr_req_i : in std_logic;
......@@ -69,6 +80,8 @@ entity wr_dio_wb is
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf3_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf3_leap_second_valid_i : in std_logic;
irq_nempty_3_i : in std_logic;
-- FIFO write request
dio_tsf4_wr_req_i : in std_logic;
......@@ -79,7 +92,21 @@ entity wr_dio_wb is
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf4_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf4_leap_second_valid_i : in std_logic;
irq_nempty_4_i : in std_logic;
-- FIFO write request
dio_tsf5_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf5_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf5_wr_empty_o : out std_logic;
dio_tsf5_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf5_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf5_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf5_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf5_leap_second_valid_i : in std_logic;
irq_nempty_5_i : in std_logic;
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
......@@ -110,6 +137,12 @@ entity wr_dio_wb is
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 5 seconds-based trigger for pulse generation'
dio_trig5_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 5 seconds-based trigger for pulse generation'
dio_trigh5_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 5 cycles to trigger a pulse generation'
dio_cyc5_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'channel0' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch0_o : out std_logic_vector(3 downto 0);
dio_iomode_ch0_i : in std_logic_vector(3 downto 0);
......@@ -130,6 +163,10 @@ entity wr_dio_wb is
dio_iomode_ch4_o : out std_logic_vector(3 downto 0);
dio_iomode_ch4_i : in std_logic_vector(3 downto 0);
dio_iomode_ch4_load_o : out std_logic;
-- Port for std_logic_vector field: 'channel5' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch5_o : out std_logic_vector(3 downto 0);
dio_iomode_ch5_i : in std_logic_vector(3 downto 0);
dio_iomode_ch5_load_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
......@@ -140,23 +177,40 @@ entity wr_dio_wb is
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch5_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO time trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(4 downto 0);
dio_trig_rdy_i : in std_logic_vector(5 downto 0);
irq_trigger_ready_0_i : in std_logic;
irq_trigger_ready_1_i : in std_logic;
irq_trigger_ready_2_i : in std_logic;
irq_trigger_ready_3_i : in std_logic;
irq_trigger_ready_4_i : in std_logic;
irq_trigger_ready_5_i : in std_logic;
-- Port for std_logic_vector field: 'number of ticks field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse length'
dio_prog0_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse period'
dio_prog0_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse length'
dio_prog1_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse period'
dio_prog1_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse length'
dio_prog2_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse period'
dio_prog2_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse length'
dio_prog3_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse period'
dio_prog3_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse length'
dio_prog4_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse period'
dio_prog4_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 5' in reg: 'fmc-dio channel 5 Programmable/immediate output pulse length'
dio_prog5_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 5' in reg: 'fmc-dio channel 5 Programmable/immediate output pulse period'
dio_prog5_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_pulse_imm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
......@@ -166,136 +220,159 @@ entity wr_dio_wb is
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_pulse_imm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_pulse_imm_4_o : out std_logic
dio_pulse_imm_4_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_5' in reg: 'Pulse generate immediately'
dio_pulse_imm_5_o : out std_logic
);
end wr_dio_wb;
architecture syn of wr_dio_wb is
signal dio_tsf0_rst_n : std_logic;
signal dio_tsf0_in_int : std_logic_vector(67 downto 0);
signal dio_tsf0_out_int : std_logic_vector(67 downto 0);
signal dio_tsf0_rdreq_int : std_logic;
signal dio_tsf0_rdreq_int_d0 : std_logic;
signal dio_tsf1_rst_n : std_logic;
signal dio_tsf1_in_int : std_logic_vector(67 downto 0);
signal dio_tsf1_out_int : std_logic_vector(67 downto 0);
signal dio_tsf1_rdreq_int : std_logic;
signal dio_tsf1_rdreq_int_d0 : std_logic;
signal dio_tsf2_rst_n : std_logic;
signal dio_tsf2_in_int : std_logic_vector(67 downto 0);
signal dio_tsf2_out_int : std_logic_vector(67 downto 0);
signal dio_tsf2_rdreq_int : std_logic;
signal dio_tsf2_rdreq_int_d0 : std_logic;
signal dio_tsf3_rst_n : std_logic;
signal dio_tsf3_in_int : std_logic_vector(67 downto 0);
signal dio_tsf3_out_int : std_logic_vector(67 downto 0);
signal dio_tsf3_rdreq_int : std_logic;
signal dio_tsf3_rdreq_int_d0 : std_logic;
signal dio_tsf4_rst_n : std_logic;
signal dio_tsf4_in_int : std_logic_vector(67 downto 0);
signal dio_tsf4_out_int : std_logic_vector(67 downto 0);
signal dio_tsf4_rdreq_int : std_logic;
signal dio_tsf4_rdreq_int_d0 : std_logic;
signal dio_trig0_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh0_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc0_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig1_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh1_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc1_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig2_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh2_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc2_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig3_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh3_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc3_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig4_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh4_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc4_cyc_int : std_logic_vector(27 downto 0);
signal dio_latch_time_ch0_dly0 : std_logic;
signal dio_latch_time_ch0_int : std_logic;
signal dio_latch_time_ch1_dly0 : std_logic;
signal dio_latch_time_ch1_int : std_logic;
signal dio_latch_time_ch2_dly0 : std_logic;
signal dio_latch_time_ch2_int : std_logic;
signal dio_latch_time_ch3_dly0 : std_logic;
signal dio_latch_time_ch3_int : std_logic;
signal dio_latch_time_ch4_dly0 : std_logic;
signal dio_latch_time_ch4_int : std_logic;
signal dio_prog0_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog1_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog2_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog3_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog4_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_pulse_imm_0_int : std_logic;
signal dio_pulse_imm_0_int_delay : std_logic;
signal dio_pulse_imm_0_sync0 : std_logic;
signal dio_pulse_imm_0_sync1 : std_logic;
signal dio_pulse_imm_0_sync2 : std_logic;
signal dio_pulse_imm_1_int : std_logic;
signal dio_pulse_imm_1_int_delay : std_logic;
signal dio_pulse_imm_1_sync0 : std_logic;
signal dio_pulse_imm_1_sync1 : std_logic;
signal dio_pulse_imm_1_sync2 : std_logic;
signal dio_pulse_imm_2_int : std_logic;
signal dio_pulse_imm_2_int_delay : std_logic;
signal dio_pulse_imm_2_sync0 : std_logic;
signal dio_pulse_imm_2_sync1 : std_logic;
signal dio_pulse_imm_2_sync2 : std_logic;
signal dio_pulse_imm_3_int : std_logic;
signal dio_pulse_imm_3_int_delay : std_logic;
signal dio_pulse_imm_3_sync0 : std_logic;
signal dio_pulse_imm_3_sync1 : std_logic;
signal dio_pulse_imm_3_sync2 : std_logic;
signal dio_pulse_imm_4_int : std_logic;
signal dio_pulse_imm_4_int_delay : std_logic;
signal dio_pulse_imm_4_sync0 : std_logic;
signal dio_pulse_imm_4_sync1 : std_logic;
signal dio_pulse_imm_4_sync2 : std_logic;
signal eic_idr_int : std_logic_vector(9 downto 0);
signal eic_idr_write_int : std_logic;
signal eic_ier_int : std_logic_vector(9 downto 0);
signal eic_ier_write_int : std_logic;
signal eic_imr_int : std_logic_vector(9 downto 0);
signal eic_isr_clear_int : std_logic_vector(9 downto 0);
signal eic_isr_status_int : std_logic_vector(9 downto 0);
signal eic_irq_ack_int : std_logic_vector(9 downto 0);
signal eic_isr_write_int : std_logic;
signal dio_tsf0_full_int : std_logic;
signal dio_tsf0_empty_int : std_logic;
signal dio_tsf0_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf1_full_int : std_logic;
signal dio_tsf1_empty_int : std_logic;
signal dio_tsf1_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf2_full_int : std_logic;
signal dio_tsf2_empty_int : std_logic;
signal dio_tsf2_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf3_full_int : std_logic;
signal dio_tsf3_empty_int : std_logic;
signal dio_tsf3_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf4_full_int : std_logic;
signal dio_tsf4_empty_int : std_logic;
signal dio_tsf4_usedw_int : std_logic_vector(7 downto 0);
signal irq_inputs_vector_int : std_logic_vector(9 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(5 downto 0);
signal ack_in_progress : std_logic;
signal wr_int : std_logic;
signal rd_int : std_logic;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
signal dio_ver_id_int : std_logic_vector(31 downto 0);
signal dio_tsf0_rst_n : std_logic ;
signal dio_tsf0_in_int : std_logic_vector(84 downto 0);
signal dio_tsf0_out_int : std_logic_vector(84 downto 0);
signal dio_tsf0_rdreq_int : std_logic ;
signal dio_tsf0_rdreq_int_d0 : std_logic ;
signal dio_tsf1_rst_n : std_logic ;
signal dio_tsf1_in_int : std_logic_vector(84 downto 0);
signal dio_tsf1_out_int : std_logic_vector(84 downto 0);
signal dio_tsf1_rdreq_int : std_logic ;
signal dio_tsf1_rdreq_int_d0 : std_logic ;
signal dio_tsf2_rst_n : std_logic ;
signal dio_tsf2_in_int : std_logic_vector(84 downto 0);
signal dio_tsf2_out_int : std_logic_vector(84 downto 0);
signal dio_tsf2_rdreq_int : std_logic ;
signal dio_tsf2_rdreq_int_d0 : std_logic ;
signal dio_tsf3_rst_n : std_logic ;
signal dio_tsf3_in_int : std_logic_vector(84 downto 0);
signal dio_tsf3_out_int : std_logic_vector(84 downto 0);
signal dio_tsf3_rdreq_int : std_logic ;
signal dio_tsf3_rdreq_int_d0 : std_logic ;
signal dio_tsf4_rst_n : std_logic ;
signal dio_tsf4_in_int : std_logic_vector(84 downto 0);
signal dio_tsf4_out_int : std_logic_vector(84 downto 0);
signal dio_tsf4_rdreq_int : std_logic ;
signal dio_tsf4_rdreq_int_d0 : std_logic ;
signal dio_tsf5_rst_n : std_logic ;
signal dio_tsf5_in_int : std_logic_vector(84 downto 0);
signal dio_tsf5_out_int : std_logic_vector(84 downto 0);
signal dio_tsf5_rdreq_int : std_logic ;
signal dio_tsf5_rdreq_int_d0 : std_logic ;
signal dio_trig0_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh0_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc0_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig1_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh1_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc1_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig2_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh2_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc2_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig3_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh3_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc3_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig4_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh4_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc4_cyc_int : std_logic_vector(27 downto 0);
signal dio_trig5_seconds_int : std_logic_vector(31 downto 0);
signal dio_trigh5_seconds_int : std_logic_vector(7 downto 0);
signal dio_cyc5_cyc_int : std_logic_vector(27 downto 0);
signal dio_latch_time_ch0_dly0 : std_logic ;
signal dio_latch_time_ch0_int : std_logic ;
signal dio_latch_time_ch1_dly0 : std_logic ;
signal dio_latch_time_ch1_int : std_logic ;
signal dio_latch_time_ch2_dly0 : std_logic ;
signal dio_latch_time_ch2_int : std_logic ;
signal dio_latch_time_ch3_dly0 : std_logic ;
signal dio_latch_time_ch3_int : std_logic ;
signal dio_latch_time_ch4_dly0 : std_logic ;
signal dio_latch_time_ch4_int : std_logic ;
signal dio_latch_time_ch5_dly0 : std_logic ;
signal dio_latch_time_ch5_int : std_logic ;
signal dio_prog0_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog0_pulse_per_int : std_logic_vector(27 downto 0);
signal dio_prog1_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog1_pulse_per_int : std_logic_vector(27 downto 0);
signal dio_prog2_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog2_pulse_per_int : std_logic_vector(27 downto 0);
signal dio_prog3_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog3_pulse_per_int : std_logic_vector(27 downto 0);
signal dio_prog4_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog4_pulse_per_int : std_logic_vector(27 downto 0);
signal dio_prog5_pulse_length_int : std_logic_vector(27 downto 0);
signal dio_prog5_pulse_per_int : std_logic_vector(27 downto 0);
signal dio_pulse_imm_0_int : std_logic ;
signal dio_pulse_imm_0_int_delay : std_logic ;
signal dio_pulse_imm_0_sync0 : std_logic ;
signal dio_pulse_imm_0_sync1 : std_logic ;
signal dio_pulse_imm_0_sync2 : std_logic ;
signal dio_pulse_imm_1_int : std_logic ;
signal dio_pulse_imm_1_int_delay : std_logic ;
signal dio_pulse_imm_1_sync0 : std_logic ;
signal dio_pulse_imm_1_sync1 : std_logic ;
signal dio_pulse_imm_1_sync2 : std_logic ;
signal dio_pulse_imm_2_int : std_logic ;
signal dio_pulse_imm_2_int_delay : std_logic ;
signal dio_pulse_imm_2_sync0 : std_logic ;
signal dio_pulse_imm_2_sync1 : std_logic ;
signal dio_pulse_imm_2_sync2 : std_logic ;
signal dio_pulse_imm_3_int : std_logic ;
signal dio_pulse_imm_3_int_delay : std_logic ;
signal dio_pulse_imm_3_sync0 : std_logic ;
signal dio_pulse_imm_3_sync1 : std_logic ;
signal dio_pulse_imm_3_sync2 : std_logic ;
signal dio_pulse_imm_4_int : std_logic ;
signal dio_pulse_imm_4_int_delay : std_logic ;
signal dio_pulse_imm_4_sync0 : std_logic ;
signal dio_pulse_imm_4_sync1 : std_logic ;
signal dio_pulse_imm_4_sync2 : std_logic ;
signal dio_pulse_imm_5_int : std_logic ;
signal dio_pulse_imm_5_int_delay : std_logic ;
signal dio_pulse_imm_5_sync0 : std_logic ;
signal dio_pulse_imm_5_sync1 : std_logic ;
signal dio_pulse_imm_5_sync2 : std_logic ;
signal eic_idr_int : std_logic_vector(11 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(11 downto 0);
signal eic_ier_write_int : std_logic ;
signal eic_imr_int : std_logic_vector(11 downto 0);
signal eic_isr_clear_int : std_logic_vector(11 downto 0);
signal eic_isr_status_int : std_logic_vector(11 downto 0);
signal eic_irq_ack_int : std_logic_vector(11 downto 0);
signal eic_isr_write_int : std_logic ;
signal dio_tsf0_full_int : std_logic ;
signal dio_tsf0_empty_int : std_logic ;
signal dio_tsf0_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf1_full_int : std_logic ;
signal dio_tsf1_empty_int : std_logic ;
signal dio_tsf1_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf2_full_int : std_logic ;
signal dio_tsf2_empty_int : std_logic ;
signal dio_tsf2_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf3_full_int : std_logic ;
signal dio_tsf3_empty_int : std_logic ;
signal dio_tsf3_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf4_full_int : std_logic ;
signal dio_tsf4_empty_int : std_logic ;
signal dio_tsf4_usedw_int : std_logic_vector(7 downto 0);
signal dio_tsf5_full_int : std_logic ;
signal dio_tsf5_empty_int : std_logic ;
signal dio_tsf5_usedw_int : std_logic_vector(7 downto 0);
signal irq_inputs_vector_int : std_logic_vector(11 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(6 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -304,6 +381,7 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dio_ver_id_int <= "00000000000000000000000000000010";
dio_trig0_seconds_int <= "00000000000000000000000000000000";
dio_trigh0_seconds_int <= "00000000";
dio_cyc0_cyc_int <= "0000000000000000000000000000";
......@@ -319,21 +397,33 @@ begin
dio_trig4_seconds_int <= "00000000000000000000000000000000";
dio_trigh4_seconds_int <= "00000000";
dio_cyc4_cyc_int <= "0000000000000000000000000000";
dio_trig5_seconds_int <= "00000000000000000000000000000000";
dio_trigh5_seconds_int <= "00000000";
dio_cyc5_cyc_int <= "0000000000000000000000000000";
dio_iomode_ch0_load_o <= '0';
dio_iomode_ch1_load_o <= '0';
dio_iomode_ch2_load_o <= '0';
dio_iomode_ch3_load_o <= '0';
dio_iomode_ch4_load_o <= '0';
dio_iomode_ch5_load_o <= '0';
dio_latch_time_ch0_int <= '0';
dio_latch_time_ch1_int <= '0';
dio_latch_time_ch2_int <= '0';
dio_latch_time_ch3_int <= '0';
dio_latch_time_ch4_int <= '0';
dio_latch_time_ch5_int <= '0';
dio_prog0_pulse_length_int <= "0000000000000000000000000000";
dio_prog0_pulse_per_int <= "0000000000000000000000000000";
dio_prog1_pulse_length_int <= "0000000000000000000000000000";
dio_prog1_pulse_per_int <= "0000000000000000000000000000";
dio_prog2_pulse_length_int <= "0000000000000000000000000000";
dio_prog2_pulse_per_int <= "0000000000000000000000000000";
dio_prog3_pulse_length_int <= "0000000000000000000000000000";
dio_prog3_pulse_per_int <= "0000000000000000000000000000";
dio_prog4_pulse_length_int <= "0000000000000000000000000000";
dio_prog4_pulse_per_int <= "0000000000000000000000000000";
dio_prog5_pulse_length_int <= "0000000000000000000000000000";
dio_prog5_pulse_per_int <= "0000000000000000000000000000";
dio_pulse_imm_0_int <= '0';
dio_pulse_imm_0_int_delay <= '0';
dio_pulse_imm_1_int <= '0';
......@@ -344,6 +434,8 @@ begin
dio_pulse_imm_3_int_delay <= '0';
dio_pulse_imm_4_int <= '0';
dio_pulse_imm_4_int_delay <= '0';
dio_pulse_imm_5_int <= '0';
dio_pulse_imm_5_int_delay <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -352,6 +444,7 @@ begin
dio_tsf2_rdreq_int <= '0';
dio_tsf3_rdreq_int <= '0';
dio_tsf4_rdreq_int <= '0';
dio_tsf5_rdreq_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -363,11 +456,13 @@ begin
dio_iomode_ch2_load_o <= '0';
dio_iomode_ch3_load_o <= '0';
dio_iomode_ch4_load_o <= '0';
dio_iomode_ch5_load_o <= '0';
dio_latch_time_ch0_int <= '0';
dio_latch_time_ch1_int <= '0';
dio_latch_time_ch2_int <= '0';
dio_latch_time_ch3_int <= '0';
dio_latch_time_ch4_int <= '0';
dio_latch_time_ch5_int <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -378,6 +473,7 @@ begin
dio_iomode_ch2_load_o <= '0';
dio_iomode_ch3_load_o <= '0';
dio_iomode_ch4_load_o <= '0';
dio_iomode_ch5_load_o <= '0';
dio_pulse_imm_0_int <= dio_pulse_imm_0_int_delay;
dio_pulse_imm_0_int_delay <= '0';
dio_pulse_imm_1_int <= dio_pulse_imm_1_int_delay;
......@@ -388,18 +484,27 @@ begin
dio_pulse_imm_3_int_delay <= '0';
dio_pulse_imm_4_int <= dio_pulse_imm_4_int_delay;
dio_pulse_imm_4_int_delay <= '0';
dio_pulse_imm_5_int <= dio_pulse_imm_5_int_delay;
dio_pulse_imm_5_int_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(5 downto 0) is
when "000000" =>
case rwaddr_reg(6 downto 0) is
when "0000000" =>
if (wb_we_i = '1') then
dio_ver_id_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_ver_id_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0000001" =>
if (wb_we_i = '1') then
dio_trig0_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig0_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000001" =>
when "0000010" =>
if (wb_we_i = '1') then
dio_trigh0_seconds_int <= wrdata_reg(7 downto 0);
end if;
......@@ -430,7 +535,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000010" =>
when "0000011" =>
if (wb_we_i = '1') then
dio_cyc0_cyc_int <= wrdata_reg(27 downto 0);
end if;
......@@ -441,14 +546,14 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000011" =>
when "0000100" =>
if (wb_we_i = '1') then
dio_trig1_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig1_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000100" =>
when "0000101" =>
if (wb_we_i = '1') then
dio_trigh1_seconds_int <= wrdata_reg(7 downto 0);
end if;
......@@ -479,7 +584,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000101" =>
when "0000110" =>
if (wb_we_i = '1') then
dio_cyc1_cyc_int <= wrdata_reg(27 downto 0);
end if;
......@@ -490,14 +595,14 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000110" =>
when "0000111" =>
if (wb_we_i = '1') then
dio_trig2_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig2_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
when "0001000" =>
if (wb_we_i = '1') then
dio_trigh2_seconds_int <= wrdata_reg(7 downto 0);
end if;
......@@ -528,7 +633,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001000" =>
when "0001001" =>
if (wb_we_i = '1') then
dio_cyc2_cyc_int <= wrdata_reg(27 downto 0);
end if;
......@@ -539,14 +644,14 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001001" =>
when "0001010" =>
if (wb_we_i = '1') then
dio_trig3_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig3_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001010" =>
when "0001011" =>
if (wb_we_i = '1') then
dio_trigh3_seconds_int <= wrdata_reg(7 downto 0);
end if;
......@@ -577,7 +682,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
when "0001100" =>
if (wb_we_i = '1') then
dio_cyc3_cyc_int <= wrdata_reg(27 downto 0);
end if;
......@@ -588,14 +693,14 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001100" =>
when "0001101" =>
if (wb_we_i = '1') then
dio_trig4_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig4_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001101" =>
when "0001110" =>
if (wb_we_i = '1') then
dio_trigh4_seconds_int <= wrdata_reg(7 downto 0);
end if;
......@@ -626,7 +731,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001110" =>
when "0001111" =>
if (wb_we_i = '1') then
dio_cyc4_cyc_int <= wrdata_reg(27 downto 0);
end if;
......@@ -637,23 +742,70 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001111" =>
when "0010000" =>
if (wb_we_i = '1') then
dio_trig5_seconds_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= dio_trig5_seconds_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010001" =>
if (wb_we_i = '1') then
dio_trigh5_seconds_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= dio_trigh5_seconds_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010010" =>
if (wb_we_i = '1') then
dio_cyc5_cyc_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_cyc5_cyc_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010011" =>
if (wb_we_i = '1') then
dio_iomode_ch0_load_o <= '1';
dio_iomode_ch1_load_o <= '1';
dio_iomode_ch2_load_o <= '1';
dio_iomode_ch3_load_o <= '1';
dio_iomode_ch4_load_o <= '1';
dio_iomode_ch5_load_o <= '1';
end if;
rddata_reg(3 downto 0) <= dio_iomode_ch0_i;
rddata_reg(7 downto 4) <= dio_iomode_ch1_i;
rddata_reg(11 downto 8) <= dio_iomode_ch2_i;
rddata_reg(15 downto 12) <= dio_iomode_ch3_i;
rddata_reg(19 downto 16) <= dio_iomode_ch4_i;
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(23 downto 20) <= dio_iomode_ch5_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -664,19 +816,21 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
when "0010100" =>
if (wb_we_i = '1') then
dio_latch_time_ch0_int <= wrdata_reg(0);
dio_latch_time_ch1_int <= wrdata_reg(1);
dio_latch_time_ch2_int <= wrdata_reg(2);
dio_latch_time_ch3_int <= wrdata_reg(3);
dio_latch_time_ch4_int <= wrdata_reg(4);
dio_latch_time_ch5_int <= wrdata_reg(5);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= '0';
rddata_reg(3) <= '0';
rddata_reg(4) <= '0';
rddata_reg(5) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -711,11 +865,10 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "010001" =>
when "0010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= dio_trig_rdy_i;
rddata_reg(5) <= 'X';
rddata_reg(5 downto 0) <= dio_trig_rdy_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
......@@ -744,7 +897,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
when "0010110" =>
if (wb_we_i = '1') then
dio_prog0_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
......@@ -755,7 +908,18 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010011" =>
when "0010111" =>
if (wb_we_i = '1') then
dio_prog0_pulse_per_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog0_pulse_per_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011000" =>
if (wb_we_i = '1') then
dio_prog1_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
......@@ -766,7 +930,18 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010100" =>
when "0011001" =>
if (wb_we_i = '1') then
dio_prog1_pulse_per_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog1_pulse_per_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011010" =>
if (wb_we_i = '1') then
dio_prog2_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
......@@ -777,7 +952,18 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010101" =>
when "0011011" =>
if (wb_we_i = '1') then
dio_prog2_pulse_per_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog2_pulse_per_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011100" =>
if (wb_we_i = '1') then
dio_prog3_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
......@@ -788,7 +974,18 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010110" =>
when "0011101" =>
if (wb_we_i = '1') then
dio_prog3_pulse_per_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog3_pulse_per_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011110" =>
if (wb_we_i = '1') then
dio_prog4_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
......@@ -799,7 +996,40 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010111" =>
when "0011111" =>
if (wb_we_i = '1') then
dio_prog4_pulse_per_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog4_pulse_per_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100000" =>
if (wb_we_i = '1') then
dio_prog5_pulse_length_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog5_pulse_length_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100001" =>
if (wb_we_i = '1') then
dio_prog5_pulse_per_int <= wrdata_reg(27 downto 0);
end if;
rddata_reg(27 downto 0) <= dio_prog5_pulse_per_int;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100010" =>
if (wb_we_i = '1') then
dio_pulse_imm_0_int <= wrdata_reg(0);
dio_pulse_imm_0_int_delay <= wrdata_reg(0);
......@@ -811,12 +1041,15 @@ begin
dio_pulse_imm_3_int_delay <= wrdata_reg(3);
dio_pulse_imm_4_int <= wrdata_reg(4);
dio_pulse_imm_4_int_delay <= wrdata_reg(4);
dio_pulse_imm_5_int <= wrdata_reg(5);
dio_pulse_imm_5_int_delay <= wrdata_reg(5);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(2) <= '0';
rddata_reg(3) <= '0';
rddata_reg(4) <= '0';
rddata_reg(5) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -851,7 +1084,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "011000" =>
when "0101000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
end if;
......@@ -889,7 +1122,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011001" =>
when "0101001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
end if;
......@@ -927,12 +1160,10 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
when "0101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(9 downto 0) <= eic_imr_int(9 downto 0);
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(11 downto 0) <= eic_imr_int(11 downto 0);
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
......@@ -955,13 +1186,11 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011011" =>
when "0101011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
end if;
rddata_reg(9 downto 0) <= eic_isr_status_int(9 downto 0);
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(11 downto 0) <= eic_isr_status_int(11 downto 0);
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
......@@ -984,7 +1213,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
when "0101100" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf0_rdreq_int_d0 = '0') then
......@@ -994,7 +1223,7 @@ begin
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "011101" =>
when "0101101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf0_out_int(39 downto 32);
......@@ -1024,7 +1253,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011110" =>
when "0101110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf0_out_int(67 downto 40);
......@@ -1034,7 +1263,29 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011111" =>
when "0101111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= dio_tsf0_out_int(83 downto 68);
rddata_reg(16) <= dio_tsf0_out_int(84);
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf0_full_int;
......@@ -1064,7 +1315,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
when "0110001" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf1_rdreq_int_d0 = '0') then
......@@ -1074,7 +1325,7 @@ begin
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "100001" =>
when "0110010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf1_out_int(39 downto 32);
......@@ -1104,7 +1355,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100010" =>
when "0110011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf1_out_int(67 downto 40);
......@@ -1114,7 +1365,29 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100011" =>
when "0110100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= dio_tsf1_out_int(83 downto 68);
rddata_reg(16) <= dio_tsf1_out_int(84);
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf1_full_int;
......@@ -1144,7 +1417,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100100" =>
when "0110110" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf2_rdreq_int_d0 = '0') then
......@@ -1154,7 +1427,7 @@ begin
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "100101" =>
when "0110111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf2_out_int(39 downto 32);
......@@ -1184,7 +1457,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100110" =>
when "0111000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf2_out_int(67 downto 40);
......@@ -1194,7 +1467,29 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100111" =>
when "0111001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= dio_tsf2_out_int(83 downto 68);
rddata_reg(16) <= dio_tsf2_out_int(84);
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf2_full_int;
......@@ -1224,7 +1519,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101000" =>
when "0111011" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf3_rdreq_int_d0 = '0') then
......@@ -1234,7 +1529,7 @@ begin
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "101001" =>
when "0111100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf3_out_int(39 downto 32);
......@@ -1264,7 +1559,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101010" =>
when "0111101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf3_out_int(67 downto 40);
......@@ -1274,7 +1569,29 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101011" =>
when "0111110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= dio_tsf3_out_int(83 downto 68);
rddata_reg(16) <= dio_tsf3_out_int(84);
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf3_full_int;
......@@ -1304,7 +1621,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101100" =>
when "1000000" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf4_rdreq_int_d0 = '0') then
......@@ -1314,7 +1631,7 @@ begin
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "101101" =>
when "1000001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf4_out_int(39 downto 32);
......@@ -1344,7 +1661,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101110" =>
when "1000010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf4_out_int(67 downto 40);
......@@ -1354,7 +1671,29 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101111" =>
when "1000011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= dio_tsf4_out_int(83 downto 68);
rddata_reg(16) <= dio_tsf4_out_int(84);
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf4_full_int;
......@@ -1384,6 +1723,108 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000101" =>
if (wb_we_i = '1') then
end if;
if (dio_tsf5_rdreq_int_d0 = '0') then
dio_tsf5_rdreq_int <= not dio_tsf5_rdreq_int;
else
rddata_reg(31 downto 0) <= dio_tsf5_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "1000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= dio_tsf5_out_int(39 downto 32);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= dio_tsf5_out_int(67 downto 40);
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= dio_tsf5_out_int(83 downto 68);
rddata_reg(16) <= dio_tsf5_out_int(84);
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dio_tsf5_full_int;
rddata_reg(17) <= dio_tsf5_empty_int;
rddata_reg(7 downto 0) <= dio_tsf5_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -1397,15 +1838,19 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Version identifier
dio_ver_id_o <= dio_ver_id_int;
-- extra code for reg/fifo/mem: Timestamp FIFO 0
dio_tsf0_in_int(31 downto 0) <= dio_tsf0_tag_seconds_i;
dio_tsf0_in_int(39 downto 32) <= dio_tsf0_tag_secondsh_i;
dio_tsf0_in_int(67 downto 40) <= dio_tsf0_tag_cycles_i;
dio_tsf0_in_int(83 downto 68) <= dio_tsf0_leap_second_value_i;
dio_tsf0_in_int(84) <= dio_tsf0_leap_second_valid_i;
dio_tsf0_rst_n <= rst_n_i;
dio_tsf0_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_width => 85,
g_usedw_size => 8
)
port map (
......@@ -1426,11 +1871,13 @@ begin
dio_tsf1_in_int(31 downto 0) <= dio_tsf1_tag_seconds_i;
dio_tsf1_in_int(39 downto 32) <= dio_tsf1_tag_secondsh_i;
dio_tsf1_in_int(67 downto 40) <= dio_tsf1_tag_cycles_i;
dio_tsf1_in_int(83 downto 68) <= dio_tsf1_leap_second_value_i;
dio_tsf1_in_int(84) <= dio_tsf1_leap_second_valid_i;
dio_tsf1_rst_n <= rst_n_i;
dio_tsf1_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_width => 85,
g_usedw_size => 8
)
port map (
......@@ -1451,11 +1898,13 @@ begin
dio_tsf2_in_int(31 downto 0) <= dio_tsf2_tag_seconds_i;
dio_tsf2_in_int(39 downto 32) <= dio_tsf2_tag_secondsh_i;
dio_tsf2_in_int(67 downto 40) <= dio_tsf2_tag_cycles_i;
dio_tsf2_in_int(83 downto 68) <= dio_tsf2_leap_second_value_i;
dio_tsf2_in_int(84) <= dio_tsf2_leap_second_valid_i;
dio_tsf2_rst_n <= rst_n_i;
dio_tsf2_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_width => 85,
g_usedw_size => 8
)
port map (
......@@ -1476,11 +1925,13 @@ begin
dio_tsf3_in_int(31 downto 0) <= dio_tsf3_tag_seconds_i;
dio_tsf3_in_int(39 downto 32) <= dio_tsf3_tag_secondsh_i;
dio_tsf3_in_int(67 downto 40) <= dio_tsf3_tag_cycles_i;
dio_tsf3_in_int(83 downto 68) <= dio_tsf3_leap_second_value_i;
dio_tsf3_in_int(84) <= dio_tsf3_leap_second_valid_i;
dio_tsf3_rst_n <= rst_n_i;
dio_tsf3_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_width => 85,
g_usedw_size => 8
)
port map (
......@@ -1501,11 +1952,13 @@ begin
dio_tsf4_in_int(31 downto 0) <= dio_tsf4_tag_seconds_i;
dio_tsf4_in_int(39 downto 32) <= dio_tsf4_tag_secondsh_i;
dio_tsf4_in_int(67 downto 40) <= dio_tsf4_tag_cycles_i;
dio_tsf4_in_int(83 downto 68) <= dio_tsf4_leap_second_value_i;
dio_tsf4_in_int(84) <= dio_tsf4_leap_second_valid_i;
dio_tsf4_rst_n <= rst_n_i;
dio_tsf4_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 68,
g_width => 85,
g_usedw_size => 8
)
port map (
......@@ -1522,6 +1975,33 @@ begin
rd_data_o => dio_tsf4_out_int
);
-- extra code for reg/fifo/mem: Timestamp FIFO 5
dio_tsf5_in_int(31 downto 0) <= dio_tsf5_tag_seconds_i;
dio_tsf5_in_int(39 downto 32) <= dio_tsf5_tag_secondsh_i;
dio_tsf5_in_int(67 downto 40) <= dio_tsf5_tag_cycles_i;
dio_tsf5_in_int(83 downto 68) <= dio_tsf5_leap_second_value_i;
dio_tsf5_in_int(84) <= dio_tsf5_leap_second_valid_i;
dio_tsf5_rst_n <= rst_n_i;
dio_tsf5_INST : wbgen2_fifo_sync
generic map (
g_size => 256,
g_width => 85,
g_usedw_size => 8
)
port map (
wr_req_i => dio_tsf5_wr_req_i,
wr_full_o => dio_tsf5_wr_full_o,
wr_empty_o => dio_tsf5_wr_empty_o,
rd_full_o => dio_tsf5_full_int,
rd_empty_o => dio_tsf5_empty_int,
rd_usedw_o => dio_tsf5_usedw_int,
rd_req_i => dio_tsf5_rdreq_int,
rst_n_i => dio_tsf5_rst_n,
clk_i => clk_sys_i,
wr_data_i => dio_tsf5_in_int,
rd_data_o => dio_tsf5_out_int
);
-- seconds field
dio_trig0_seconds_o <= dio_trig0_seconds_int;
-- seconds field
......@@ -1552,6 +2032,12 @@ begin
dio_trigh4_seconds_o <= dio_trigh4_seconds_int;
-- cycles field
dio_cyc4_cyc_o <= dio_cyc4_cyc_int;
-- seconds field
dio_trig5_seconds_o <= dio_trig5_seconds_int;
-- seconds field
dio_trigh5_seconds_o <= dio_trigh5_seconds_int;
-- cycles field
dio_cyc5_cyc_o <= dio_cyc5_cyc_int;
-- channel0
dio_iomode_ch0_o <= wrdata_reg(3 downto 0);
-- channel1
......@@ -1562,6 +2048,8 @@ begin
dio_iomode_ch3_o <= wrdata_reg(15 downto 12);
-- channel4
dio_iomode_ch4_o <= wrdata_reg(19 downto 16);
-- channel5
dio_iomode_ch5_o <= wrdata_reg(23 downto 20);
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
......@@ -1627,17 +2115,44 @@ begin
end process;
-- Sincle-cycle strobe
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_latch_time_ch5_dly0 <= '0';
dio_latch_time_ch5_o <= '0';
elsif rising_edge(clk_sys_i) then
dio_latch_time_ch5_dly0 <= dio_latch_time_ch5_int;
dio_latch_time_ch5_o <= dio_latch_time_ch5_int and (not dio_latch_time_ch5_dly0);
end if;
end process;
-- trig_rdy field
-- number of ticks field for channel 0
dio_prog0_pulse_length_o <= dio_prog0_pulse_length_int;
-- number of ticks (period) field for channel 0
dio_prog0_pulse_per_o <= dio_prog0_pulse_per_int;
-- number of ticks field for channel 1
dio_prog1_pulse_length_o <= dio_prog1_pulse_length_int;
-- number of ticks (period) field for channel 1
dio_prog1_pulse_per_o <= dio_prog1_pulse_per_int;
-- number of ticks field for channel 2
dio_prog2_pulse_length_o <= dio_prog2_pulse_length_int;
-- number of ticks (period) field for channel 2
dio_prog2_pulse_per_o <= dio_prog2_pulse_per_int;
-- number of ticks field for channel 3
dio_prog3_pulse_length_o <= dio_prog3_pulse_length_int;
-- number of ticks (period) field for channel 3
dio_prog3_pulse_per_o <= dio_prog3_pulse_per_int;
-- number of ticks field for channel 4
dio_prog4_pulse_length_o <= dio_prog4_pulse_length_int;
-- number of ticks (period) field for channel 4
dio_prog4_pulse_per_o <= dio_prog4_pulse_per_int;
-- number of ticks field for channel 5
dio_prog5_pulse_length_o <= dio_prog5_pulse_length_int;
-- number of ticks (period) field for channel 5
dio_prog5_pulse_per_o <= dio_prog5_pulse_per_int;
-- pulse_gen_now_0
process (clk_asyn_i, rst_n_i)
begin
......@@ -1723,16 +2238,33 @@ begin
end process;
-- pulse_gen_now_5
process (clk_asyn_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_pulse_imm_5_o <= '0';
dio_pulse_imm_5_sync0 <= '0';
dio_pulse_imm_5_sync1 <= '0';
dio_pulse_imm_5_sync2 <= '0';
elsif rising_edge(clk_asyn_i) then
dio_pulse_imm_5_sync0 <= dio_pulse_imm_5_int;
dio_pulse_imm_5_sync1 <= dio_pulse_imm_5_sync0;
dio_pulse_imm_5_sync2 <= dio_pulse_imm_5_sync1;
dio_pulse_imm_5_o <= dio_pulse_imm_5_sync2 and (not dio_pulse_imm_5_sync1);
end if;
end process;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(9 downto 0) <= wrdata_reg(9 downto 0);
eic_idr_int(11 downto 0) <= wrdata_reg(11 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
eic_ier_int(9 downto 0) <= wrdata_reg(9 downto 0);
eic_ier_int(11 downto 0) <= wrdata_reg(11 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
eic_isr_clear_int(9 downto 0) <= wrdata_reg(9 downto 0);
eic_isr_clear_int(11 downto 0) <= wrdata_reg(11 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => 10,
g_num_interrupts => 12,
g_irq00_mode => 3,
g_irq01_mode => 3,
g_irq02_mode => 3,
......@@ -1743,8 +2275,8 @@ begin
g_irq07_mode => 3,
g_irq08_mode => 3,
g_irq09_mode => 3,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0a_mode => 3,
g_irq0b_mode => 3,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
......@@ -1787,11 +2319,13 @@ begin
irq_inputs_vector_int(2) <= irq_nempty_2_i;
irq_inputs_vector_int(3) <= irq_nempty_3_i;
irq_inputs_vector_int(4) <= irq_nempty_4_i;
irq_inputs_vector_int(5) <= irq_trigger_ready_0_i;
irq_inputs_vector_int(6) <= irq_trigger_ready_1_i;
irq_inputs_vector_int(7) <= irq_trigger_ready_2_i;
irq_inputs_vector_int(8) <= irq_trigger_ready_3_i;
irq_inputs_vector_int(9) <= irq_trigger_ready_4_i;
irq_inputs_vector_int(5) <= irq_nempty_5_i;
irq_inputs_vector_int(6) <= irq_trigger_ready_0_i;
irq_inputs_vector_int(7) <= irq_trigger_ready_1_i;
irq_inputs_vector_int(8) <= irq_trigger_ready_2_i;
irq_inputs_vector_int(9) <= irq_trigger_ready_3_i;
irq_inputs_vector_int(10) <= irq_trigger_ready_4_i;
irq_inputs_vector_int(11) <= irq_trigger_ready_5_i;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 0
process (clk_sys_i, rst_n_i)
begin
......@@ -1805,6 +2339,7 @@ begin
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 0' data output register 3
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 0
process (clk_sys_i, rst_n_i)
begin
......@@ -1818,6 +2353,7 @@ begin
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 1' data output register 3
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 0
process (clk_sys_i, rst_n_i)
begin
......@@ -1831,6 +2367,7 @@ begin
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 2' data output register 3
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 0
process (clk_sys_i, rst_n_i)
begin
......@@ -1844,6 +2381,7 @@ begin
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 3' data output register 3
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 0
process (clk_sys_i, rst_n_i)
begin
......@@ -1857,8 +2395,25 @@ begin
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 4' data output register 3
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 5' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dio_tsf5_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
dio_tsf5_rdreq_int_d0 <= dio_tsf5_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 5' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 5' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO 5' data output register 3
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/modules/wr_dio/xwr_dio.vhd
View file @ 37e705b5
......@@ -48,7 +48,7 @@
-- 0x100: DIO-I2C
-- 0x200: DIO-GPIO
-- 0x300: DIO-TIMING REGISTERS
-- 0x400: SDB-BRIDGE --> MAGIC NUMBER
-- 0x800: SDB-BRIDGE --> MAGIC NUMBER
library ieee;
use ieee.std_logic_1164.all;
......@@ -70,10 +70,10 @@ entity xwr_dio is
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_in_i : in std_logic_vector(5 downto 0);
dio_out_o : out std_logic_vector(5 downto 0);
dio_oe_n_o : out std_logic_vector(5 downto 0);
dio_term_en_o : out std_logic_vector(5 downto 0);
dio_onewire_b : inout std_logic;
dio_sdn_n_o : out std_logic;
dio_sdn_ck_n_o : out std_logic;
......@@ -104,6 +104,7 @@ end xwr_dio;
architecture rtl of xwr_dio is
-------------------------------------------------------------------------------
-- Component only for debugging (in order to generate seconds time)
-------------------------------------------------------------------------------
......@@ -151,7 +152,6 @@ architecture rtl of xwr_dio is
trig_utc_i : in std_logic_vector(39 downto 0);
trig_cycles_i : in std_logic_vector(27 downto 0);
trig_valid_p1_i : in std_logic;
pulse_length_i : in std_logic_vector(27 downto 0)
);
end component;
......@@ -212,7 +212,7 @@ architecture rtl of xwr_dio is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -223,143 +223,196 @@ architecture rtl of xwr_dio is
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
clk_asyn_i : in std_logic;
-- FIFO write request
-- Port for std_logic_vector field: 'Version identifier' in reg: 'Version register'
dio_ver_id_o : out std_logic_vector(31 downto 0);
-- FIFO write request
dio_tsf0_wr_req_i : in std_logic;
-- FIFO full flag
-- FIFO full flag
dio_tsf0_wr_full_o : out std_logic;
-- FIFO empty flag
-- FIFO empty flag
dio_tsf0_wr_empty_o : out std_logic;
dio_tsf0_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf0_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf0_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf0_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf0_leap_second_valid_i : in std_logic;
irq_nempty_0_i : in std_logic;
-- FIFO write request
-- FIFO write request
dio_tsf1_wr_req_i : in std_logic;
-- FIFO full flag
-- FIFO full flag
dio_tsf1_wr_full_o : out std_logic;
-- FIFO empty flag
-- FIFO empty flag
dio_tsf1_wr_empty_o : out std_logic;
dio_tsf1_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf1_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf1_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf1_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf1_leap_second_valid_i : in std_logic;
irq_nempty_1_i : in std_logic;
-- FIFO write request
-- FIFO write request
dio_tsf2_wr_req_i : in std_logic;
-- FIFO full flag
-- FIFO full flag
dio_tsf2_wr_full_o : out std_logic;
-- FIFO empty flag
-- FIFO empty flag
dio_tsf2_wr_empty_o : out std_logic;
dio_tsf2_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf2_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf2_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf2_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf2_leap_second_valid_i : in std_logic;
irq_nempty_2_i : in std_logic;
-- FIFO write request
-- FIFO write request
dio_tsf3_wr_req_i : in std_logic;
-- FIFO full flag
-- FIFO full flag
dio_tsf3_wr_full_o : out std_logic;
-- FIFO empty flag
-- FIFO empty flag
dio_tsf3_wr_empty_o : out std_logic;
dio_tsf3_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf3_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf3_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf3_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf3_leap_second_valid_i : in std_logic;
irq_nempty_3_i : in std_logic;
-- FIFO write request
-- FIFO write request
dio_tsf4_wr_req_i : in std_logic;
-- FIFO full flag
-- FIFO full flag
dio_tsf4_wr_full_o : out std_logic;
-- FIFO empty flag
-- FIFO empty flag
dio_tsf4_wr_empty_o : out std_logic;
dio_tsf4_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf4_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf4_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf4_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf4_leap_second_valid_i : in std_logic;
irq_nempty_4_i : in std_logic;
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
-- FIFO write request
dio_tsf5_wr_req_i : in std_logic;
-- FIFO full flag
dio_tsf5_wr_full_o : out std_logic;
-- FIFO empty flag
dio_tsf5_wr_empty_o : out std_logic;
dio_tsf5_tag_seconds_i : in std_logic_vector(31 downto 0);
dio_tsf5_tag_secondsh_i : in std_logic_vector(7 downto 0);
dio_tsf5_tag_cycles_i : in std_logic_vector(27 downto 0);
dio_tsf5_leap_second_value_i : in std_logic_vector(15 downto 0);
dio_tsf5_leap_second_valid_i : in std_logic;
irq_nempty_5_i : in std_logic;
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trig0_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 0 seconds-based trigger for pulse generation'
dio_trigh0_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 0 cycles to trigger a pulse generation'
dio_cyc0_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trig1_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 1 seconds-based trigger for pulse generation'
dio_trigh1_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 1 cycles to trigger a pulse generation'
dio_cyc1_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trig2_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 2 seconds-based trigger for pulse generation'
dio_trigh2_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 2 cycles to trigger a pulse generation'
dio_cyc2_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trig3_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 3 seconds-based trigger for pulse generation'
dio_trigh3_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 3 cycles to trigger a pulse generation'
dio_cyc3_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trig4_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 4 seconds-based trigger for pulse generation'
dio_trigh4_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 4 cycles to trigger a pulse generation'
dio_cyc4_cyc_o : out std_logic_vector(27 downto 0);
-- Port for unsigned field: 'channel' in reg: 'FMC-DIO input/output configuration register. '
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 5 seconds-based trigger for pulse generation'
dio_trig5_seconds_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'seconds field' in reg: 'fmc-dio 5 seconds-based trigger for pulse generation'
dio_trigh5_seconds_o : out std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'cycles field' in reg: 'fmc-dio 5 cycles to trigger a pulse generation'
dio_cyc5_cyc_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'channel0' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch0_o : out std_logic_vector(3 downto 0);
dio_iomode_ch0_i : in std_logic_vector(3 downto 0);
dio_iomode_ch0_load_o : out std_logic;
-- Port for unsigned field: 'channel1' in reg: 'FMC-DIO input/output configuration register. '
-- Port for std_logic_vector field: 'channel1' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch1_o : out std_logic_vector(3 downto 0);
dio_iomode_ch1_i : in std_logic_vector(3 downto 0);
dio_iomode_ch1_load_o : out std_logic;
-- Port for unsigned field: 'channel2' in reg: 'FMC-DIO input/output configuration register. '
-- Port for std_logic_vector field: 'channel2' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch2_o : out std_logic_vector(3 downto 0);
dio_iomode_ch2_i : in std_logic_vector(3 downto 0);
dio_iomode_ch2_load_o : out std_logic;
-- Port for unsigned field: 'channel3' in reg: 'FMC-DIO input/output configuration register. '
-- Port for std_logic_vector field: 'channel3' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch3_o : out std_logic_vector(3 downto 0);
dio_iomode_ch3_i : in std_logic_vector(3 downto 0);
dio_iomode_ch3_load_o : out std_logic;
-- Port for unsigned field: 'channel4' in reg: 'FMC-DIO input/output configuration register. '
-- Port for std_logic_vector field: 'channel4' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch4_o : out std_logic_vector(3 downto 0);
dio_iomode_ch4_i : in std_logic_vector(3 downto 0);
dio_iomode_ch4_load_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
-- Port for std_logic_vector field: 'channel5' in reg: 'FMC-DIO input/output configuration register. '
dio_iomode_ch5_o : out std_logic_vector(3 downto 0);
dio_iomode_ch5_i : in std_logic_vector(3 downto 0);
dio_iomode_ch5_load_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch0_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch1_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch2_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch3_o : out std_logic;
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch4_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO time trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(4 downto 0);
-- Port for MONOSTABLE field: 'Sincle-cycle strobe' in reg: 'Time-programmable output strobe signal'
dio_latch_time_ch5_o : out std_logic;
-- Port for std_logic_vector field: 'trig_rdy field' in reg: 'FMC-DIO time trigger is ready to accept a new trigger generation request'
dio_trig_rdy_i : in std_logic_vector(5 downto 0);
irq_trigger_ready_0_i : in std_logic;
irq_trigger_ready_1_i : in std_logic;
irq_trigger_ready_2_i : in std_logic;
irq_trigger_ready_3_i : in std_logic;
irq_trigger_ready_4_i : in std_logic;
-- Port for std_logic_vector field: 'number of ticks field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse length'
irq_trigger_ready_5_i : in std_logic;
-- Port for std_logic_vector field: 'number of ticks field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse length'
dio_prog0_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse length'
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 0' in reg: 'fmc-dio channel 0 Programmable/immediate output pulse period'
dio_prog0_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse length'
dio_prog1_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse length'
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 1' in reg: 'fmc-dio channel 1 Programmable/immediate output pulse period'
dio_prog1_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse length'
dio_prog2_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse length'
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 2' in reg: 'fmc-dio channel 2 Programmable/immediate output pulse period'
dio_prog2_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse length'
dio_prog3_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse length'
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 3' in reg: 'fmc-dio channel 3 Programmable/immediate output pulse period'
dio_prog3_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse length'
dio_prog4_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 4' in reg: 'fmc-dio channel 4 Programmable/immediate output pulse period'
dio_prog4_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks field for channel 5' in reg: 'fmc-dio channel 5 Programmable/immediate output pulse length'
dio_prog5_pulse_length_o : out std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'number of ticks (period) field for channel 5' in reg: 'fmc-dio channel 5 Programmable/immediate output pulse period'
dio_prog5_pulse_per_o : out std_logic_vector(27 downto 0);
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_0' in reg: 'Pulse generate immediately'
dio_pulse_imm_0_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_1' in reg: 'Pulse generate immediately'
dio_pulse_imm_1_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_2' in reg: 'Pulse generate immediately'
dio_pulse_imm_2_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_3' in reg: 'Pulse generate immediately'
dio_pulse_imm_3_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_pulse_imm_4_o : out std_logic
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_4' in reg: 'Pulse generate immediately'
dio_pulse_imm_4_o : out std_logic;
-- Port for asynchronous (clock: clk_asyn_i) MONOSTABLE field: 'pulse_gen_now_5' in reg: 'Pulse generate immediately'
dio_pulse_imm_5_o : out std_logic
);
end component;
......@@ -390,7 +443,6 @@ architecture rtl of xwr_dio is
signal trig_seconds : t_seconds_array;
signal trig_cycles : t_cycles_array;
signal trig_valid_p1 : std_logic_vector (4 downto 0);
signal trig_ready : std_logic_vector (4 downto 0);
......@@ -418,9 +470,9 @@ architecture rtl of xwr_dio is
(0 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00000000"), -- ONEWIRE
1 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00000100"), -- I2C
2 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"00000200"), -- GPIO
3 => f_sdb_embed_device(c_xwr_dio_wb_sdb, x"00000300") -- DIO REGISTERS
3 => f_sdb_embed_device(c_xwr_dio_wb_sdb, x"00000400") -- DIO REGISTERS
);
constant c_diobar_sdb_address : t_wishbone_address := x"00000400";
constant c_diobar_sdb_address : t_wishbone_address := x"00000800";
signal cbar_master_in : t_wishbone_master_in_array(c_WB_SLAVES_DIO-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_WB_SLAVES_DIO-1 downto 0);
......
hdl/top/dio-common/dio_common_top.vhd
View file @ 37e705b5
......@@ -240,10 +240,10 @@ architecture top of dio_common_top is
dio_clk_i : in std_logic;
dio_pps_i : in std_logic;
dio_in_i : in std_logic_vector(4 downto 0);
dio_out_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_in_i : in std_logic_vector(5 downto 0);
dio_out_o : out std_logic_vector(5 downto 0);
dio_oe_n_o : out std_logic_vector(5 downto 0);
dio_term_en_o : out std_logic_vector(5 downto 0);
dio_onewire_b : inout std_logic;
dio_sdn_n_o : out std_logic;
dio_sdn_ck_n_o : out std_logic;
......@@ -325,8 +325,8 @@ architecture top of dio_common_top is
signal svec_led : std_logic_vector(15 downto 0);
-- DIO Mezzanine
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal dio_in : std_logic_vector(5 downto 0);
signal dio_out : std_logic_vector(5 downto 0);
-- Timecode output
signal tm_time_valid : std_logic;
......@@ -350,6 +350,9 @@ architecture top of dio_common_top is
-- VIC-only signals
signal vic_only_irqs : std_logic_vector(3 downto 0);
signal dio_oe_n_o_internal : std_logic_vector(5 downto 0);
signal dio_term_en_o_internal : std_logic_vector(5 downto 0);
begin -- architecture top
-----------------------------------------------------------------------------
......@@ -663,8 +666,8 @@ begin -- architecture top
dio_pps_i => wrc_pps_out,
dio_in_i => dio_in,
dio_out_o => dio_out,
dio_oe_n_o => dio_oe_n_o,
dio_term_en_o => dio_term_en_o,
dio_oe_n_o => dio_oe_n_o_internal,
dio_term_en_o => dio_term_en_o_internal,
dio_onewire_b => dio_onewire_b,
dio_sdn_n_o => dio_sdn_n_o,
dio_sdn_ck_n_o => dio_sdn_ck_n_o,
......@@ -679,6 +682,9 @@ begin -- architecture top
dio_int => dio_int
);
dio_oe_n_o <= dio_oe_n_o_internal(4 downto 0);
dio_term_en_o <= dio_term_en_o_internal(4 downto 0);
vic_vec_int(0) <= dio_int;
NIC_GEN : if g_dio_mode = DIO_NIC generate
......
hdl/top/dio-common/dio_common_top_pkg.vhd
View file @ 37e705b5
......@@ -238,7 +238,7 @@ package dio_common_top_pkg is
constant c_nic_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0001ffff", x"00011000");
constant c_wr_dio_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_product_manual_sdb(x"00000fff", x"00000400", c_xwr_dio_sdb);
f_xwb_bridge_product_manual_sdb(x"00000fff", x"00000800", c_xwr_dio_sdb);
-- Primary wishbone crossbar layout (NIC)
constant c_NIC_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
......
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