- 29 Nov, 2023 1 commit
-
-
Mathieu Saccani authored
-
- 28 Nov, 2023 1 commit
-
-
Mathieu Saccani authored
Rename a block in regulator module, change the SPI polarity in the ADC LTC model, add a write DAC=0 if the HV_disable command is received
-
- 24 Nov, 2023 1 commit
-
-
Mathieu Saccani authored
-
- 22 Nov, 2023 1 commit
-
-
Mathieu Saccani authored
-
- 02 Nov, 2023 1 commit
-
-
Mathieu Saccani authored
-
- 16 Oct, 2023 2 commits
-
-
-
Mathieu Saccani authored
-
- 23 Aug, 2022 2 commits
-
-
Mathieu Saccani authored
-
Mathieu Saccani authored
-
- 06 Jul, 2022 1 commit
-
-
Mathieu Saccani authored
-
- 05 Jul, 2022 1 commit
-
-
Mathieu Saccani authored
-
- 04 Jul, 2022 1 commit
-
-
Mathieu Saccani authored
Add a top level above the interface block to include a regulator block, and minor update on the WB memory map
-
- 22 Jun, 2022 2 commits
-
-
Mathieu Saccani authored
-
Juan David González Cobas authored
-