FMC WorldFIP
FMC WorldFIP is an interface card for the
WorldFIP network
in an LPC FMC form-factor.
It is used as the physical layer interface of the
MasterFIP
project.
Top view of the masterFIP board*
Specifications
Parameter | Value |
Form-factor | FMC, LPC connector |
WorldFIP connector | Micro Sub-D 9 pins |
WorldFIP interface | FielDrive + FieldTR (Alstom) |
Bus speed | 31.25k, 1M, 2.5M, 5M (different versions of hardware) |
External sync. input | LEMO 0 connector |
Diagnostics | Embedded ADC |
Project information
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-03098
- Currently supported versions:
- FmcWorldFIP V1 - Bus speed 31.25k - EDA-03098-V1-0
- FmcWorldFIP V1 - Bus speed 1M - EDA-03098-V1-1
- FmcWorldFIP V1 - Bus speed 2.5M - EDA-03098-V1-2
- FmcWorldFIP V1 - Bus speed 5M - EDA-03098-V1-3
Project Status
Date | Event |
01-10-2014 | Schematics work started |
01-12-2014 | Schematics ready for layout |
27-01-2015 | Board layout done at CERN by DEM |
30-01-2015 | Layout review |
17-02-2015 | Layout modification ready |
20-02-2015 | First brainstorm about gateware and firmware |
19-03-2015 | Production files finalised, 3 prototypes ordered |
13-04-2015 | Designer Matthieu Cattin † |
29-04-2015 | 3 assembled prototypes received, 5 empty PCBs available |
23-07-2015 | One board tested that sent and received WorldFIP data. ADC not tested. |
Support
- Frequently Asked Questions
- Mailing list fmc-worldfip@ohwr.org and its archive.
Contacts
- Eva Gousiou - CERN
- Erik van der Bij - CERN
- Matthieu Cattin †, designer - CERN
Matthieu Cattin, Erik van der Bij, 12 October 2015