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AIDA-2020 TLU - Gateware
Commit 187ad97c authored by David Cussans's avatar David Cussans
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Was seeing behaviour from firmware that didn't match the simulation output 

( trigger output two clock cycles of 40MHz, trigger number on reset line being clocked out at 160MHz)

* Added reset circuitry to DUTInterface_AIDA_rtl.vhd

* Added one extra register of clk4x ( 160MHz ) to aid with timing closure ( although Vivado not reporting negative slack - so have probably got timing contraints wrong :-o )
parent d2a1565d
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AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_AIDA_rtl.vhd
View file @ 187ad97c
......@@ -35,10 +35,11 @@ ENTITY DUTInterface_AIDA IS
g_NUM_TRIGNUM_GUARDBITS : positive := 4
);
PORT(
clk_4x_logic_i : IN std_logic;
clk_4x_logic_i : IN std_logic; --! By default 160MHz. Rising edge active
logic_reset_i : IN std_logic ; --! High for one
strobe_4x_logic_i : IN std_logic; --! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
clockout_trigger_flag_i : in std_logic; --! Set high to clock out trigger counter on rst/dut-clock line
not_clockout_trigger_i : in std_logic; --! Set high to clock out trigger counter on rst/dut-clock line
trigger_i : IN std_logic; --! goes high when trigger logic issues a trigger
reset_or_clk_to_dut_i : IN std_logic; --! Synchronization signal. Passed to DUT pins
shutter_to_dut_i : IN std_logic; --! Goes high to indicate data-taking active. Gets passed to DUT pins
......@@ -60,7 +61,8 @@ END ENTITY DUTInterface_AIDA ;
--
ARCHITECTURE rtl OF DUTInterface_AIDA IS
signal s_strobe_4x_logic_d1 : std_logic;
-- signal s_strobe_4x_logic_d1 : std_logic;
signal s_busy, s_dut_clk_d1, s_trigger_out_d1, s_dut_reset_or_clk : std_logic := '0';
signal s_dut_clk : std_logic := '0'; --! Clock to be sent to DUT connectors ( before final register )
signal s_dut_clk_sr : std_logic_vector(2 downto 0) := "001"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
signal s_stretch_trig_in : std_logic := '0'; --! stretched version of trigger_i
......@@ -68,7 +70,7 @@ ARCHITECTURE rtl OF DUTInterface_AIDA IS
signal s_trigger_out : std_logic := '0'; -- ! trigger shifted to start on strobe_4x_logic
-- Set length of output trigger here ( output length = length of this vector + 1 )
signal s_trigger_out_sr : std_logic_vector(2 downto 0) := ( others => '1'); --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic.
signal s_trigger_out_sr : std_logic_vector(2 downto 0) := ( others => '0'); --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic.
signal s_trigger_number_sr : std_logic_vector(g_NUM_TRIGNUM_BITS_TO_CLOCKOUT-1 downto 0) := (others => '0'); --! Shift register loaded with trigger(event) number
signal s_trigger_number_guard_sr : std_logic_vector( (g_NUM_TRIGNUM_BITS_TO_CLOCKOUT+g_NUM_TRIGNUM_GUARDBITS) -1 downto 0) := (others => '0'); --! Loaded with "ones" to indicate busy shifting trigger number
......@@ -85,7 +87,7 @@ BEGIN
if ( rising_edge(clk_4x_logic_i) and strobe_4x_logic_i = '1' ) then
if ( s_trigger_out = '1' and s_trigger_number_guard_sr(0) = '0' and clockout_trigger_flag_i = '1' ) then --! If we have a trigger, we are not busy with previous trigger and we want to shift out trigger number, then load shift register with trigger number
if ( s_trigger_out = '1' and s_trigger_number_guard_sr(0) = '0' and not_clockout_trigger_i = '0' ) then --! If we have a trigger, we are not busy with previous trigger and we want to shift out trigger number, then load shift register with trigger number
s_trigger_number_sr <= trigger_counter_i(s_trigger_number_sr'range);
s_trigger_number_guard_sr <= ( others =>'1');
else
......@@ -119,6 +121,7 @@ BEGIN
end if;
end if;
end process p_dut_clk_gen;
else generate
s_dut_clk <= '0'; -- Set clock to zero and rely on external clock generator chip
......@@ -130,12 +133,15 @@ BEGIN
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , trigger_i
-- outputs: s_premask_trigger_to_dut
p_dut_trig_retime: process (clk_4x_logic_i , strobe_4x_logic_i , trigger_i) is
p_dut_trig_retime: process (clk_4x_logic_i , strobe_4x_logic_i , trigger_i , logic_reset_i ) is
begin -- process p_dut_trig_retime
if rising_edge(clk_4x_logic_i) then
-- Stretch trigger_i pulse to 4 clock cycles on clk4x
if trigger_i = '1' then
if logic_reset_i = '1' then
s_stretch_trig_in <= '0';
s_stretch_trig_in_sr <= ( others => '0' );
elsif trigger_i = '1' then
s_stretch_trig_in <= '1';
s_stretch_trig_in_sr <= ( others => '1' );
else
......@@ -144,7 +150,10 @@ BEGIN
end if;
--! Synchronize stretched trigger with strobe_4x_logic_i
if (strobe_4x_logic_i = '1') and ( s_stretch_trig_in = '1' ) then
if logic_reset_i = '1' then
s_trigger_out <= '0';
s_trigger_out_sr <= ( others => '0' );
elsif (strobe_4x_logic_i = '1') and ( s_stretch_trig_in = '1' ) then
s_trigger_out <= '1';
s_trigger_out_sr <= ( others => '1' );
else
......@@ -160,25 +169,32 @@ BEGIN
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
-- outputs: busy_o
register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
register_signals: process (clk_4x_logic_i, not_clockout_trigger_i ) is -- , strobe_4x_logic_i , s_veto)
begin -- process register_signals
if rising_edge(clk_4x_logic_i) then
s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
-- s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
busy_o <= dut_busy_i or s_busy_clocking_trigger_number;
s_busy <= dut_busy_i or s_busy_clocking_trigger_number;
dut_clk_o <= s_dut_clk ;
s_dut_clk_d1 <= s_dut_clk ;
dut_trigger_o <= s_trigger_out;
s_trigger_out_d1 <= s_trigger_out;
if clockout_trigger_flag_i = '1' then -- if flag set then clock out trigger number
dut_reset_or_clk_o <= s_trigger_number_sr(0); -- Clock out trigger number LSB first.
if not_clockout_trigger_i = '0' then -- if flag set then clock out trigger number
s_dut_reset_or_clk <= s_trigger_number_sr(0); -- Clock out trigger number LSB first.
else
-- Copy reset/clk signal straight through
dut_reset_or_clk_o <= reset_or_clk_to_dut_i;
s_dut_reset_or_clk <= reset_or_clk_to_dut_i;
end if;
-- Add registers to help timing closture
busy_o <= s_busy;
dut_clk_o <= s_dut_clk_d1;
dut_trigger_o <= s_trigger_out_d1;
dut_reset_or_clk_o <= s_dut_reset_or_clk;
end if;
end process register_signals;
......
AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl.vhd
View file @ 187ad97c
......@@ -57,6 +57,7 @@ ENTITY DUTInterfaces IS
);
PORT(
clk_4x_logic_i : IN std_logic;
logic_reset_i : IN std_logic ; --! Goes high for one cycle of clk_4x_logic to reset shift reg.
strobe_4x_logic_i : IN std_logic; --! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
trigger_i : IN std_logic; --! goes high when trigger logic issues a trigger
......@@ -107,7 +108,7 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal s_DUT_aida_eudet_mode : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! set bit to 1 for AIDA mode, 0 for EUDET
signal s_dut_enable_veto_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! set bit high to allow asynchronous veto using DUT_CLK when in EUDET mode
signal s_aida_clockout_trigger_flag : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Set high to clock out trigger number in AIDA mode.
signal s_aida_not_clockout_trigger : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Set high to clock out trigger number in AIDA mode.
signal s_DUT_interface_mode_modifier : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1');
signal s_IgnoreShutterVeto : std_logic := '0'; -- --! When high the shutter won't veto triggers when low.
......@@ -204,9 +205,10 @@ BEGIN
)
PORT map (
clk_4x_logic_i => clk_4x_logic_i ,
logic_reset_i => logic_reset_i,
strobe_4x_logic_i => strobe_4x_logic_i ,
trigger_counter_i => trigger_counter_i ,
clockout_trigger_flag_i => s_aida_clockout_trigger_flag(dut),
not_clockout_trigger_i => s_aida_not_clockout_trigger(dut),
trigger_i => trigger_i ,
reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
shutter_to_dut_i => shutter_to_dut_i ,
......@@ -244,7 +246,7 @@ BEGIN
);
s_DUT_aida_eudet_mode(dut) <= s_DUT_interface_mode(2*dut);
s_aida_clockout_trigger_flag(dut) <= s_DUT_interface_mode( (2*dut) + 1 );
s_aida_not_clockout_trigger(dut) <= s_DUT_interface_mode( (2*dut) + 1 );
s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut);
......
AIDA_tlu/components/tlu/firmware/hdl/logic_clocks_rtl.vhd
View file @ 187ad97c
......@@ -51,9 +51,6 @@ use unisim.vcomponents.all;
--! \br (decode 2 bits)
--! \li 0x00000000 - control/status register:
--! \li bit-0 - PLL locked ( 1 = locked )
--! \li bit-1 - buff-PLL locked ( 1 = locked )
--! \li bit-2 - use xtal for logic ( 1 = xtal , 0= external)
--! \li bit-3 - clock connector is an input ( 1=input , 0 = output)
--! \li 0x00000001 - reset logic. Write to bit-zero to send reset.
--!
--!
......@@ -87,7 +84,7 @@ ARCHITECTURE rtl OF logic_clocks IS
signal ryanclock : std_logic;
signal s_clk320 , s_clk320_internal : std_logic;
signal s_clk40_out : std_logic; -- Clock generated by DDR register to feed out of chip.
signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '0'; -- default to
--Junk signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '0'; -- default to
-- input from ext
-- signal s_logic_clk_rst : std_logic := '0';
signal s_locked_pll, s_locked_bufpll : std_logic;
......@@ -132,8 +129,8 @@ BEGIN
s_logic_reset_ipb <= '0';
if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
case ipbus_i.ipb_addr(1 downto 0) is
when "00" =>
s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
--Junk when "00" =>
--Junk s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
when "01" =>
s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset
......@@ -146,7 +143,7 @@ BEGIN
s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
-- register the clock status signals onto IPBus domain.
--s_clock_status_ipb <= x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
s_clock_status_ipb <= x"0000000" & '0' & '0' & '0' & s_locked_pll; -- The only useful bit is not the PLL lock status.
s_clock_status_ipb <= x"0000000" & '0' & '0' & '0' & s_locked_pll; -- The only useful bit is now the PLL lock status.
end if;
end process ipbus_write;
......@@ -317,7 +314,7 @@ BEGIN
end if;
end if;
end process generate_8x_strobe;
strobe_8x_logic_O <= s_strobe160(15);
strobe_8x_logic_o <= s_strobe160(15);
--strobe_4x_logic_o <= s_strobe_generator(15); --
--s_clk40_out <= s_logic_clk_generator(15); --
......
AIDA_tlu/components/tlu/sim/hdl/DUTInterace_AIDA_tb.vhd
View file @ 187ad97c
......@@ -25,9 +25,10 @@ architecture bench of DUTInterface_AIDA_tb is
);
PORT(
clk_4x_logic_i : IN std_logic;
logic_reset_i : IN std_logic;
strobe_4x_logic_i : IN std_logic;
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
clockout_trigger_flag_i : in std_logic;
not_clockout_trigger_i : in std_logic;
trigger_i : IN std_logic;
reset_or_clk_to_dut_i : IN std_logic;
shutter_to_dut_i : IN std_logic;
......@@ -43,7 +44,7 @@ architecture bench of DUTInterface_AIDA_tb is
signal clk_4x_logic_i: std_logic;
signal strobe_4x_logic_i: std_logic;
signal trigger_counter_i: std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0) := (others =>'0');
signal clockout_trigger_flag_i: std_logic;
signal s_not_clockout_trigger: std_logic;
signal trigger_i: std_logic := '0';
signal reset_or_clk_to_dut_i: std_logic := '0';
signal shutter_to_dut_i: std_logic := '0';
......@@ -53,6 +54,7 @@ architecture bench of DUTInterface_AIDA_tb is
signal dut_reset_or_clk_o: std_logic;
signal dut_shutter_o: std_logic;
signal dut_trigger_o: std_logic ;
signal logic_reset : std_logic;
constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;
......@@ -68,9 +70,10 @@ begin
g_NUM_TRIGNUM_BITS_TO_CLOCKOUT => 16,
g_NUM_TRIGNUM_GUARDBITS => 4 )
port map ( clk_4x_logic_i => clk_4x_logic_i,
logic_reset_i => logic_reset,
strobe_4x_logic_i => strobe_4x_logic_i,
trigger_counter_i => trigger_counter_i,
clockout_trigger_flag_i => clockout_trigger_flag_i,
not_clockout_trigger_i => s_not_clockout_trigger,
trigger_i => trigger_i,
reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
shutter_to_dut_i => shutter_to_dut_i,
......@@ -91,8 +94,15 @@ begin
begin
-- Put initialisation code here
clockout_trigger_flag_i <= '1';
s_not_clockout_trigger <= '0';
logic_reset <= '0';
wait for clock_period *4 ;
wait until rising_edge(clk_4x_logic_i);
logic_reset <= '1';
wait until rising_edge(clk_4x_logic_i);
logic_reset <= '0';
-- reset_i <= '1';
-- wait for clock_period*4;
-- reset_i <= '0';
......
AIDA_tlu/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
View file @ 187ad97c
---------------------------------------------------------------------------------
--
-- Copyright 2017 - University of Bristol
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- - - -
--
-- Additional information about ipbus-firmare and the list of ipbus-firmware
-- contacts are available at
--
-- https://ohwr.org/project/fmc-mtlu
--
---------------------------------------------------------------------------------
-- Top-level design for TLU v1E
--
-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
......@@ -25,7 +51,7 @@ use work.ipbus.ALL;
entity top is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000018"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"1e000020"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......@@ -158,6 +184,7 @@ architecture rtl of top is
);
port (
clk_4x_logic_i : IN std_logic ;
logic_reset_i : IN std_logic ;
strobe_4x_logic_i : IN std_logic ; --! goes high every 4th clock cycle
trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
trigger_i : IN std_logic ; --! goes high when trigger logic issues a trigger
......@@ -637,6 +664,7 @@ begin
)
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
logic_reset_i => logic_reset,
strobe_4x_logic_i => strobe_4x_logic,
trigger_counter_i => trigger_count,
trigger_i => overall_trigger,
......
AIDA_tlu/scripts/build_tlu_firmware.sh
View file @ 187ad97c
......@@ -2,7 +2,7 @@
# Put which branch of Git to use here...
IPBUS_BRANCH="-b v1.3"
TLU_BRANCH=""
TLU_BRANCH="-b 1e000020"
mkdir work
cd work
......
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