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AIDA-2020 TLU - Gateware
Commit 978bf193 authored by Thomas Blake's avatar Thomas Blake
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Commit of developments for nexys video

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AIDA_tlu/boards/digilent/base_fw/sim/firmware/cfg/lib_mappings.tcl 0 → 100755
View file @ 978bf193
set xlib $::env(XILINX_SIMLIBS)
vmap secureip $xlib/secureip
vmap unisim $xlib/unisim
vmap unimacro $xlib/unimacro
vmap unifast $xlib/unifast
vmap unisims_ver $xlib/unisims_ver
vmap unimacro_ver $xlib/unimacro_ver
vmap unifast_ver $xlib/unifast_ver
vmap simprims_ver $xlib/simprims_ver
AIDA_tlu/boards/digilent/base_fw/synth/firmware/cfg/digilent_nexys_video_infra.dep 0 → 100755
View file @ 978bf193
#-------------------------------------------------------------------------------
#
# Copyright 2017 - Rutherford Appleton Laboratory and University of Bristol
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# - - -
#
# Additional information about ipbus-firmare and the list of ipbus-firmware
# contacts are available at
#
# https://ipbus.web.cern.ch/ipbus
#
#-------------------------------------------------------------------------------
src --vhdl2008 digilent_nexys_video_infra.vhd
src -c ipbus-firmware:components/ipbus_util clocks/clocks_7s_extphy_se.vhd ipbus_clock_div.vhd led_stretcher.vhd
src -c ipbus-firmware:components/ipbus_util masters/ipbus_ctrl.vhd
include -c ipbus-firmware:components/ipbus_transport_udp
# include -c ipbus-firmware:components/ipbus_core
include -c ipbus-firmware:components/ipbus_eth artix_rgmii.dep
# Include simulated Ethernet - even though the Generate statement will ensure it never gets used.
src -c ipbus-firmware:components/modelsim_fli/eth ../sim/eth_mac_sim.vhd
src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd
AIDA_tlu/boards/digilent/base_fw/synth/firmware/cfg/settings_v7.tcl 0 → 100755
View file @ 978bf193
set obj [get_projects top]
set_property "default_lib" "xil_defaultlib" $obj
set_property "simulator_language" "Mixed" $obj
set_property "source_mgmt_mode" "DisplayOnly" $obj
set_property "target_language" "VHDL" $obj
AIDA_tlu/boards/digilent/base_fw/synth/firmware/hdl/digilent_nexys_video_infra.vhd 0 → 100755
View file @ 978bf193
---------------------------------------------------------------------------------
--
-- Copyright 2017 - Rutherford Appleton Laboratory and University of Bristol
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- - - -
--
-- Additional information about ipbus-firmare and the list of ipbus-firmware
-- contacts are available at
--
-- https://ipbus.web.cern.ch/ipbus
--
---------------------------------------------------------------------------------
-- digilent_nexys_video_infra
--
-- All board-specific stuff goes here
--
-- Dave Newbold, June 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity digilent_nexys_video_infra is
generic (
g_BUILD_SIMULATED_MAC :integer := 0 -- set != 0 to build with
-- simulated Phy
);
port(
sysclk: in std_logic; -- 50MHz board crystal clock
clk_ipb_o: out std_logic; -- IPbus clock
rst_ipb_o: out std_logic;
clk125_o: out std_logic;
clk_200_o: out std_logic; -- needed to calibrate I/O delays
rst125_o: out std_logic;
clk_aux_o: out std_logic; -- 50MHz clock
rst_aux_o: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
rgmii_txd: out std_logic_vector(3 downto 0);
rgmii_tx_ctl: out std_logic;
rgmii_txc: out std_logic;
rgmii_rxd: in std_logic_vector(3 downto 0);
rgmii_rx_ctl: in std_logic;
rgmii_rxc: in std_logic;
mac_addr: in std_logic_vector(47 downto 0); -- MAC address
ip_addr: in std_logic_vector(31 downto 0); -- IP address
ipb_in: in ipb_rbus; -- ipbus
ipb_out: out ipb_wbus
);
end digilent_nexys_video_infra;
architecture rtl of digilent_nexys_video_infra is
signal clk125_fr, clk125, clk125_90, clk200, clk_ipb, clk_ipb_i, locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
signal led_p: std_logic_vector(0 downto 0);
begin
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_7s_extphy_se
port map(
sysclk => sysclk,
clko_125 => clk125,
clko_125_90 => clk125_90,
clko_200 => clk200,
clko_ipb => clk_ipb_i,
locked => locked,
nuke => nuke,
soft_rst => soft_rst,
rsto_125 => rst125,
rsto_ipb => rst_ipb,
rsto_ipb_ctrl => rst_ipb_ctrl,
onehz => onehz
);
clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
clk_ipb_o <= clk_ipb_i;
rst_ipb_o <= rst_ipb;
clk125_o <= clk125;
rst125_o <= rst125;
clk_200_o <= clk200;
stretch: entity work.led_stretcher
generic map(
WIDTH => 1
)
port map(
clk => clk125,
d(0) => pkt,
q => led_p
);
leds <= (led_p(0), locked and onehz);
-- Ethernet MAC core and PHY interface
gen_ethernetPhy: if (g_BUILD_SIMULATED_MAC = 0) generate
-- Physical Phy
eth: entity work.eth_7s_rgmii
port map(
clk125 => clk125,
clk125_90 => clk125_90,
clk200 => clk200,
rst => rst125,
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
else generate
-- Simulated Phy
eth: entity work.eth_mac_sim
generic map(
MULTI_PACKET => true
)
port map(
clk => clk125,
rst => rst125,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
end generate gen_ethernetPhy;
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
port map(
mac_clk => clk125,
rst_macclk => rst125,
ipb_clk => clk_ipb,
rst_ipb => rst_ipb_ctrl,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_out,
ipb_in => ipb_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
pkt => pkt
);
end rtl;
AIDA_tlu/projects/TLU_v1e/firmware/cfg/digilent_nexys_video.dep 0 → 100755
View file @ 978bf193
@device_family = "artix7"
@device_name = "xc7a200t"
@device_package = "sbg484"
@device_speed = "-1"
@boardname = "digilent_nexys_video"
setup settings_v7.tcl
# Top level file
src top_digilent_nexys_video_tlu_v1e.vhd
#
src --cd ../cgn digilent_nexys_video_clkin_PLL.xci
include -c AIDA_tlu/boards/digilent/base_fw/synth digilent_nexys_video_infra.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
src --cd ../ucf TLU_digilent_nexys_video_v1e.tcl
# Use local file rather than external contrib
src --cd ../ucf digilent_nexys_video_contrib.tcl
#src -- digilent:boards/digilent_nexys_video/synth --cd ../ucf digilent_nexys_video.tcl
src --cd ../ucf I2C_constr_digilent_nexys_video.xdc
AIDA_tlu/projects/TLU_v1e/firmware/cfg/top_tlu_1e_digilent_nexys_video.dep 0 → 100755
View file @ 978bf193
include digilent_nexys_video.dep
include tlu_1e.dep
AIDA_tlu/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
View file @ 978bf193
......@@ -51,7 +51,7 @@ use work.ipbus.ALL;
entity top is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000027"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"1e000025"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......@@ -62,18 +62,15 @@ entity top is
g_BUILD_SIMULATED_MAC :integer := 0
);
port(
-- Voltage regulator setting
vadj: out std_logic_vector(1 downto 0);
--Clock
osc_clk: in std_logic; --100 MHz clock input from xtal osc
osc_clk: in std_logic; --50 MHz clock input from FPGA
--clk_enclustra: in std_logic; --Enclustra onboard oscillator 50 MHz. Used for the IPBus block
sysclk_50_o_p : out std_logic; --50 MHz clock output to FMC pins
sysclk_50_o_n : out std_logic; --50 MHz clock output to FMC pins
sysclk_40_i_p: in std_logic;
sysclk_40_i_n: in std_logic;
--Misc
leds: out std_logic_vector(7 downto 0); -- status LEDs
leds: out std_logic_vector(3 downto 0); -- status LEDs
--dip_sw: in std_logic_vector(3 downto 0); -- switches
--cfg: in std_logic_vector(3 downto 0); -- switches
gpio: out std_logic; -- gpio pin on J1 (eventually make it inout)
......@@ -121,7 +118,6 @@ end top;
architecture rtl of top is
signal osc_clk_50MHz: std_logic;
signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, clk_200, sysclk_40, clk_encl_buf, userled: std_logic;
signal mac_addr: std_logic_vector(47 downto 0);
signal ip_addr: std_logic_vector(31 downto 0);
......@@ -179,16 +175,6 @@ architecture rtl of top is
signal ctrl, stat: ipb_reg_v(0 downto 0);
--My signals
--SIGNAL busy_toggle_o : std_logic_vector(g_NUM_DUTS-1 downto 0);
component clkinPLL
port
(-- Clock in ports
-- Clock out ports
clk_out1 : out std_logic;
clk_in1 : in std_logic
);
end component;
----------------------------------------------
----------------------------------------------
......@@ -434,44 +420,6 @@ end component;
begin
led_flash: process(osc_clk_50MHz)
variable t: natural:=0;
variable v: std_logic_vector(3 downto 0);
begin
if (rising_edge(osc_clk_50MHz)) then
t := t + 1;
if (t >= 250000000) then t := 0; end if;
if (t = 0) then
v := "0000";
elsif (t > 200000000) then
v := "1111";
elsif (t > 150000000) then
v := "0111";
elsif (t > 100000000) then
v := "0011";
elsif (t > 50000000) then
v := "0001";
end if;
leds(7 downto 4) <= v;
end if;
end process;
-- Enclustra board had 50MHz clock input whereas the Digilent has 100MHz input
-- use PLL to convert the 100MHz down to 50MHz so it is compatible with the original firmware
INPUT_CLK_PLL: clkinPLL port map (
clk_out1 => osc_clk_50MHz,
clk_in1 => osc_clk
);
Vadj <= "10"; -- set voltage regulator to 2.5V
--led_iic_test <= iic_test;
--Implicit instantiation of output tristate buffers.
......@@ -845,7 +793,7 @@ Vadj <= "10"; -- set voltage regulator to 2.5V
IBUFG_inst: IBUFG
port map (
O => clk_encl_buf,
I => osc_clk_50MHz -- clk_enclustra
I => osc_clk -- clk_enclustra
);
------------------------------------------
......
AIDA_tlu/projects/TLU_v1e/firmware/ucf/I2C_constr_digilent_nexys_video.xdc 0 → 100755
View file @ 978bf193
#set_property IOSTANDARD LVCMOS33 [get_ports i2c_reset]
set_property IOSTANDARD LVCMOS25 [get_ports i2c_reset]
set_property PACKAGE_PIN E19 [get_ports i2c_reset]
set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl_b]
#set_property IOSTANDARD LVCMOS25 [get_ports i2c_scl_b]
set_property PACKAGE_PIN W5 [get_ports i2c_scl_b]
set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda_b]
#set_property IOSTANDARD LVCMOS25 [get_ports i2c_sda_b]
set_property PACKAGE_PIN V5 [get_ports i2c_sda_b]
# -------------------------------------------------------------------------------------------------
#DEBUG PROBES
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_digilent_nexys_video_v1e.tcl 0 → 100755
View file @ 978bf193
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
## Trigger inputs
#set_property IOSTANDARD LVCMOS18 [get_ports {threshold_discr_p_i[*]}]
#set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
#set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {threshold_discr_n_i[*]}]
set_property PACKAGE_PIN A15 [get_ports {threshold_discr_p_i[0]}]
set_property PACKAGE_PIN A16 [get_ports {threshold_discr_n_i[0]}]
set_property PACKAGE_PIN F13 [get_ports {threshold_discr_p_i[1]}]
set_property PACKAGE_PIN F14 [get_ports {threshold_discr_n_i[1]}]
set_property PACKAGE_PIN A13 [get_ports {threshold_discr_p_i[2]}]
set_property PACKAGE_PIN A14 [get_ports {threshold_discr_n_i[2]}]
set_property PACKAGE_PIN E13 [get_ports {threshold_discr_p_i[3]}]
set_property PACKAGE_PIN E14 [get_ports {threshold_discr_n_i[3]}]
set_property PACKAGE_PIN C13 [get_ports {threshold_discr_p_i[4]}]
set_property PACKAGE_PIN B13 [get_ports {threshold_discr_n_i[4]}]
set_property PACKAGE_PIN C14 [get_ports {threshold_discr_p_i[5]}]
set_property PACKAGE_PIN C15 [get_ports {threshold_discr_n_i[5]}]
## Miscellaneous I/O
set_property IOSTANDARD LVCMOS25 [get_ports clk_gen_rst]
set_property PACKAGE_PIN D19 [get_ports clk_gen_rst]
set_property IOSTANDARD LVCMOS25 [get_ports gpio]
set_property PACKAGE_PIN B16 [get_ports gpio]
## Crystal clock
set_property IOSTANDARD LVDS_25 [get_ports sysclk_40_i_p]
set_property PACKAGE_PIN J19 [get_ports sysclk_40_i_p]
set_property PACKAGE_PIN H19 [get_ports sysclk_40_i_n]
## Output clock (currently not working so set to 0)
set_property IOSTANDARD LVCMOS25 [get_ports sysclk_50_o_p]
set_property PACKAGE_PIN C18 [get_ports sysclk_50_o_p]
set_property IOSTANDARD LVCMOS25 [get_ports sysclk_50_o_n]
set_property PACKAGE_PIN C19 [get_ports sysclk_50_o_n]
## Inputs/Outputs for DUTs
set_property IOSTANDARD LVCMOS25 [get_ports {busy_o[*]}]
set_property PACKAGE_PIN L19 [get_ports {busy_o[0]}]
set_property PACKAGE_PIN K17 [get_ports {busy_o[1]}]
set_property PACKAGE_PIN J22 [get_ports {busy_o[2]}]
set_property PACKAGE_PIN L16 [get_ports {busy_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {triggers_o[*]}]
set_property PACKAGE_PIN M15 [get_ports {triggers_o[0]}]
set_property PACKAGE_PIN H20 [get_ports {triggers_o[1]}]
set_property PACKAGE_PIN K21 [get_ports {triggers_o[2]}]
set_property PACKAGE_PIN L14 [get_ports {triggers_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {cont_o[*]}]
set_property PACKAGE_PIN K18 [get_ports {cont_o[0]}]
set_property PACKAGE_PIN J20 [get_ports {cont_o[1]}]
set_property PACKAGE_PIN M18 [get_ports {cont_o[2]}]
set_property PACKAGE_PIN N18 [get_ports {cont_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {spare_o[*]}]
set_property PACKAGE_PIN N20 [get_ports {spare_o[0]}]
set_property PACKAGE_PIN M21 [get_ports {spare_o[1]}]
set_property PACKAGE_PIN N22 [get_ports {spare_o[2]}]
set_property PACKAGE_PIN M13 [get_ports {spare_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dut_clk_o[*]}]
set_property PACKAGE_PIN G17 [get_ports {dut_clk_o[0]}]
set_property PACKAGE_PIN B17 [get_ports {dut_clk_o[1]}]
set_property PACKAGE_PIN D17 [get_ports {dut_clk_o[2]}]
set_property PACKAGE_PIN A18 [get_ports {dut_clk_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {cont_i[*]}]
set_property PACKAGE_PIN K19 [get_ports {cont_i[0]}]
set_property PACKAGE_PIN J21 [get_ports {cont_i[1]}]
set_property PACKAGE_PIN L18 [get_ports {cont_i[2]}]
set_property PACKAGE_PIN N19 [get_ports {cont_i[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {spare_i[*]}]
set_property PACKAGE_PIN M20 [get_ports {spare_i[0]}]
set_property PACKAGE_PIN L21 [get_ports {spare_i[1]}]
set_property PACKAGE_PIN M22 [get_ports {spare_i[2]}]
set_property PACKAGE_PIN L13 [get_ports {spare_i[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {triggers_i[*]}]
set_property PACKAGE_PIN M16 [get_ports {triggers_i[0]}]
set_property PACKAGE_PIN G20 [get_ports {triggers_i[1]}]
set_property PACKAGE_PIN K22 [get_ports {triggers_i[2]}]
set_property PACKAGE_PIN L15 [get_ports {triggers_i[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {busy_i[*]}]
set_property PACKAGE_PIN L20 [get_ports {busy_i[0]}]
set_property PACKAGE_PIN J17 [get_ports {busy_i[1]}]
set_property PACKAGE_PIN H22 [get_ports {busy_i[2]}]
set_property PACKAGE_PIN K16 [get_ports {busy_i[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dut_clk_i[*]}]
set_property PACKAGE_PIN G18 [get_ports {dut_clk_i[0]}]
set_property PACKAGE_PIN B18 [get_ports {dut_clk_i[1]}]
set_property PACKAGE_PIN C17 [get_ports {dut_clk_i[2]}]
set_property PACKAGE_PIN A19 [get_ports {dut_clk_i[3]}]
# -------------------------------------------------------------------------------------------------
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
# Clocks
create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_ports sysclk_40_i_p]
# sysclk is asynchronous to the oscillator
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks osc_clk_100MHz] -group [get_clocks -include_generated_clocks sysclk_40_i_p]
# Tidy up timing report by putting in (bogus) constraints on trigger inputs
set_input_delay -clock [get_clocks s_clk320] -min 1.700 [get_ports {threshold_discr_p_i[*]}]
set_input_delay -clock [get_clocks s_clk320] -max 1.710 [get_ports {threshold_discr_p_i[*]}]
# Cycle is kept.
# N.B. Make sure timing relationship is correctly documented!
set_input_delay -clock [get_clocks s_clk160] -min 3.200 [get_ports {busy_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -max 3.300 [get_ports {busy_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -min 3.200 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -max 3.300 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks ipbus_clk] -min 15.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks ipbus_clk] -max 17.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks ipbus_clk] -min 15.000 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks ipbus_clk] -max 17.000 [get_ports i2c_sda_b]
AIDA_tlu/projects/TLU_v1e/firmware/ucf/digilent_nexys_video_contrib.tcl 0 → 100755
View file @ 978bf193
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
proc false_path {patt clk} {
set p [get_ports -quiet $patt -filter {direction != out}]
if {[llength $p] != 0} {
set_input_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != out}]
set_false_path -from [get_ports $patt -filter {direction != out}]
}
set p [get_ports -quiet $patt -filter {direction != in}]
if {[llength $p] != 0} {
set_output_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != in}]
set_false_path -to [get_ports $patt -filter {direction != in}]
}
}
# System oscillator clock
create_clock -period 10.000 -name osc_clk_100MHz [get_ports osc_clk_100MHz]
set_property IOSTANDARD LVCMOS33 [get_ports osc_clk_100MHz]
set_property PACKAGE_PIN R4 [get_ports osc_clk_100MHz]
#voltage adjust pins
set_property IOSTANDARD LVCMOS25 [get_ports {vadj[*]}]
set_property PACKAGE_PIN AB17 [get_ports {vadj[1]}]
set_property PACKAGE_PIN AA13 [get_ports {vadj[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {leds[*]}]
set_property SLEW SLOW [get_ports {leds[*]}]
set_property PACKAGE_PIN T14 [get_ports {leds[0]}]
set_property PACKAGE_PIN T15 [get_ports {leds[1]}]
set_property PACKAGE_PIN T16 [get_ports {leds[2]}]
set_property PACKAGE_PIN U16 [get_ports {leds[3]}]
set_property PACKAGE_PIN V15 [get_ports {leds[4]}]
set_property PACKAGE_PIN W16 [get_ports {leds[5]}]
set_property PACKAGE_PIN W15 [get_ports {leds[6]}]
set_property PACKAGE_PIN Y13 [get_ports {leds[7]}]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_*]
set_property PACKAGE_PIN Y12 [get_ports {rgmii_txd[0]}]
set_property PACKAGE_PIN W12 [get_ports {rgmii_txd[1]}]
set_property PACKAGE_PIN W11 [get_ports {rgmii_txd[2]}]
set_property PACKAGE_PIN Y11 [get_ports {rgmii_txd[3]}]
set_property PACKAGE_PIN V10 [get_ports rgmii_tx_ctl]
set_property PACKAGE_PIN AA14 [get_ports rgmii_txc]
set_property PACKAGE_PIN AB16 [get_ports {rgmii_rxd[0]}]
set_property PACKAGE_PIN AA15 [get_ports {rgmii_rxd[1]}]
set_property PACKAGE_PIN AB15 [get_ports {rgmii_rxd[2]}]
set_property PACKAGE_PIN AB11 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN W10 [get_ports rgmii_rx_ctl]
set_property PACKAGE_PIN V13 [get_ports rgmii_rxc]
set_property IOSTANDARD LVCMOS33 [get_ports phy_rstn]
set_property PACKAGE_PIN U7 [get_ports phy_rstn]
false_path {phy_rstn} osc_clk_100MHz
# UART pins (not always used).
# AA19 bank 0 (config). V18 bank 14, 3v3
set_property IOSTANDARD LVCMOS33 [get_ports {FTDI_*}]
set_property PACKAGE_PIN AA19 [get_ports {FTDI_RXD}]
set_property PACKAGE_PIN V18 [get_ports {FTDI_TXD}]
## Configuration options.
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
# Configuration pins on bank 16, Vadj.
if { [llength [get_ports {cfg[*]}]] > 0} {
set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
set_property PACKAGE_PIN E22 [get_ports {cfg[0]}]
set_property PACKAGE_PIN F21 [get_ports {cfg[1]}]
set_property PACKAGE_PIN G21 [get_ports {cfg[2]}]
set_property PACKAGE_PIN G22 [get_ports {cfg[3]}]
}
# Clock constraints
set_false_path -through [get_pins infra/clocks/rst_reg/Q]
set_false_path -through [get_nets infra/clocks/nuke_i]
# IPbus clock
create_generated_clock -name ipbus_clk -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT3]
# Ethernet clock
create_generated_clock -name clk_125 -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT1]
create_generated_clock -name clk_125_90 -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT2]
# 200 Mhz derived clock
create_generated_clock -name clk_200 -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT4]
# 40 Mhz derived clock
create_generated_clock -name clk_aux -source [get_pins infra/clocks/mmcm/CLKIN1] [get_pins infra/clocks/mmcm/CLKOUT5]
# Asynchronous clock groupings
set_clock_groups -asynchronous -group [get_clocks ipbus_clk] -group [get_clocks -include_generated_clocks [get_clocks clk_aux]]
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