coarse_timestamp_o:OUTstd_logic_vector(g_COUNTER_TRIG_WIDTH-1DOWNTO0);--! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
reset_timestamp_i:INstd_logic;--! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_i:INstd_logic;--! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_o:OUTstd_logic--! Goes high for one clock cycle of clk_4x_logic when timestamp reset
reset_timestamp_o:OUTstd_logic--! Goes high for one clock cycle of clk_4x_logic when timestamp reset
);
);
...
@@ -134,8 +136,7 @@ ARCHITECTURE rtl OF eventFormatter IS
...
@@ -134,8 +136,7 @@ ARCHITECTURE rtl OF eventFormatter IS
signals_data_o:std_logic_vector(g_EVENT_DATA_WIDTH-1DOWNTO0);-- Multiplexed data from FIFOs
signals_data_o:std_logic_vector(g_EVENT_DATA_WIDTH-1DOWNTO0);-- Multiplexed data from FIFOs
constantc_COARSE_TIMESTAMP_WIDTH:positive:=48;-- ! Number of bits in 40MHz timestamp
g_NUM_COARSE_TS_BITS:natural:=3;--! Number of coarse ( clk_1x_logic normally 40MHz ) timestamp bits to add to MSB of trigger times.
g_IPBUS_WIDTH:positive:=32
g_IPBUS_WIDTH:positive:=32
);
);
PORT(
PORT(
...
@@ -94,6 +95,7 @@ ENTITY triggerInputs_newTLU IS
...
@@ -94,6 +95,7 @@ ENTITY triggerInputs_newTLU IS
threshold_discr_p_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_p_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_n_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_n_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
reset_i:INstd_logic;
reset_i:INstd_logic;
coarse_timestamp_i:instd_logic_vector(g_NUM_COARSE_TS_BITS-1DOWNTO0);--! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
trigger_times_o:OUTt_triggerTimeArray(g_NUM_INPUTS-1DOWNTO0);--! trigger arrival time ( w.r.t. logic_strobe)
trigger_times_o:OUTt_triggerTimeArray(g_NUM_INPUTS-1DOWNTO0);--! trigger arrival time ( w.r.t. logic_strobe)
trigger_o:OUTstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
trigger_o:OUTstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
--trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
--trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
...
@@ -199,7 +201,11 @@ BEGIN
...
@@ -199,7 +201,11 @@ BEGIN
--BEGIN FOR LOOP
--BEGIN FOR LOOP
-- Instantiate one for each trigger input of the TLU
-- Instantiate one for each trigger input of the TLU
coarse_timestamp_i:instd_logic_vector(g_NUM_COARSE_TS_BITS-1DOWNTO0);--! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
@@ -64,6 +66,7 @@ architecture bench of triggerInputs_newTLU_tb is
...
@@ -64,6 +66,7 @@ architecture bench of triggerInputs_newTLU_tb is
signalclk_8x_logic_i:std_logic;
signalclk_8x_logic_i:std_logic;
signalclk_logic:std_logic;
signalclk_logic:std_logic;
signalstrobe_8x_logic_i:std_logic;
signalstrobe_8x_logic_i:std_logic;
signals_coarse_timestamp:std_logic_vector(c_TRIGIN_NUM_COARSE_TS_BITS-1downto0):=(others=>'0');-- counts on each strobe_4x_logic pulse
-- constant C_NUM_STROBE_TAPS : positive := 2; --! Adjust to shift strobes relative to 40MHz clock edge
-- constant C_NUM_STROBE_TAPS : positive := 2; --! Adjust to shift strobes relative to 40MHz clock edge
-- signal s_clk40_delayed_160 : std_logic_vector(C_NUM_STROBE_TAPS downto 0); --! Shift register used to generate clock_4x strobe. Adjust length for correct alignment with incoming clock
-- signal s_clk40_delayed_160 : std_logic_vector(C_NUM_STROBE_TAPS downto 0); --! Shift register used to generate clock_4x strobe. Adjust length for correct alignment with incoming clock
-- signal s_clk40_delayed_320 : std_logic_vector((2*C_NUM_STROBE_TAPS)+1 downto 0); --! Shift register used to generate clock_8x strobe. Adjust length for correct alignment with incoming clock
-- signal s_clk40_delayed_320 : std_logic_vector((2*C_NUM_STROBE_TAPS)+1 downto 0); --! Shift register used to generate clock_8x strobe. Adjust length for correct alignment with incoming clock
...
@@ -97,6 +100,7 @@ begin
...
@@ -97,6 +100,7 @@ begin
threshold_discr_p_i=>threshold_discr_p_i,
threshold_discr_p_i=>threshold_discr_p_i,
threshold_discr_n_i=>threshold_discr_n_i,
threshold_discr_n_i=>threshold_discr_n_i,
reset_i=>s_logic_reset,
reset_i=>s_logic_reset,
coarse_timestamp_i=>s_coarse_timestamp,
trigger_times_o=>trigger_times_o,
trigger_times_o=>trigger_times_o,
trigger_o=>trigger_o,
trigger_o=>trigger_o,
edge_rising_times_o=>edge_rising_times_o,
edge_rising_times_o=>edge_rising_times_o,
...
@@ -156,8 +160,9 @@ begin
...
@@ -156,8 +160,9 @@ begin
triggerNumber_o=>open,
triggerNumber_o=>open,
timeStamp_o=>open
timeStamp_o=>open
);
);
threshold_discr_p_i<=s_pulses;
threshold_discr_n_i<=nots_pulses;
threshold_discr_p_i<=s_pulses;
threshold_discr_n_i<=nots_pulses;
clockGenerator:entitywork.logic_clocks
clockGenerator:entitywork.logic_clocks
portmap(
portmap(
...
@@ -204,5 +209,20 @@ threshold_discr_n_i <= not s_pulses;
...
@@ -204,5 +209,20 @@ threshold_discr_n_i <= not s_pulses;
coarse_timestamp_o:outstd_logic_vector(g_COUNTER_TRIG_WIDTH-1DOWNTO0);--! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
reset_timestamp_i:INstd_logic;--! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_i:INstd_logic;--! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
reset_timestamp_o:OUTstd_logic--! Goes high for one clock cycle of clk_4x_logic when timestamp reset
reset_timestamp_o:OUTstd_logic--! Goes high for one clock cycle of clk_4x_logic when timestamp reset
);
);
...
@@ -320,7 +323,8 @@ architecture rtl of top is
...
@@ -320,7 +323,8 @@ architecture rtl of top is
----------------------------------------------
----------------------------------------------
COMPONENTtriggerInputs_newTLU
COMPONENTtriggerInputs_newTLU
GENERIC(
GENERIC(
g_NUM_INPUTS:natural:=1;
g_NUM_INPUTS:natural:=1;
g_NUM_COARSE_TS_BITS:natural:=3;--! Number of coarse ( clk_1x_logic normally 40MHz ) timestamp bits to add to MSB of trigger times.
g_IPBUS_WIDTH:positive:=32
g_IPBUS_WIDTH:positive:=32
);
);
PORT(
PORT(
...
@@ -332,6 +336,7 @@ architecture rtl of top is
...
@@ -332,6 +336,7 @@ architecture rtl of top is
threshold_discr_p_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_p_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_n_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
threshold_discr_n_i:INstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! inputs from threshold comparators
reset_i:INstd_logic;
reset_i:INstd_logic;
coarse_timestamp_i:instd_logic_vector(g_NUM_COARSE_TS_BITS-1DOWNTO0);--! Global timestamp. Clocked on clk_4x_logic, but only increments with logic_strobe
trigger_times_o:OUTt_triggerTimeArray(g_NUM_INPUTS-1DOWNTO0);--! trigger arrival time ( w.r.t. logic_strobe)
trigger_times_o:OUTt_triggerTimeArray(g_NUM_INPUTS-1DOWNTO0);--! trigger arrival time ( w.r.t. logic_strobe)
trigger_o:OUTstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
trigger_o:OUTstd_logic_vector(g_NUM_INPUTS-1DOWNTO0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
--trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
--trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold