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AIDA-2020 TLU - Gateware
Commit c0c02dcb authored by David Cussans's avatar David Cussans
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Updated build script

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AIDA_tlu/scripts/build_tlu_firmware.sh
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#!/bin/sh #!/bin/sh
IPBUS_BRANCH="enhancement/68"
mkdir work mkdir work
cd work cd work
git clone git@github.com:ipbus/ipbb.git # git clone git@github.com:ipbus/ipbb.git
# ( ... or curl -L https://github.com/ipbus/ipbb/archive/v0.2.5.tar.gz | tar xvz ) # ( ... or curl -L https://github.com/ipbus/ipbb/archive/v0.2.5.tar.gz | tar xvz )
curl -L https://github.com/ipbus/ipbb/archive/v0.3.11.tar.gz | tar xvz
ln -s ipbb-0.3.11 ipbb
source ipbb/env.sh source ipbb/env.sh
ipbb init build ipbb init build
cd build cd build
ipbb add git https://github.com/ipbus/ipbus-firmware.git -b enhancement/28 ipbb add git https://github.com/ipbus/ipbus-firmware.git -b ${IPBUS_BRANCH}
ipbb add git git@github.com:DavidCussans/firmware_AIDA.git ipbb add git git://ohwr.org/fmc-projects/fmc-mtlu/fmc-mtlu-gw.git
# For read/write load a valid ssh key and use
# ipbb add git ssh://git@ohwr.org/fmc-projects/fmc-mtlu/fmc-mtlu-gw.git
# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html # In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
echo "Generating address table VHDL from XML file" echo "Generating address table VHDL from XML file"
pushd src/firmware_AIDA/projects/TLU_v1e/addr_table pushd src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/addr_table
pwd pwd
/opt/cactus/bin/uhal/tools/gen_ipbus_addr_decode -v TLUaddrmap.xml /opt/cactus/bin/uhal/tools/gen_ipbus_addr_decode -v TLUaddrmap.xml
#copy resulting file ( ipbus_decode_TLUaddrmap.vhd ) to work/build/src/firmware_AIDA/projects/TLU_v1e/firmware/hdl/ #copy resulting file ( ipbus_decode_TLUaddrmap.vhd ) to work/build/src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/hdl/
cp ipbus_decode_TLUaddrmap.vhd ../firmware/hdl/ mv ipbus_decode_TLUaddrmap.vhd ../firmware/hdl/
popd popd
# Edit the files in the IPBus repostitory to expose the 200MHz clock # Edit the files in the IPBus repostitory to expose the 200MHz clock
...@@ -29,17 +34,17 @@ sed -i 's/clk125_o: out std_logic/clk125_o, clk_200_o: out std_logic/' src/ipbus ...@@ -29,17 +34,17 @@ sed -i 's/clk125_o: out std_logic/clk125_o, clk_200_o: out std_logic/' src/ipbus
# Comment out the cfg signals in the IPBus constraints file enclustra_ax3_pm3.tcl # Comment out the cfg signals in the IPBus constraints file enclustra_ax3_pm3.tcl
echo "BUILD: patching /enclustra_ax3_pm3.patch" echo "BUILD: patching /enclustra_ax3_pm3.patch"
pushd src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf pushd src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf
patch < ../../../../../../../firmware_AIDA/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch patch < ../../../../../../../fmc-mtlu-gw/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch
popd popd
echo "BUILD: ipbb proj create" echo "BUILD: ipbb proj create"
ipbb proj create vivado TLU_1e firmware_AIDA:projects/TLU_v1e -t top_tlu_1e_a35.dep ipbb proj create vivado TLU_1e fmc-mtlu-gw:AIDA_tlu/projects/TLU_v1e -t top_tlu_1e_a35.dep
cd proj/TLU_1e cd proj/TLU_1e
ipbb vivado project ipbb vivado project
# Set correct file as design "top" # Set correct file as design "top"
#echo "BUILD: Setting the correct design as top" #echo "BUILD: Setting the correct design as top"
#vivado -mode tcl -nojournal -nolog -notrace -source ../../src/firmware_AIDA/projects/TLU_v1e/firmware/cfg/set_top.tcl top/top.xpr #vivado -mode tcl -nojournal -nolog -notrace -source ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/cfg/set_top.tcl top/top.xpr
echo "BUILD: ipbb impl" echo "BUILD: ipbb impl"
......
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