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AIDA-2020 TLU - Hardware
Commit 679c6aed authored by David Cussans's avatar David Cussans
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Adding files after FMC mini-TLU version "c" schematic complete. 

Added some new blocks ( fmc_tlu_clock_gen ,fmc_tlu_hdmi_dut_connector , fmc_tlu_threshold_discriminator_dual )

Printed out schematic ( fmc_tlu_v1c.pdf )
parent a648eb8d
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Cadence/adw/shoppingCart.xml
View file @ 679c6aed
...@@ -90,4 +90,47 @@ ...@@ -90,4 +90,47 @@
<property name="PACK_TYPE" value="SOD123-CA"/> <property name="PACK_TYPE" value="SOD123-CA"/>
<property name="TYPE" value="BZT52-C3V6"/> <property name="TYPE" value="BZT52-C3V6"/>
</component> </component>
<component cell="si5345" library="cninterface" partname="SI5345" partno="Si5345A-B-GM" quantity="1" >
<property name="PACK_TYPE" value="QFN"/>
<property name="TYPE" value="Si5345A-B-GM"/>
</component>
<component cell="rsmd0603" library="cnpassive" partname="RSMD0603" partno="R0603_1K_1%_0.1W_100PPM" quantity="1" >
<property name="PACK_TYPE" value="1/10W"/>
<property name="TOL" value="1%"/>
<property name="VALUE" value="1k"/>
</component>
<component cell="lp38692sd" library="bris_cds_analogue" partname="LP38692SD" partno="LP38692SD-1.8" quantity="1" >
<property name="MANUF" value="Texas Instruments"/>
<property name="PACK_TYPE" value="WSON"/>
<property name="VALUE" value="1.8V"/>
</component>
<component cell="rsmd0603" library="cnpassive" partname="RSMD0603" partno="R0603_XX_1%_0.1W_100PPM" quantity="1" >
<property name="PACK_TYPE" value="1/10W"/>
<property name="TOL" value="1%"/>
<property name="VALUE" value="XX"/>
</component>
<component cell="rsmd0603" library="cnpassive" partname="RSMD0603" partno="R0603_00_JUMPER" quantity="1" >
<property name="PACK_TYPE" value=""/>
<property name="TOL" value=""/>
<property name="VALUE" value="00"/>
</component>
<component cell="pca9555" library="bris_cds_analogue" partname="PCA9555" partno="PCA9555" quantity="1" >
<property name="MANUF" value="NXP"/>
<property name="PACK_TYPE" value="SSOP24"/>
</component>
<component cell="pca9539" library="cninterface" partname="PCA9539" partno="PCA9539PW" quantity="1" >
<property name="PACK_TYPE" value="TSSOP"/>
<property name="TYPE" value="PCA9539PW"/>
</component>
<component cell="led1" library="cndiscrete" partname="LED1" partno="597-3111-502F" quantity="1" >
<property name="TYPE" value="597_RED"/>
</component>
<component cell="led1" library="cndiscrete" partname="LED1" partno="597-3301-502F" quantity="1" >
<property name="TYPE" value="597_GREEN"/>
</component>
<component cell="rsmd0603" library="cnpassive" partname="RSMD0603" partno="R0603_82R_1%_0.1W_100PPM" quantity="1" >
<property name="PACK_TYPE" value="1/10W"/>
<property name="TOL" value="1%"/>
<property name="VALUE" value="82"/>
</component>
</sc:shoppingCart> </sc:shoppingCart>
Cadence/cp.log 0 → 100644
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Cadence/cp_log.log 0 → 100644
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Cadence/cp_script.scr 0 → 100644
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hier_write -quit
Cadence/fmc_tlu_clock_gen.cpm 0 → 100644
View file @ 679c6aed
{ Machine generated file created by SPI }
{ Last modified was 15:19:04 Wednesday, June 08, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/fmc_tlu_clock_gen/physical'
design_name 'fmc_tlu_clock_gen'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors' 'cds_special' 'cnmech' 'cnspecial'
temp_dir 'temp'
cpm_version '16.3'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_tlu_clock_gen/physical'
trapezoidal_angle_in_degree '90.000000'
session_name 'ProjectMgr8446'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_TOGGLE 'ON'
LOGIC_GRID_SIZE '0.0500'
SYMBOL_GRID_TOGGLE 'ON'
DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
repackage 'ON'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
GEN_SUBDESIGN 'fmc_tlu_clock_gen'
FORCE_SUBDESIGN
f2b_overwrite_constraints 'OFF'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_clk_gen_01.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
show_report 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_tlu_toplevel_b/bom/fmc_tlu_v1a.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_PDF
CURRENTPDFVIEWER '0'
CURRENTPDFVIEWERPATH 'Default'
END_PDF
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
Cadence/fmc_tlu_hdmi_dut_connector.cpm 0 → 100644
View file @ 679c6aed
{ Machine generated file created by SPI }
{ Last modified was 13:52:18 Wednesday, June 08, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/fmc_tlu_hdmi_dut_connector/physical'
design_name 'fmc_tlu_hdmi_dut_connector'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors' 'cds_special' 'cnmech' 'cnspecial'
temp_dir 'temp'
cpm_version '16.3'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_tlu_hdmi_dut_connector/physical'
trapezoidal_angle_in_degree '90.000000'
session_name 'ProjectMgr8446'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_TOGGLE 'ON'
LOGIC_GRID_SIZE '0.0500'
SYMBOL_GRID_TOGGLE 'ON'
DOC_GRID_TOGGLE 'ON'
DOC_GRID_SIZE '0.0500'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
repackage 'ON'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
GEN_SUBDESIGN 'fmc_tlu_hdmi_dut_connector'
FORCE_SUBDESIGN
f2b_overwrite_constraints 'OFF'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_hdmi_dut_connector_unplaced.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
show_report 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/fmc_tlu_toplevel_b/bom/fmc_tlu_v1a.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_PDF
CURRENTPDFVIEWER '0'
CURRENTPDFVIEWERPATH 'Default'
END_PDF
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
Cadence/fmc_tlu_rj45_lvds_adaptor.ps 0 → 100644
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This diff is collapsed.
Cadence/fmc_tlu_threshold_discriminator_dual.cpm 0 → 100644
View file @ 679c6aed
{ Machine generated file created by SPI }
{ Last modified was 14:40:25 Wednesday, June 08, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/fmc_tlu_threshold_discriminator_dual/physical'
design_name 'fmc_tlu_threshold_discriminator_dual'
design_library 'fmc_tlu_v1_lib'
library 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cnconnector' 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete' 'standard' 'cds_analogue' 'cds_standard' 'cn100e'
temp_dir 'temp'
cpm_version '16.3'
session_name 'ProjectMgr7259'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
cdsprop_file ''
physical_path './worklib/fmc_tlu_threshold_discriminator_dual/physical'
END_GLOBAL
START_CONCEPTHDL
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL
START_PKGRXL
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'ON'
gen_subdesign 'fmc_tlu_threshold_discriminator_dual'
f2b_overwrite_constraints 'ON'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'fmc_tlu_threshold_discriminator_dual_01.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
show_report 'NO'
END_DESIGNSYNC
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
Cadence/fmc_tlu_v1c.cpm
View file @ 679c6aed
{ Machine generated file created by SPI } { Machine generated file created by SPI }
{ Last modified was 15:16:35 Friday, May 20, 2016 } { Last modified was 15:28:36 Wednesday, June 08, 2016 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by } { NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. } { SPI, your modifications will be overwritten. }
...@@ -35,11 +35,12 @@ PLOT_EDGE_TO_EDGE 'ON' ...@@ -35,11 +35,12 @@ PLOT_EDGE_TO_EDGE 'ON'
END_CONCEPTHDL END_CONCEPTHDL
START_PKGRXL START_PKGRXL
optimize 'ON'
regenerate_physical_net_name 'OFF' regenerate_physical_net_name 'OFF'
electrical_constraints 'ON' electrical_constraints 'ON'
overwrite_constraints 'OFF' overwrite_constraints 'OFF'
GEN_SUBDESIGN GEN_SUBDESIGN
force_subdesign 'fmc_tlu_cfd' 'fmc_tlu_vsupply5v' force_subdesign 'fmc_tlu_clock_gen' 'fmc_tlu_hdmi_dut_connector' 'fmc_tlu_threshold_discriminator_dual' 'fmc_tlu_vsupply5v'
f2b_overwrite_constraints 'ON' f2b_overwrite_constraints 'ON'
END_PKGRXL END_PKGRXL
...@@ -51,7 +52,7 @@ create_user_prop 'NO' ...@@ -51,7 +52,7 @@ create_user_prop 'NO'
run_packager 'YES' run_packager 'YES'
run_netrev 'YES' run_netrev 'YES'
backannotate_forward 'NO' backannotate_forward 'NO'
last_board_file 'fmc_tlu_v1c_67.brd' last_board_file 'fmc_tlu_v1c_73.brd'
run_feedback 'YES' run_feedback 'YES'
run_genfeedformat 'YES' run_genfeedformat 'YES'
backannotate_feedback 'NO' backannotate_feedback 'NO'
...@@ -70,6 +71,13 @@ last_callout_file '' ...@@ -70,6 +71,13 @@ last_callout_file ''
last_variant '' last_variant ''
END_BOMHDL END_BOMHDL
START_ERCDX
pin_direction_check 'OFF'
io_check 'OFF'
load_check 'OFF'
connect_check 'OFF'
END_ERCDX
START_PDF START_PDF
CURRENTPDFVIEWER '0' CURRENTPDFVIEWER '0'
CURRENTPDFVIEWERPATH 'Default' CURRENTPDFVIEWERPATH 'Default'
......
Cadence/pc042a_lib/pc042b_vsupply5v/physical/enved.jrl 0 → 100644
View file @ 679c6aed
\t (00:00:00) enved 16.5 S003 (v16-5-13K) Linux IA32
\t (00:00:00) Journal start - Tue Sep 25 12:36:21 2012
\t (00:00:00) Host=fortis.phy.bris.ac.uk User=phdgc Pid=29644 CPUs=4
\t (00:00:00)
\i (00:00:09) setwindow form.prfedit
\i (00:00:09) FORM prfedit treelist Paths
\i (00:00:12) FORM prfedit treelist Library Paths
\i (00:00:14) FORM prfedit psmpath
\i (00:00:38) FORM prfedit done
\t (00:00:38) Journal end - Tue Sep 25 12:36:59 2012
Cadence/worklib/fmc_tlu_cfd/physical/enved.jrl 0 → 100755
View file @ 679c6aed
\t (00:00:00) enved 16.5 S003 (v16-5-13K) Linux IA32
\t (00:00:00) Journal start - Thu May 10 13:15:56 2012
\t (00:00:00) Host=calgary.phy.bris.ac.uk User=phdgc Pid=12593 CPUs=4
\t (00:00:00)
\i (00:00:08) setwindow form.prfedit
\i (00:00:08) FORM prfedit treelist Library Paths
\i (00:00:14) FORM prfedit psmpath
\i (00:00:55) FORM prfedit done
\t (00:00:55) Journal end - Thu May 10 13:16:52 2012
Cadence/worklib/fmc_tlu_clock_gen/cfg_package/expand.cfg 0 → 100644
View file @ 679c6aed
config fmc_tlu_clock_gen;
design fmc_tlu_v1_lib.fmc_tlu_clock_gen:sch_1;
liblist fmc_tlu_v1_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_logic, bris_cds_memory, bris_cds_special, bris_cds_standard, bris_cds_switches, cnconnector, cninterface, cnpower, cnlinear, cnpassive, cndiscrete, standard, cds_analogue, cn100e, cn74lv, cn74tiac, cn75als, cncmos, cnfast, cnmemory, uob_hep_pc036a_lib, cds_connectors, cds_special, cnmech, cnspecial;
viewlist chips, pic_1, picopt_1, sch_1, schematic, entity, functional;
stoplist chips;
endconfig
Cadence/worklib/fmc_tlu_clock_gen/cfg_pic/expand.cfg 0 → 100644
View file @ 679c6aed
config fmc_tlu_clock_gen;
design fmc_tlu_v1_lib.fmc_tlu_clock_gen:sch_1;
liblist fmc_tlu_v1_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_logic, bris_cds_memory, bris_cds_special, bris_cds_standard, bris_cds_switches, cnconnector, cninterface, cnpower, cnlinear, cnpassive, cndiscrete, standard, cds_analogue, cn100e, cn74lv, cn74tiac, cn75als, cncmos, cnfast, cnmemory, uob_hep_pc036a_lib, cds_connectors, cds_special, cnmech, cnspecial;
viewlist edif, vlog_rtl, vhdl_rtl, sch_1, entity;
stoplist none;
endconfig
Cadence/worklib/fmc_tlu_clock_gen/cfg_pic/master.tag 0 → 100644
View file @ 679c6aed
expand.cfg
\ No newline at end of file
Cadence/worklib/fmc_tlu_clock_gen/cfg_verilog/expand.cfg 0 → 100644
View file @ 679c6aed
config fmc_tlu_clock_gen;
design fmc_tlu_v1_lib.fmc_tlu_clock_gen:sim_sch_1;
liblist fmc_tlu_v1_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_logic, bris_cds_memory, bris_cds_special, bris_cds_standard, bris_cds_switches, cnconnector, cninterface, cnpower, cnlinear, cnpassive, cndiscrete, standard, cds_analogue, cn100e, cn74lv, cn74tiac, cn75als, cncmos, cnfast, cnmemory, uob_hep_pc036a_lib, cds_connectors, cds_special, cnmech, cnspecial;
viewlist vlog_map, hw_map, swift_map, vlog_model, hw_model, swift_model, vlog_structural, vlog_rtl, vlog_behavioral, vlog_system, mcvlog, pic_1, picopt_1, tbl_1, sim_sch_1, sch_1, entity;
stoplist vlog_model, swift_model;
endconfig
Cadence/worklib/fmc_tlu_clock_gen/cfg_vhdl/expand.cfg 0 → 100644
View file @ 679c6aed
config fmc_tlu_clock_gen;
design fmc_tlu_v1_lib.fmc_tlu_clock_gen:sim_sch_1;
liblist fmc_tlu_v1_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_logic, bris_cds_memory, bris_cds_special, bris_cds_standard, bris_cds_switches, cnconnector, cninterface, cnpower, cnlinear, cnpassive, cndiscrete, standard, cds_analogue, cn100e, cn74lv, cn74tiac, cn75als, cncmos, cnfast, cnmemory, uob_hep_pc036a_lib, cds_connectors, cds_special, cnmech, cnspecial;
viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl_system, mc_arch, pic_1, picopt_1, sim_sch_1, sch_1;
stoplist none;
endconfig
Cadence/worklib/fmc_tlu_clock_gen/cfg_vhdl/master.tag 0 → 100644
View file @ 679c6aed
expand.cfg
\ No newline at end of file
Cadence/worklib/fmc_tlu_clock_gen/entity/verilog.v 0 → 100644
View file @ 679c6aed
// generated by newgenasym Wed Jun 8 15:16:21 2016
module fmc_tlu_clock_gen (clk_from_fpga_n, clk_from_fpga_p, clk_io_1_n,
clk_io_1_p, clk_io_2, clk_n, clk_p, clk_to_fpga_n,
clk_to_fpga_p, dut_clk_from_fpga, dut_clk_to_fpga,
enable_clk_to_dut, enable_clk_to_lemo,
enable_dut_clk_from_fpga, \intr* , \lol* , \rst* , scl, sda);
input clk_from_fpga_n;
input clk_from_fpga_p;
output clk_io_1_n;
output clk_io_1_p;
output clk_io_2;
output [3:0] clk_n;
output [3:0] clk_p;
output clk_to_fpga_n;
output clk_to_fpga_p;
input [3:0] dut_clk_from_fpga;
output [3:0] dut_clk_to_fpga;
input [3:0] enable_clk_to_dut;
input enable_clk_to_lemo;
input [3:0] enable_dut_clk_from_fpga;
output \intr* ;
output \lol* ;
input \rst* ;
input scl;
input sda;
initial
begin
end
endmodule
Cadence/worklib/fmc_tlu_clock_gen/entity/vhdl.vhd 0 → 100644
View file @ 679c6aed
-- generated by newgenasym Wed Jun 8 15:16:21 2016
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity FMC_TLU_CLOCK_GEN is
port (
CLK_FROM_FPGA_N: IN std_logic;
CLK_FROM_FPGA_P: IN std_logic;
CLK_IO_1_N: OUT std_logic;
CLK_IO_1_P: OUT std_logic;
CLK_IO_2: OUT std_logic;
CLK_N: OUT std_logic_vector (3 DOWNTO 0);
CLK_P: OUT std_logic_vector (3 DOWNTO 0);
CLK_TO_FPGA_N: OUT std_logic;
CLK_TO_FPGA_P: OUT std_logic;
DUT_CLK_FROM_FPGA: IN std_logic_vector (3 DOWNTO 0);
DUT_CLK_TO_FPGA: OUT std_logic_vector (3 DOWNTO 0);
ENABLE_CLK_TO_DUT: IN std_logic_vector (3 DOWNTO 0);
ENABLE_CLK_TO_LEMO: IN std_logic;
ENABLE_DUT_CLK_FROM_FPGA: IN std_logic_vector (3 DOWNTO 0);
\intr*\: OUT std_logic;
\lol*\: OUT std_logic;
\rst*\: IN std_logic;
SCL: IN std_logic;
SDA: IN std_logic);
end FMC_TLU_CLOCK_GEN;
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pxl.state
\ No newline at end of file
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FILE_TYPE=PINLIST;
{ Packager-XL run on 08-Jun-2016 AT 15:18:50 }
TIME=' COMPILATION ON 08-Jun-2016 AT 15:18:50';
primitive '1-HOLE_0-8-BASE';body '1-HOLE';
'A'<0>:'(1)';IN;
end_primitive;
primitive 'BF-100.000MBE-T-GND=GND_SIGNALA';body 'OSC_6P_ENDIS_OUTP_OUTN';
'ENDIS':'(1)';IN;
'OUTP':'(4)';OUT;
'OUTN':'(5)';OUT;
end_primitive;
primitive 'CAPCERSMDCL2_0402-100NF,16V_GEN';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0603-100NF,16V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0603-10UF,6.3V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0805-22UF,6.3V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_1210-10UF,10V_GEN';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPN4I-1UF,16V,X5R,GNM21';body 'CAPN4I';
'B'<0>:'(2,4,6,8)';$S;BIDI;
'A'<0>:'(1,3,5,7)';$S;BIDI;
end_primitive;
primitive 'COMMON_MODE_LINE_FILTER_4312-7A';body 'COMMON_MODE_LINE_FILTER';
'1DOT'<0>:'(4)';
'1'<0>:'(3)';
'2DOT'<0>:'(1)';
'2'<0>:'(2)';
end_primitive;
primitive 'CON3P-SIL254D';body 'CON3P';
'A'<2>:'(3)';
'A'<1>:'(2)';
'A'<0>:'(1)';
end_primitive;
primitive 'DS92001TLD-GND=GND_SIGNAL,VCC=A';body 'DS92001';
'IN-':'(2)';IN;
'IN+':'(3)';IN;
'OUT+':'(6)';OUT;
'OUT-':'(7)';OUT;
'EN':'(8)';IN;
end_primitive;
primitive 'DS92001TLD-GND=GND_SIGNAL,VCC=B';body 'DS92001';
'IN-':'(2)';IN;
'IN+':'(3)';IN;
'OUT+':'(6)';OUT;
'OUT-':'(7)';OUT;
'EN':'(8)';IN;
end_primitive;
primitive 'FERRITE_C0805-LI0805H121R-10,LA';body 'FERRITE';
'B'<0>:'(2)';BIDI;
'A'<0>:'(1)';BIDI;
end_primitive;
primitive 'LP38692SD_WSON-1.8V,TEXAS INSTA';body 'LP38692SD';
'SNS':'(5)';IN;
'OUT':'(4)';OUT;
'IN1':'(1)';IN;
'IN2':'(6)';IN;
'EN':'(3)';IN;
'GND':'(2)';
'DAP':'(7)';
end_primitive;
primitive 'PLEMO2CI-EPG.00.302.NLN-GND=GNA';body 'PLEMO2CI';
'A':'(1)';
'B':'(2)';
end_primitive;
primitive 'RES_ARRAY_X4_1206_TC164-47,1%';body 'RES_ARRAY_X4';
'B'<0>:'(5,6,7,8)';$S;IN;
'A'<0>:'(4,3,2,1)';$S;IN;
end_primitive;
primitive 'RSMD0603_1/10W-100,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-1K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-4.7K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-XX,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'SI5345A-B-GM-GND=GND_SIGNAL,VDA';body 'SI5345';
'A0/CS':'(19)';IN;
'A1/SDO':'(17)';BIDI;
'FDEC':'(25)';IN;
'FINC':'(48)';IN;
'I2C_SEL':'(39)';IN;
'IN0':'(63)';IN;
'IN0*':'(64)';IN;
'IN1':'(1)';IN;
'IN1*':'(2)';IN;
'IN2':'(14)';IN;
'IN2*':'(15)';IN;
'IN3/FB_IN':'(61)';IN;
'IN3/FB_IN*':'(62)';IN;
'INTR*':'(12)';OUT;
'IN_SEL0':'(3)';IN;
'IN_SEL1':'(4)';IN;
'LOL*':'(47)';OUT;
'OE*':'(11)';IN;
'OUT0':'(24)';OUT;
'OUT0*':'(23)';OUT;
'OUT1':'(28)';OUT;
'OUT1*':'(27)';OUT;
'OUT2':'(31)';OUT;
'OUT2*':'(30)';OUT;
'OUT3':'(35)';OUT;
'OUT3*':'(34)';OUT;
'OUT4':'(38)';OUT;
'OUT4*':'(37)';OUT;
'OUT5':'(42)';OUT;
'OUT5*':'(41)';OUT;
'OUT6':'(45)';OUT;
'OUT6*':'(44)';OUT;
'OUT7':'(51)';OUT;
'OUT7*':'(50)';OUT;
'OUT8':'(54)';OUT;
'OUT8*':'(53)';OUT;
'OUT9':'(59)';OUT;
'OUT9*':'(58)';OUT;
'RST*':'(6)';IN;
'RSVD1':'(5)';
'RSVD2':'(20)';
'RSVD3':'(21)';
'RSVD4':'(55)';
'RSVD5':'(56)';
'SCLK':'(16)';IN;
'SDA/SDIO':'(18)';BIDI;
'VDDO0':'(22)';
'VDDO1':'(26)';
'VDDO2':'(29)';
'VDDO3':'(33)';
'VDDO4':'(36)';
'VDDO5':'(40)';
'VDDO6':'(43)';
'VDDO7':'(49)';
'VDDO8':'(52)';
'VDDO9':'(57)';
'X1':'(7)';IN;
'X2':'(10)';IN;
'XA':'(8)';IN;
'XB':'(9)';IN;
end_primitive;
primitive 'SN65MLVD040RGZ-GND=GND_SIGNAL,A';body 'SN65MLVD040';
'DE'<0>:'(1,5,8,12)';$S;IN;
'D'<0>:'(35,32,28,25)';$S;IN;
'R'<0>:'(36,33,29,26)';$S;OUT;
'A'<0>:'(47,3,9,13)';$S;OUT;
'B*'<0>:'(48,4,10,14)';$S;OUT;
'RE*'<0>:'(40,42,19,21)';$S;IN;
'FSEN'<0>:'(39,41,20,22)';$S;IN;
'PDN':'(30,30,30,30)';IN;
end_primitive;
primitive 'USBLC6-2SC6'; body 'USBLC6-2';
'I/O1'<0>:'(1)';BIDI;
'I/O2'<0>:'(3)';BIDI;
'I/O1'<1>:'(6)';BIDI;
'I/O2'<1>:'(4)';BIDI;
'GND':'(2)';
'VBUS':'(5)';
end_primitive;
END.
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstpin.dat,1 0 → 100644
View file @ 679c6aed
FILE_TYPE=PINLIST;
{ Packager-XL run on 03-Jun-2016 AT 10:45:06 }
TIME=' COMPILATION ON 03-Jun-2016 AT 10:45:06';
primitive '1-HOLE_0-8-BASE';body '1-HOLE';
'A'<0>:'(1)';IN;
end_primitive;
primitive 'BF-100.000MBE-T-GND=GND_SIGNALA';body 'OSC_6P_ENDIS_OUTP_OUTN';
'ENDIS':'(1)';IN;
'OUTP':'(4)';OUT;
'OUTN':'(5)';OUT;
end_primitive;
primitive 'CAPCERSMDCL2_0402-100NF,16V_GEN';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0603-100NF,16V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0603-10UF,6.3V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0805-22UF,6.3V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_1210-10UF,10V_GEN';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPN4I-1UF,16V,X5R,GNM21';body 'CAPN4I';
'B'<0>:'(2,4,6,8)';$S;BIDI;
'A'<0>:'(1,3,5,7)';$S;BIDI;
end_primitive;
primitive 'COMMON_MODE_LINE_FILTER_4312-7A';body 'COMMON_MODE_LINE_FILTER';
'1DOT'<0>:'(4)';
'1'<0>:'(3)';
'2DOT'<0>:'(1)';
'2'<0>:'(2)';
end_primitive;
primitive 'CON3P-SIL254D';body 'CON3P';
'A'<2>:'(3)';
'A'<1>:'(2)';
'A'<0>:'(1)';
end_primitive;
primitive 'DS92001TLD-GND=GND_SIGNAL,VCC=A';body 'DS92001';
'IN-':'(2)';IN;
'IN+':'(3)';IN;
'OUT+':'(6)';OUT;
'OUT-':'(7)';OUT;
'EN':'(8)';IN;
end_primitive;
primitive 'DS92001TLD-GND=GND_SIGNAL,VCC=B';body 'DS92001';
'IN-':'(2)';IN;
'IN+':'(3)';IN;
'OUT+':'(6)';OUT;
'OUT-':'(7)';OUT;
'EN':'(8)';IN;
end_primitive;
primitive 'FERRITE_C0805-LI0805H121R-10,LA';body 'FERRITE';
'B'<0>:'(2)';BIDI;
'A'<0>:'(1)';BIDI;
end_primitive;
primitive 'LP38692SD_WSON-1.8V,TEXAS INSTA';body 'LP38692SD';
'SNS':'(5)';IN;
'OUT':'(4)';OUT;
'IN1':'(1)';IN;
'IN2':'(6)';IN;
'EN':'(3)';IN;
'GND':'(2)';
'DAP':'(7)';
end_primitive;
primitive 'PLEMO2CI-EPG.00.302.NLN-GND=GNA';body 'PLEMO2CI';
'A':'(1)';
'B':'(2)';
end_primitive;
primitive 'RES_ARRAY_X4_1206_TC164-47,1%';body 'RES_ARRAY_X4';
'B'<0>:'(5,6,7,8)';$S;IN;
'A'<0>:'(4,3,2,1)';$S;IN;
end_primitive;
primitive 'RSMD0603_1/10W-100,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-1K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-4.7K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'SI5345A-B-GM-GND=GND_SIGNAL,VDA';body 'SI5345';
'A0/CS':'(19)';IN;
'A1/SDO':'(17)';BIDI;
'FDEC':'(25)';IN;
'FINC':'(48)';IN;
'I2C_SEL':'(39)';IN;
'IN0':'(63)';IN;
'IN0*':'(64)';IN;
'IN1':'(1)';IN;
'IN1*':'(2)';IN;
'IN2':'(14)';IN;
'IN2*':'(15)';IN;
'IN3/FB_IN':'(61)';IN;
'IN3/FB_IN*':'(62)';IN;
'INTR*':'(12)';OUT;
'IN_SEL0':'(3)';IN;
'IN_SEL1':'(4)';IN;
'LOL*':'(47)';OUT;
'OE*':'(11)';IN;
'OUT0':'(24)';OUT;
'OUT0*':'(23)';OUT;
'OUT1':'(28)';OUT;
'OUT1*':'(27)';OUT;
'OUT2':'(31)';OUT;
'OUT2*':'(30)';OUT;
'OUT3':'(35)';OUT;
'OUT3*':'(34)';OUT;
'OUT4':'(38)';OUT;
'OUT4*':'(37)';OUT;
'OUT5':'(42)';OUT;
'OUT5*':'(41)';OUT;
'OUT6':'(45)';OUT;
'OUT6*':'(44)';OUT;
'OUT7':'(51)';OUT;
'OUT7*':'(50)';OUT;
'OUT8':'(54)';OUT;
'OUT8*':'(53)';OUT;
'OUT9':'(59)';OUT;
'OUT9*':'(58)';OUT;
'RST*':'(6)';IN;
'RSVD1':'(5)';
'RSVD2':'(20)';
'RSVD3':'(21)';
'RSVD4':'(55)';
'RSVD5':'(56)';
'SCLK':'(16)';IN;
'SDA/SDIO':'(18)';BIDI;
'VDDO0':'(22)';
'VDDO1':'(26)';
'VDDO2':'(29)';
'VDDO3':'(33)';
'VDDO4':'(36)';
'VDDO5':'(40)';
'VDDO6':'(43)';
'VDDO7':'(49)';
'VDDO8':'(52)';
'VDDO9':'(57)';
'X1':'(7)';IN;
'X2':'(10)';IN;
'XA':'(8)';IN;
'XB':'(9)';IN;
end_primitive;
primitive 'SN65MLVD040RGZ-GND=GND_SIGNAL,A';body 'SN65MLVD040';
'DE'<0>:'(1,5,8,12)';$S;IN;
'D'<0>:'(35,32,28,25)';$S;IN;
'R'<0>:'(36,33,29,26)';$S;OUT;
'A'<0>:'(47,3,9,13)';$S;OUT;
'B*'<0>:'(48,4,10,14)';$S;OUT;
'RE*'<0>:'(40,42,19,21)';$S;IN;
'FSEN'<0>:'(39,41,20,22)';$S;IN;
'PDN':'(30,30,30,30)';IN;
end_primitive;
primitive 'USBLC6-2SC6'; body 'USBLC6-2';
'I/O1'<0>:'(1)';BIDI;
'I/O2'<0>:'(3)';BIDI;
'I/O1'<1>:'(6)';BIDI;
'I/O2'<1>:'(4)';BIDI;
'GND':'(2)';
'VBUS':'(5)';
end_primitive;
END.
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstpin.dat,2 0 → 100644
View file @ 679c6aed
FILE_TYPE=PINLIST;
{ Packager-XL run on 03-Jun-2016 AT 13:35:26 }
TIME=' COMPILATION ON 03-Jun-2016 AT 13:35:26';
primitive '1-HOLE_0-8-BASE';body '1-HOLE';
'A'<0>:'(1)';IN;
end_primitive;
primitive 'BF-100.000MBE-T-GND=GND_SIGNALA';body 'OSC_6P_ENDIS_OUTP_OUTN';
'ENDIS':'(1)';IN;
'OUTP':'(4)';OUT;
'OUTN':'(5)';OUT;
end_primitive;
primitive 'CAPCERSMDCL2_0402-100NF,16V_GEN';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0603-100NF,16V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0603-10UF,6.3V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0805-22UF,6.3V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_1210-10UF,10V_GEN';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPN4I-1UF,16V,X5R,GNM21';body 'CAPN4I';
'B'<0>:'(2,4,6,8)';$S;BIDI;
'A'<0>:'(1,3,5,7)';$S;BIDI;
end_primitive;
primitive 'COMMON_MODE_LINE_FILTER_4312-7A';body 'COMMON_MODE_LINE_FILTER';
'1DOT'<0>:'(4)';
'1'<0>:'(3)';
'2DOT'<0>:'(1)';
'2'<0>:'(2)';
end_primitive;
primitive 'CON3P-SIL254D';body 'CON3P';
'A'<2>:'(3)';
'A'<1>:'(2)';
'A'<0>:'(1)';
end_primitive;
primitive 'DS92001TLD-GND=GND_SIGNAL,VCC=A';body 'DS92001';
'IN-':'(2)';IN;
'IN+':'(3)';IN;
'OUT+':'(6)';OUT;
'OUT-':'(7)';OUT;
'EN':'(8)';IN;
end_primitive;
primitive 'DS92001TLD-GND=GND_SIGNAL,VCC=B';body 'DS92001';
'IN-':'(2)';IN;
'IN+':'(3)';IN;
'OUT+':'(6)';OUT;
'OUT-':'(7)';OUT;
'EN':'(8)';IN;
end_primitive;
primitive 'FERRITE_C0805-LI0805H121R-10,LA';body 'FERRITE';
'B'<0>:'(2)';BIDI;
'A'<0>:'(1)';BIDI;
end_primitive;
primitive 'LP38692SD_WSON-1.8V,TEXAS INSTA';body 'LP38692SD';
'SNS':'(5)';IN;
'OUT':'(4)';OUT;
'IN1':'(1)';IN;
'IN2':'(6)';IN;
'EN':'(3)';IN;
'GND':'(2)';
'DAP':'(7)';
end_primitive;
primitive 'PLEMO2CI-EPG.00.302.NLN-GND=GNA';body 'PLEMO2CI';
'A':'(1)';
'B':'(2)';
end_primitive;
primitive 'RES_ARRAY_X4_1206_TC164-47,1%';body 'RES_ARRAY_X4';
'B'<0>:'(5,6,7,8)';$S;IN;
'A'<0>:'(4,3,2,1)';$S;IN;
end_primitive;
primitive 'RSMD0603_1/10W-100,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-1K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-4.7K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-XX,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'SI5345A-B-GM-GND=GND_SIGNAL,VDA';body 'SI5345';
'A0/CS':'(19)';IN;
'A1/SDO':'(17)';BIDI;
'FDEC':'(25)';IN;
'FINC':'(48)';IN;
'I2C_SEL':'(39)';IN;
'IN0':'(63)';IN;
'IN0*':'(64)';IN;
'IN1':'(1)';IN;
'IN1*':'(2)';IN;
'IN2':'(14)';IN;
'IN2*':'(15)';IN;
'IN3/FB_IN':'(61)';IN;
'IN3/FB_IN*':'(62)';IN;
'INTR*':'(12)';OUT;
'IN_SEL0':'(3)';IN;
'IN_SEL1':'(4)';IN;
'LOL*':'(47)';OUT;
'OE*':'(11)';IN;
'OUT0':'(24)';OUT;
'OUT0*':'(23)';OUT;
'OUT1':'(28)';OUT;
'OUT1*':'(27)';OUT;
'OUT2':'(31)';OUT;
'OUT2*':'(30)';OUT;
'OUT3':'(35)';OUT;
'OUT3*':'(34)';OUT;
'OUT4':'(38)';OUT;
'OUT4*':'(37)';OUT;
'OUT5':'(42)';OUT;
'OUT5*':'(41)';OUT;
'OUT6':'(45)';OUT;
'OUT6*':'(44)';OUT;
'OUT7':'(51)';OUT;
'OUT7*':'(50)';OUT;
'OUT8':'(54)';OUT;
'OUT8*':'(53)';OUT;
'OUT9':'(59)';OUT;
'OUT9*':'(58)';OUT;
'RST*':'(6)';IN;
'RSVD1':'(5)';
'RSVD2':'(20)';
'RSVD3':'(21)';
'RSVD4':'(55)';
'RSVD5':'(56)';
'SCLK':'(16)';IN;
'SDA/SDIO':'(18)';BIDI;
'VDDO0':'(22)';
'VDDO1':'(26)';
'VDDO2':'(29)';
'VDDO3':'(33)';
'VDDO4':'(36)';
'VDDO5':'(40)';
'VDDO6':'(43)';
'VDDO7':'(49)';
'VDDO8':'(52)';
'VDDO9':'(57)';
'X1':'(7)';IN;
'X2':'(10)';IN;
'XA':'(8)';IN;
'XB':'(9)';IN;
end_primitive;
primitive 'SN65MLVD040RGZ-GND=GND_SIGNAL,A';body 'SN65MLVD040';
'DE'<0>:'(1,5,8,12)';$S;IN;
'D'<0>:'(35,32,28,25)';$S;IN;
'R'<0>:'(36,33,29,26)';$S;OUT;
'A'<0>:'(47,3,9,13)';$S;OUT;
'B*'<0>:'(48,4,10,14)';$S;OUT;
'RE*'<0>:'(40,42,19,21)';$S;IN;
'FSEN'<0>:'(39,41,20,22)';$S;IN;
'PDN':'(30,30,30,30)';IN;
end_primitive;
primitive 'USBLC6-2SC6'; body 'USBLC6-2';
'I/O1'<0>:'(1)';BIDI;
'I/O2'<0>:'(3)';BIDI;
'I/O1'<1>:'(6)';BIDI;
'I/O2'<1>:'(4)';BIDI;
'GND':'(2)';
'VBUS':'(5)';
end_primitive;
END.
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstpin.dat,3 0 → 100644
View file @ 679c6aed
FILE_TYPE=PINLIST;
{ Packager-XL run on 08-Jun-2016 AT 14:50:07 }
TIME=' COMPILATION ON 08-Jun-2016 AT 14:50:07';
primitive '1-HOLE_0-8-BASE';body '1-HOLE';
'A'<0>:'(1)';IN;
end_primitive;
primitive 'BF-100.000MBE-T-GND=GND_SIGNALA';body 'OSC_6P_ENDIS_OUTP_OUTN';
'ENDIS':'(1)';IN;
'OUTP':'(4)';OUT;
'OUTN':'(5)';OUT;
end_primitive;
primitive 'CAPCERSMDCL2_0402-100NF,16V_GEN';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0603-100NF,16V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0603-10UF,6.3V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_0805-22UF,6.3V';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPCERSMDCL2_1210-10UF,10V_GEN';body 'CAPCERSMDCL2';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'CAPN4I-1UF,16V,X5R,GNM21';body 'CAPN4I';
'B'<0>:'(2,4,6,8)';$S;BIDI;
'A'<0>:'(1,3,5,7)';$S;BIDI;
end_primitive;
primitive 'COMMON_MODE_LINE_FILTER_4312-7A';body 'COMMON_MODE_LINE_FILTER';
'1DOT'<0>:'(4)';
'1'<0>:'(3)';
'2DOT'<0>:'(1)';
'2'<0>:'(2)';
end_primitive;
primitive 'CON3P-SIL254D';body 'CON3P';
'A'<2>:'(3)';
'A'<1>:'(2)';
'A'<0>:'(1)';
end_primitive;
primitive 'DS92001TLD-GND=GND_SIGNAL,VCC=A';body 'DS92001';
'IN-':'(2)';IN;
'IN+':'(3)';IN;
'OUT+':'(6)';OUT;
'OUT-':'(7)';OUT;
'EN':'(8)';IN;
end_primitive;
primitive 'DS92001TLD-GND=GND_SIGNAL,VCC=B';body 'DS92001';
'IN-':'(2)';IN;
'IN+':'(3)';IN;
'OUT+':'(6)';OUT;
'OUT-':'(7)';OUT;
'EN':'(8)';IN;
end_primitive;
primitive 'FERRITE_C0805-LI0805H121R-10,LA';body 'FERRITE';
'B'<0>:'(2)';BIDI;
'A'<0>:'(1)';BIDI;
end_primitive;
primitive 'LP38692SD_WSON-1.8V,TEXAS INSTA';body 'LP38692SD';
'SNS':'(5)';IN;
'OUT':'(4)';OUT;
'IN1':'(1)';IN;
'IN2':'(6)';IN;
'EN':'(3)';IN;
'GND':'(2)';
'DAP':'(7)';
end_primitive;
primitive 'PLEMO2CI-EPG.00.302.NLN-GND=GNA';body 'PLEMO2CI';
'A':'(1)';
'B':'(2)';
end_primitive;
primitive 'RES_ARRAY_X4_1206_TC164-47,1%';body 'RES_ARRAY_X4';
'B'<0>:'(5,6,7,8)';$S;IN;
'A'<0>:'(4,3,2,1)';$S;IN;
end_primitive;
primitive 'RSMD0603_1/10W-100,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-1K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-4.7K,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'RSMD0603_1/10W-XX,1%';body 'RSMD0603';
'A'<0>:'(1)';BIDI;
'B'<0>:'(2)';BIDI;
end_primitive;
primitive 'SI5345A-B-GM-GND=GND_SIGNAL,VDA';body 'SI5345';
'A0/CS':'(19)';IN;
'A1/SDO':'(17)';BIDI;
'FDEC':'(25)';IN;
'FINC':'(48)';IN;
'I2C_SEL':'(39)';IN;
'IN0':'(63)';IN;
'IN0*':'(64)';IN;
'IN1':'(1)';IN;
'IN1*':'(2)';IN;
'IN2':'(14)';IN;
'IN2*':'(15)';IN;
'IN3/FB_IN':'(61)';IN;
'IN3/FB_IN*':'(62)';IN;
'INTR*':'(12)';OUT;
'IN_SEL0':'(3)';IN;
'IN_SEL1':'(4)';IN;
'LOL*':'(47)';OUT;
'OE*':'(11)';IN;
'OUT0':'(24)';OUT;
'OUT0*':'(23)';OUT;
'OUT1':'(28)';OUT;
'OUT1*':'(27)';OUT;
'OUT2':'(31)';OUT;
'OUT2*':'(30)';OUT;
'OUT3':'(35)';OUT;
'OUT3*':'(34)';OUT;
'OUT4':'(38)';OUT;
'OUT4*':'(37)';OUT;
'OUT5':'(42)';OUT;
'OUT5*':'(41)';OUT;
'OUT6':'(45)';OUT;
'OUT6*':'(44)';OUT;
'OUT7':'(51)';OUT;
'OUT7*':'(50)';OUT;
'OUT8':'(54)';OUT;
'OUT8*':'(53)';OUT;
'OUT9':'(59)';OUT;
'OUT9*':'(58)';OUT;
'RST*':'(6)';IN;
'RSVD1':'(5)';
'RSVD2':'(20)';
'RSVD3':'(21)';
'RSVD4':'(55)';
'RSVD5':'(56)';
'SCLK':'(16)';IN;
'SDA/SDIO':'(18)';BIDI;
'VDDO0':'(22)';
'VDDO1':'(26)';
'VDDO2':'(29)';
'VDDO3':'(33)';
'VDDO4':'(36)';
'VDDO5':'(40)';
'VDDO6':'(43)';
'VDDO7':'(49)';
'VDDO8':'(52)';
'VDDO9':'(57)';
'X1':'(7)';IN;
'X2':'(10)';IN;
'XA':'(8)';IN;
'XB':'(9)';IN;
end_primitive;
primitive 'SN65MLVD040RGZ-GND=GND_SIGNAL,A';body 'SN65MLVD040';
'DE'<0>:'(1,5,8,12)';$S;IN;
'D'<0>:'(35,32,28,25)';$S;IN;
'R'<0>:'(36,33,29,26)';$S;OUT;
'A'<0>:'(47,3,9,13)';$S;OUT;
'B*'<0>:'(48,4,10,14)';$S;OUT;
'RE*'<0>:'(40,42,19,21)';$S;IN;
'FSEN'<0>:'(39,41,20,22)';$S;IN;
'PDN':'(30,30,30,30)';IN;
end_primitive;
primitive 'USBLC6-2SC6'; body 'USBLC6-2';
'I/O1'<0>:'(1)';BIDI;
'I/O2'<0>:'(3)';BIDI;
'I/O1'<1>:'(6)';BIDI;
'I/O2'<1>:'(4)';BIDI;
'GND':'(2)';
'VBUS':'(5)';
end_primitive;
END.
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstrprt.dat 0 → 100644
View file @ 679c6aed
- SPARES LIST -
CAPN4I-1UF,16V,X5R,GNM21
CN2 2, 3, 4
RES_ARRAY_X4_1206_TC164-47,1%
RN3 3, 4
- PART SUMMARY -
1-HOLE_0-8-BASE 4
BF-100.000MBE-T-GND=GND_SIGNALA BF-100.000MBE-T 1
CAPCERSMDCL2_0402-100NF,16V_GEN CC0402_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0603-100NF,16V CC0603_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0603-10UF,6.3V CC0603_10UF_6V3_20%_X5R 5
CAPCERSMDCL2_0805-22UF,6.3V CC0805_22UF_6V3_15%_X7R 2
CAPCERSMDCL2_1210-10UF,10V_GEN CC1210_10UF_25V_10%_X5R 1
CAPN4I-1UF,16V,X5R,GNM21 GNM214B11C105MA01D 2
COMMON_MODE_LINE_FILTER_4312-7A 744231091 5
CON3P-SIL254D MTLW-103-07-L-S-250 1
DS92001TLD-GND=GND_SIGNAL,VCC=A DS92001TLD 1
DS92001TLD-GND=GND_SIGNAL,VCC=B DS92001TLD 5
FERRITE_C0805-LI0805H121R-10,LA LI0805H121R-10 3
LP38692SD_WSON-1.8V,TEXAS INSTA LP38692SD-1.8 1
PLEMO2CI-EPG.00.302.NLN-GND=GNA EPG.00.302.NLN 1
RES_ARRAY_X4_1206_TC164-47,1% TC164-FR-##47RL 3
RSMD0603_1/10W-100,1% R0603_100R_1%_0.1W_100PPM 10
RSMD0603_1/10W-1K,1% R0603_1K_1%_0.1W_100PPM 12
RSMD0603_1/10W-4.7K,1% R0603_4K7_1%_0.1W_100PPM 1
RSMD0603_1/10W-XX,1% R0603_XX_1%_0.1W_100PPM 2
SI5345A-B-GM-GND=GND_SIGNAL,VDA Si5345A-B-GM 1
SN65MLVD040RGZ-GND=GND_SIGNAL,A SN65MLVD040RGZ 1
USBLC6-2SC6 USBLC6-2SC6 1
Total 81
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstrprt.dat,1 0 → 100644
View file @ 679c6aed
- SPARES LIST -
CAPN4I-1UF,16V,X5R,GNM21
CN2 2, 3, 4
RES_ARRAY_X4_1206_TC164-47,1%
RN3 3, 4
- PART SUMMARY -
1-HOLE_0-8-BASE 4
BF-100.000MBE-T-GND=GND_SIGNALA BF-100.000MBE-T 1
CAPCERSMDCL2_0402-100NF,16V_GEN CC0402_100NF_16V_10%_X7R 7
CAPCERSMDCL2_0603-100NF,16V CC0603_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0603-10UF,6.3V CC0603_10UF_6V3_20%_X5R 4
CAPCERSMDCL2_0805-22UF,6.3V CC0805_22UF_6V3_15%_X7R 2
CAPCERSMDCL2_1210-10UF,10V_GEN CC1210_10UF_25V_10%_X5R 1
CAPN4I-1UF,16V,X5R,GNM21 GNM214B11C105MA01D 2
COMMON_MODE_LINE_FILTER_4312-7A 744231091 5
CON3P-SIL254D MTLW-103-07-L-S-250 1
DS92001TLD-GND=GND_SIGNAL,VCC=A DS92001TLD 1
DS92001TLD-GND=GND_SIGNAL,VCC=B DS92001TLD 5
FERRITE_C0805-LI0805H121R-10,LA LI0805H121R-10 3
LP38692SD_WSON-1.8V,TEXAS INSTA LP38692SD-1.8 1
PLEMO2CI-EPG.00.302.NLN-GND=GNA EPG.00.302.NLN 1
RES_ARRAY_X4_1206_TC164-47,1% TC164-FR-##47RL 3
RSMD0603_1/10W-100,1% R0603_100R_1%_0.1W_100PPM 12
RSMD0603_1/10W-1K,1% R0603_1K_1%_0.1W_100PPM 12
RSMD0603_1/10W-4.7K,1% R0603_4K7_1%_0.1W_100PPM 1
SI5345A-B-GM-GND=GND_SIGNAL,VDA Si5345A-B-GM 1
SN65MLVD040RGZ-GND=GND_SIGNAL,A SN65MLVD040RGZ 1
USBLC6-2SC6 USBLC6-2SC6 1
Total 78
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstrprt.dat,2 0 → 100644
View file @ 679c6aed
- SPARES LIST -
CAPN4I-1UF,16V,X5R,GNM21
CN2 3, 4
- PART SUMMARY -
1-HOLE_0-8-BASE 4
BF-100.000MBE-T-GND=GND_SIGNALA BF-100.000MBE-T 1
CAPCERSMDCL2_0402-100NF,16V_GEN CC0402_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0603-100NF,16V CC0603_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0603-10UF,6.3V CC0603_10UF_6V3_20%_X5R 5
CAPCERSMDCL2_0805-22UF,6.3V CC0805_22UF_6V3_15%_X7R 2
CAPCERSMDCL2_1210-10UF,10V_GEN CC1210_10UF_25V_10%_X5R 1
CAPN4I-1UF,16V,X5R,GNM21 GNM214B11C105MA01D 2
COMMON_MODE_LINE_FILTER_4312-7A 744231091 6
CON3P-SIL254D MTLW-103-07-L-S-250 1
DS92001TLD-GND=GND_SIGNAL,VCC=A DS92001TLD 1
DS92001TLD-GND=GND_SIGNAL,VCC=B DS92001TLD 5
FERRITE_C0805-LI0805H121R-10,LA LI0805H121R-10 3
LP38692SD_WSON-1.8V,TEXAS INSTA LP38692SD-1.8 1
PLEMO2CI-EPG.00.302.NLN-GND=GNA EPG.00.302.NLN 1
RES_ARRAY_X4_1206_TC164-47,1% TC164-FR-##47RL 3
RSMD0603_1/10W-100,1% R0603_100R_1%_0.1W_100PPM 10
RSMD0603_1/10W-1K,1% R0603_1K_1%_0.1W_100PPM 12
RSMD0603_1/10W-4.7K,1% R0603_4K7_1%_0.1W_100PPM 1
RSMD0603_1/10W-XX,1% R0603_XX_1%_0.1W_100PPM 2
SI5345A-B-GM-GND=GND_SIGNAL,VDA Si5345A-B-GM 1
SN65MLVD040RGZ-GND=GND_SIGNAL,A SN65MLVD040RGZ 1
USBLC6-2SC6 USBLC6-2SC6 1
Total 82
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstrprt.dat,3 0 → 100644
View file @ 679c6aed
- SPARES LIST -
CAPN4I-1UF,16V,X5R,GNM21
CN2 2, 3, 4
RES_ARRAY_X4_1206_TC164-47,1%
RN3 3, 4
- PART SUMMARY -
1-HOLE_0-8-BASE 4
BF-100.000MBE-T-GND=GND_SIGNALA BF-100.000MBE-T 1
CAPCERSMDCL2_0402-100NF,16V_GEN CC0402_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0603-100NF,16V CC0603_100NF_16V_10%_X7R 9
CAPCERSMDCL2_0603-10UF,6.3V CC0603_10UF_6V3_20%_X5R 5
CAPCERSMDCL2_0805-22UF,6.3V CC0805_22UF_6V3_15%_X7R 2
CAPCERSMDCL2_1210-10UF,10V_GEN CC1210_10UF_25V_10%_X5R 1
CAPN4I-1UF,16V,X5R,GNM21 GNM214B11C105MA01D 2
COMMON_MODE_LINE_FILTER_4312-7A 744231091 5
CON3P-SIL254D MTLW-103-07-L-S-250 1
DS92001TLD-GND=GND_SIGNAL,VCC=A DS92001TLD 1
DS92001TLD-GND=GND_SIGNAL,VCC=B DS92001TLD 5
FERRITE_C0805-LI0805H121R-10,LA LI0805H121R-10 3
LP38692SD_WSON-1.8V,TEXAS INSTA LP38692SD-1.8 1
PLEMO2CI-EPG.00.302.NLN-GND=GNA EPG.00.302.NLN 1
RES_ARRAY_X4_1206_TC164-47,1% TC164-FR-##47RL 3
RSMD0603_1/10W-100,1% R0603_100R_1%_0.1W_100PPM 10
RSMD0603_1/10W-1K,1% R0603_1K_1%_0.1W_100PPM 12
RSMD0603_1/10W-4.7K,1% R0603_4K7_1%_0.1W_100PPM 1
RSMD0603_1/10W-XX,1% R0603_XX_1%_0.1W_100PPM 2
SI5345A-B-GM-GND=GND_SIGNAL,VDA Si5345A-B-GM 1
SN65MLVD040RGZ-GND=GND_SIGNAL,A SN65MLVD040RGZ 1
USBLC6-2SC6 USBLC6-2SC6 1
Total 81
Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxnet.dat 0 → 100644
View file @ 679c6aed
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Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxprt.dat 0 → 100644
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Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxprt.dat,2 0 → 100644
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Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxprt.dat,3 0 → 100644
View file @ 679c6aed
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Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxref.dat 0 → 100644
View file @ 679c6aed
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Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxref.dat,2 0 → 100644
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Cadence/worklib/fmc_tlu_clock_gen/packaged/pstxref.dat,3 0 → 100644
View file @ 679c6aed
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Cadence/worklib/fmc_tlu_clock_gen/packaged/pxl.chg 0 → 100644
View file @ 679c6aed
This diff is collapsed.
Cadence/worklib/fmc_tlu_clock_gen/packaged/pxl.chg,1 0 → 100644
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Cadence/worklib/fmc_tlu_clock_gen/packaged/pxl.chg,2 0 → 100644
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Cadence/worklib/fmc_tlu_clock_gen/packaged/pxl.dbg 0 → 100644
View file @ 679c6aed
Log File: /tmp/filegMCvY7
Markers File: /tmp/fileHZSdFZ
Debug File: /tmp/file4IEOiJ
Debug[0] := TRUE
Elapsed time since start = (00:00:01)
**************************************************************
* End processing project file and command line (00:00:00) *
**************************************************************
****************************************
* Starting to assign physical parts. *
****************************************
Elapsed time since start = (00:00:01)
***********************************************
* End assigning physical parts. (00:00:00) *
***********************************************
***************
* Packaging *
***************
Elapsed time since start = (00:00:01)
*******************************
* End packaging (00:00:00) *
*******************************
3333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333333DDB_INFO: State file for design FMC_TLU_CLOCK_GEN successfully written.
DDB_INFO: Pst files for design FMC_TLU_CLOCK_GEN successfully written.
DDB_INFO: Generating state file for subdesign FMC_TLU_CLOCK_GEN
system time 0
user time 0
Cadence/worklib/fmc_tlu_clock_gen/packaged/pxl.dbg.old 0 → 100644
View file @ 679c6aed
Log File: /tmp/fileU9p1pW
Markers File: /tmp/fileiOmtRA
Debug File: /tmp/file9aeuPT
Debug[0] := TRUE
Elapsed time since start = (00:00:00)
**************************************************************
* End processing project file and command line (00:00:00) *
**************************************************************
system time 0
user time 0
**************************************************
* FATAL ERROR PackagerXL exiting with status 2 *
**************************************************
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(marker_file
(version 5.0)
(markers
(
(tool "Packager-XL")
(class "LOGICAL")
(severity 40)
(error_num 563)
(short_msg "ERROR(SPCODD-563): Following blocks have netlisting errors. Fix them in Design Entry HDL before packaging: fmc_tlu_clock_gen")
(long_msg "ERROR(SPCODD-563): Following blocks have netlisting errors. Fix them in Design Entry HDL before packaging: fmc_tlu_clock_gen
")
)
)
)
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